1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017 General Electric Company
4 *
5 * Based on board/freescale/mx53loco/mx53loco.c:
6 *
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jason Liu <r64343@freescale.com>
9 */
10
11 #include <common.h>
12 #include <init.h>
13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/iomux-mx53.h>
19 #include <asm/arch/clock.h>
20 #include <env.h>
21 #include <linux/errno.h>
22 #include <linux/libfdt.h>
23 #include <asm/mach-imx/mxc_i2c.h>
24 #include <asm/mach-imx/mx5_video.h>
25 #include <netdev.h>
26 #include <i2c.h>
27 #include <mmc.h>
28 #include <fsl_esdhc_imx.h>
29 #include <asm/gpio.h>
30 #include <power/pmic.h>
31 #include <dialog_pmic.h>
32 #include <fsl_pmic.h>
33 #include <linux/fb.h>
34 #include <ipu_pixfmt.h>
35 #include <version.h>
36 #include <watchdog.h>
37 #include "ppd_gpio.h"
38 #include <stdlib.h>
39 #include "../../ge/common/ge_common.h"
40 #include "../../ge/common/vpd_reader.h"
41
42 #define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
43
44 DECLARE_GLOBAL_DATA_PTR;
45
46 static u32 mx53_dram_size[2];
47
get_effective_memsize(void)48 phys_size_t get_effective_memsize(void)
49 {
50 /*
51 * WARNING: We must override get_effective_memsize() function here
52 * to report only the size of the first DRAM bank. This is to make
53 * U-Boot relocator place U-Boot into valid memory, that is, at the
54 * end of the first DRAM bank. If we did not override this function
55 * like so, U-Boot would be placed at the address of the first DRAM
56 * bank + total DRAM size - sizeof(uboot), which in the setup where
57 * each DRAM bank contains 512MiB of DRAM would result in placing
58 * U-Boot into invalid memory area close to the end of the first
59 * DRAM bank.
60 */
61 return mx53_dram_size[0];
62 }
63
dram_init(void)64 int dram_init(void)
65 {
66 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
67 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
68
69 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
70
71 return 0;
72 }
73
dram_init_banksize(void)74 int dram_init_banksize(void)
75 {
76 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
77 gd->bd->bi_dram[0].size = mx53_dram_size[0];
78
79 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
80 gd->bd->bi_dram[1].size = mx53_dram_size[1];
81
82 return 0;
83 }
84
get_board_rev(void)85 u32 get_board_rev(void)
86 {
87 return get_cpu_rev() & ~(0xF << 8);
88 }
89
90 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
91 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
92
93 #ifdef CONFIG_USB_EHCI_MX5
board_ehci_hcd_init(int port)94 int board_ehci_hcd_init(int port)
95 {
96 /* request VBUS power enable pin, GPIO7_8 */
97 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
98 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
99 return 0;
100 }
101 #endif
102
setup_iomux_fec(void)103 static void setup_iomux_fec(void)
104 {
105 static const iomux_v3_cfg_t fec_pads[] = {
106 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
107 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
108 PAD_CTL_ODE),
109 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
110 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
111 PAD_CTL_HYS | PAD_CTL_PKE),
112 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
113 PAD_CTL_HYS | PAD_CTL_PKE),
114 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
115 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
116 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
117 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
118 PAD_CTL_HYS | PAD_CTL_PKE),
119 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
120 PAD_CTL_HYS | PAD_CTL_PKE),
121 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
122 PAD_CTL_HYS | PAD_CTL_PKE),
123 };
124
125 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
126 }
127
128 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
129 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
130
setup_iomux_i2c(void)131 static void setup_iomux_i2c(void)
132 {
133 static const iomux_v3_cfg_t i2c1_pads[] = {
134 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
135 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
136 };
137
138 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
139 }
140
141 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
142
143 static struct i2c_pads_info i2c_pad_info1 = {
144 .scl = {
145 .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
146 .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
147 .gp = IMX_GPIO_NR(3, 28)
148 },
149 .sda = {
150 .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
151 .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
152 .gp = IMX_GPIO_NR(3, 21)
153 }
154 };
155
clock_1GHz(void)156 static int clock_1GHz(void)
157 {
158 int ret;
159 u32 ref_clk = MXC_HCLK;
160 /*
161 * After increasing voltage to 1.25V, we can switch
162 * CPU clock to 1GHz and DDR to 400MHz safely
163 */
164 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
165 if (ret) {
166 printf("CPU: Switch CPU clock to 1GHZ failed\n");
167 return -1;
168 }
169
170 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
171 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
172 if (ret) {
173 printf("CPU: Switch DDR clock to 400MHz failed\n");
174 return -1;
175 }
176
177 return 0;
178 }
179
ppd_gpio_init(void)180 void ppd_gpio_init(void)
181 {
182 int i;
183
184 imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
185 for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
186 gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
187 }
188
board_early_init_f(void)189 int board_early_init_f(void)
190 {
191 setup_iomux_fec();
192 setup_iomux_lcd();
193 ppd_gpio_init();
194
195 return 0;
196 }
197
198 /*
199 * Do not overwrite the console
200 * Use always serial for U-Boot console
201 */
overwrite_console(void)202 int overwrite_console(void)
203 {
204 return 1;
205 }
206
207 #define VPD_TYPE_INVALID 0x00
208 #define VPD_BLOCK_NETWORK 0x20
209 #define VPD_BLOCK_HWID 0x44
210 #define VPD_PRODUCT_PPD 4
211 #define VPD_HAS_MAC1 0x1
212 #define VPD_MAC_ADDRESS_LENGTH 6
213
214 struct vpd_cache {
215 u8 product_id;
216 u8 has;
217 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
218 };
219
220 /*
221 * Extracts MAC and product information from the VPD.
222 */
vpd_callback(struct vpd_cache * userdata,u8 id,u8 version,u8 type,size_t size,u8 const * data)223 static int vpd_callback(struct vpd_cache *userdata, u8 id, u8 version,
224 u8 type, size_t size, u8 const *data)
225 {
226 struct vpd_cache *vpd = userdata;
227
228 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
229 size >= 1) {
230 vpd->product_id = data[0];
231
232 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
233 type != VPD_TYPE_INVALID) {
234 if (size >= 6) {
235 vpd->has |= VPD_HAS_MAC1;
236 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
237 }
238 }
239
240 return 0;
241 }
242
process_vpd(struct vpd_cache * vpd)243 static void process_vpd(struct vpd_cache *vpd)
244 {
245 int fec_index = -1;
246
247 if (vpd->product_id == VPD_PRODUCT_PPD)
248 fec_index = 0;
249
250 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
251 eth_env_set_enetaddr("ethaddr", vpd->mac1);
252 }
253
board_init(void)254 int board_init(void)
255 {
256 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
257
258 mxc_set_sata_internal_clock();
259 setup_iomux_i2c();
260
261 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
262
263 return 0;
264 }
265
misc_init_r(void)266 int misc_init_r(void)
267 {
268 const char *cause;
269
270 /* We care about WDOG only, treating everything else as
271 * a power-on-reset.
272 */
273 if (get_imx_reset_cause() & 0x0010)
274 cause = "WDOG";
275 else
276 cause = "POR";
277
278 env_set("bootcause", cause);
279
280 return 0;
281 }
282
board_late_init(void)283 int board_late_init(void)
284 {
285 int res;
286 struct vpd_cache vpd;
287
288 memset(&vpd, 0, sizeof(vpd));
289 res = read_vpd(&vpd, vpd_callback);
290 if (!res)
291 process_vpd(&vpd);
292 else
293 printf("Can't read VPD");
294
295 res = clock_1GHz();
296 if (res != 0)
297 return res;
298
299 print_cpuinfo();
300 hw_watchdog_init();
301
302 check_time();
303
304 return 0;
305 }
306
checkboard(void)307 int checkboard(void)
308 {
309 puts("Board: GE PPD\n");
310
311 return 0;
312 }
313
314 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)315 int ft_board_setup(void *blob, bd_t *bd)
316 {
317 fdt_setprop(blob, 0, "ge,boot-ver", version_string,
318 strlen(version_string) + 1);
319 return 0;
320 }
321 #endif
322