1 /*
2 * hi3519av100_amp.c
3 *
4 * The board init for hisilicon
5 *
6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22 #include "../../../lib/hw_dec/hw_decompress_v2.h"
23 #include <config.h>
24 #include <common.h>
25 #include <command.h>
26 #include <asm/io.h>
27 #include <asm/arch/platform.h>
28 #include <spi_flash.h>
29 #include <linux/mtd/mtd.h>
30 #include <nand.h>
31 #include <netdev.h>
32 #include <mmc.h>
33 #include <sdhci.h>
34 #include <blk.h>
35 #include <hicpu_common.h>
36 #include <asm/mach-types.h>
37
38 #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)39 void enable_caches(void)
40 {
41 /* Enable D-cache. I-cache is already enabled in start.S */
42 dcache_enable();
43 }
44 #endif
45
46 static int boot_media = BOOT_MEDIA_UNKNOWN;
47
48 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)49 void show_boot_progress(int progress)
50 {
51 printf("Boot reached stage %d\n", progress);
52 }
53 #endif
54
55 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
56
delay(unsigned long loops)57 static inline void delay(unsigned long loops)
58 {
59 __asm__ volatile("1:\n"
60 "subs %0, %1, #1\n"
61 "bne 1b" : "=r"(loops) : "0"(loops));
62 }
63
64 /* get uboot start media. */
get_boot_media(void)65 int get_boot_media(void)
66 {
67 return boot_media;
68 }
69
get_text_base(void)70 int get_text_base(void)
71 {
72 return CONFIG_SYS_TEXT_BASE;
73 }
74
boot_flag_init(void)75 static void boot_flag_init(void)
76 {
77 unsigned int regval, boot_mode;
78
79 /* get boot mode */
80 regval = __raw_readl(SYS_CTRL_REG_BASE + REG_SYSSTAT);
81 boot_mode = get_sys_boot_mode(regval);
82
83 switch (boot_mode) {
84 /* [5:4] 00b - boot from spi device */
85 case BOOT_FROM_SPI:
86 if (get_spi_device_type(regval))
87 boot_media = BOOT_MEDIA_NAND;
88 else
89 boot_media = BOOT_MEDIA_SPIFLASH;
90 break;
91 /* [5:4] 01b - boot from spi nand device */
92 case BOOT_FROM_SPI_NAND:
93 boot_media = BOOT_MEDIA_NAND;
94 break;
95 /* [5:4] 01b - boot from Nand device */
96 case BOOT_FROM_NAND:
97 boot_media = BOOT_MEDIA_NAND;
98 break;
99 /* [5:4] 10b - boot from emmc */
100 case BOOT_FROM_EMMC:
101 boot_media = BOOT_MEDIA_EMMC;
102 break;
103 default:
104 boot_media = BOOT_MEDIA_UNKNOWN;
105 break;
106 }
107 }
108
board_early_init_f(void)109 int board_early_init_f(void)
110 {
111 return 0;
112 }
113
114
115 #define UBOOT_DATA_ADDR 0x21000000UL
116 #define UBOOT_DATA_SIZE 0x80000UL
data_to_spiflash(void)117 int data_to_spiflash(void)
118 {
119 static struct spi_flash *flash = NULL;
120 void *buf = NULL;
121 unsigned int val;
122
123 /* 0:bus; 0:cs 1000000:max_hz 0x3:spi_mode */
124 flash = spi_flash_probe(0, 0, 1000000, 0x3);
125 if (!flash) {
126 printf("Failed to initialize SPI flash\n");
127 return -1; /* -1:failed */
128 }
129
130 /* erase the address range. */
131 printf("Spi flash erase...\n");
132 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE);
133 if (val) {
134 printf("SPI flash sector erase failed\n");
135 return 1; /* 1:failed */
136 }
137
138 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
139 UBOOT_DATA_SIZE, MAP_WRBACK);
140 if (!buf) {
141 puts("Failed to map physical memory\n");
142 return 1; /* 1:failed */
143 }
144
145 /* copy the data from RAM to FLASH */
146 printf("Spi flash write...\n");
147 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf);
148 if (val) {
149 printf("SPI flash write failed, return %u\n",
150 val);
151 unmap_physmem(buf, UBOOT_DATA_SIZE);
152 return 1; /* 1:failed */
153 }
154
155 unmap_physmem(buf, UBOOT_DATA_SIZE);
156 return 0; /* 0:success */
157 }
158
data_to_nandflash(void)159 int data_to_nandflash(void)
160 {
161 struct mtd_info *nand_flash = NULL;
162 void *buf = NULL;
163 size_t length = UBOOT_DATA_SIZE;
164 unsigned int val;
165
166 nand_flash = nand_info[0];
167
168 printf("Nand flash erase...\n");
169 val = nand_erase(nand_flash, 0, UBOOT_DATA_SIZE);
170 if (val) {
171 printf("Nand flash erase failed\n");
172 return 1;
173 }
174
175 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
176 UBOOT_DATA_SIZE, MAP_WRBACK);
177 if (!buf) {
178 puts("Failed to map physical memory\n");
179 return 1;
180 }
181
182 printf("Nand flash write...\n");
183 val = nand_write(nand_flash, 0, &length, buf);
184 if (val) {
185 printf("Nand flash write failed, return %u\n",
186 val);
187 unmap_physmem(buf, UBOOT_DATA_SIZE);
188 return 1;
189 }
190
191 unmap_physmem(buf, UBOOT_DATA_SIZE);
192 return 0;
193 }
194
data_to_emmc(void)195 int data_to_emmc(void)
196 {
197 struct mmc *mmc = find_mmc_device(0);
198 void *buf = NULL;
199
200 if (!mmc)
201 return 1;
202
203 (void)mmc_init(mmc);
204
205 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
206 UBOOT_DATA_SIZE, MAP_WRBACK);
207 if (!buf) {
208 puts("Failed to map physical memory\n");
209 return 1;
210 }
211
212 printf("MMC write...\n");
213 blk_dwrite(mmc_get_blk_desc(mmc), 0, (UBOOT_DATA_SIZE >> NUM_9), buf);
214 unmap_physmem(buf, UBOOT_DATA_SIZE);
215 return 0;
216 }
save_bootdata_to_flash(void)217 int save_bootdata_to_flash(void)
218 {
219 unsigned int sd_update_flag = 0;
220 int ret = 0;
221 sd_update_flag = readl(REG_BASE_SCTL + REG_SC_GEN4);
222 if (sd_update_flag == START_MAGIC) {
223 #if defined(CONFIG_HIFMC)
224 if (boot_media == BOOT_MEDIA_SPIFLASH) {
225 ret = data_to_spiflash();
226 if (ret != 0)
227 return ret;
228 }
229 if (boot_media == BOOT_MEDIA_NAND) {
230 ret = data_to_nandflash();
231 if (ret != 0)
232 return ret;
233 }
234 #endif
235 #if defined(CONFIG_MMC)
236 if (boot_media == BOOT_MEDIA_EMMC) {
237 ret = data_to_emmc();
238 if (ret != 0)
239 return ret;
240 }
241 #endif
242
243 printf("update success!\n");
244 }
245
246 return 0;
247 }
248
249 int auto_update_flag = 0;
250 int bare_chip_program = 0;
251
252 #define REG_BASE_GPIO4 0x045f4000
253 #define GPIO4_3_DATA_OFST 0x20
254 #define GPIO_DIR_OFST 0x400
255
256 #ifdef CONFIG_TARGET_HI3519AV100
257 /* upgrade status register address */
258 #define UPGRADE_STATUS_REG_ADDR (0x04590048)
259
260 typedef enum tagUPGRADE_STATUS_E {
261 UPGRADE_STATUS_IDLE = 0,
262 UPGRADE_STATUS_PROCESSING,
263 UPGRADE_STATUS_FINISH,
264 UPGRADE_STATUS_BUTT
265 } upgrade_status_e;
266 #endif
267
is_bare_program(void)268 int is_bare_program(void)
269 {
270 return 1;
271 }
272
273 #if (CONFIG_AUTO_UPDATE == 1)
is_auto_update(void)274 int is_auto_update(void)
275 {
276 #if (defined CONFIG_AUTO_SD_UPDATE) || (defined CONFIG_AUTO_USB_UPDATE)
277 /* to add some judgement if neccessary */
278 unsigned int val[NUM_3];
279
280 #ifdef CONFIG_TARGET_HI3519AV100
281 unsigned int *puregval = (unsigned int *)UPGRADE_STATUS_REG_ADDR;
282 if (((*puregval) & (UPGRADE_STATUS_PROCESSING)) != 0)
283 return 1; /* update enable */
284 #endif
285
286 writel(0, REG_BASE_GPIO4 + GPIO_DIR_OFST);
287
288 val[NUM_0] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST);
289 if (val[NUM_0])
290 return 0;
291
292 udelay(10000); /* delay 10000 us */
293 val[NUM_1] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST);
294 udelay(10000); /* delay 10000 us */
295 val[NUM_2] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST);
296 udelay(10000); /* delay 10000 us */
297
298 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0)
299 return 1; /* update enable */
300 else
301 return 0;
302
303 #else
304 return 0;
305 #endif
306 }
307 #endif /* CONFIG_AUTO_UPDATE */
308
309 #ifdef CONFIG_TARGET_HI3519AV100
310 struct boot_medium_interface {
311 char name[0x10]; /* 0x10:name len */
312 int (*init)(void);
313 int (*read)(unsigned long offset, unsigned long len, void *buf);
314 };
315
316 /* spi nand configure */
317 #if defined(CONFIG_HIFMC_SPI_NAND)|| defined(CONFIG_HIFMC_NAND)
318 #define NAND_MAX_SIZE 0xFFFFFFFF
nand_flash_read(unsigned long offset,unsigned long len,void * buf)319 static int nand_flash_read(unsigned long offset, unsigned long len, void *buf)
320 {
321 struct mtd_info *mtd = nand_info[NUM_0];
322 size_t rwsize = len;
323 return nand_read_skip_bad(mtd, offset, &rwsize, NULL, NAND_MAX_SIZE,
324 (unsigned char *)buf);
325 }
326 #endif
327
328 #ifdef CONFIG_HIFMC_SPI_NOR /* spi nor configure */
329 struct spi_flash *spiflash;
330
331 #include "spi_flash.h"
spinor_flash_read(unsigned long offset,unsigned long len,void * buf)332 static int spinor_flash_read(unsigned long offset, unsigned long len, void *buf)
333 {
334 /* 0,0,0,0:bus,cs,max_hz,spi_mode */
335 spiflash = spi_flash_probe(0, 0, 0, 0);
336 if (!spiflash)
337 printf("spiflash is null!\n");
338 spi_flash_read(spiflash, offset, len, buf);
339 return 0;
340 }
341 #endif
342
343 #ifdef CONFIG_MMC
mmc_read_data(unsigned long offset,unsigned long len,void * buf)344 static int mmc_read_data(unsigned long offset, unsigned long len, void *buf)
345 {
346 unsigned long ret;
347 struct mmc *mmc = find_mmc_device(0);
348 if (!mmc)
349 return 1;
350 (void)mmc_init(mmc);
351 ret = blk_dread(mmc_get_blk_desc(mmc), offset, len, buf);
352 return ret;
353 }
354 #endif
355
356
357 static struct boot_medium_interface boot_intf[NUM_1] = {0};
358 static struct boot_medium_interface *boot_intf_p;
359
boot_medium_init(void)360 void boot_medium_init(void)
361 {
362 /* register boot media interface */
363 if (get_boot_media() == BOOT_MEDIA_SPIFLASH) {
364 printf("boot_media spinor!\n");
365 boot_intf[NUM_0].init = NULL;
366 #ifdef CONFIG_HIFMC_SPI_NOR
367 boot_intf[NUM_0].read = spinor_flash_read;
368 #endif
369 strncpy(boot_intf[NUM_0].name, "spinor", sizeof(boot_intf[NUM_0].name));
370 } else if (get_boot_media() == BOOT_MEDIA_NAND) {
371 printf("boot_media nand!\n");
372 boot_intf[NUM_0].init = NULL;
373 #if defined(CONFIG_HIFMC_SPI_NAND)|| defined(CONFIG_HIFMC_NAND)
374 boot_intf[NUM_0].read = nand_flash_read;
375 #endif
376 strncpy(boot_intf[NUM_0].name, "nand", sizeof(boot_intf[NUM_0].name));
377 } else if (get_boot_media() == BOOT_MEDIA_EMMC) {
378 printf("boot_media emmc!\n");
379 boot_intf[NUM_0].init = NULL;
380 #ifdef CONFIG_MMC
381 boot_intf[NUM_0].read = mmc_read_data;
382 #endif
383 strncpy(boot_intf[NUM_0].name, "emmc", sizeof(boot_intf[NUM_0].name));
384 } else {
385 printf("boot_media unkonw error !\n");
386 }
387
388 boot_intf_p = &boot_intf[NUM_0];
389
390 /* boot media init */
391 if (boot_intf_p->init)
392 boot_intf_p->init();
393 }
394 #endif
395
select_upgrade_dev(void)396 void select_upgrade_dev(void)
397 {
398 #ifdef CONFIG_EMMC
399 unsigned int uval = readl(UPGRADE_STATUS_REG_ADDR);
400 unsigned int stor_dev = 0;
401 unsigned int stor_paration = 0;
402 stor_dev = (uval >> 16) & 0x03; /* 16,0x03: store dev */
403 stor_paration = (uval >> 18) & 0x1f; /* 18,0x1f: store paration */
404 if (((uval) & (UPGRADE_STATUS_PROCESSING)) != NUM_0) {
405 /* the upgrade startup by linux application */
406 if (stor_dev == NUM_0) {
407 /* emmc */
408 target_dev = NUM_0;
409 target_paratition = stor_paration;
410 } else {
411 /* sd */
412 target_dev = NUM_1;
413 }
414 } else {
415 /* the upgrade startup by upgrade key on the board, os defaule upgrade style */
416 target_dev = NUM_1;
417 }
418
419 printf("update dev is %d: paratition is %d\n",
420 target_dev, target_paratition);
421 #endif
422 return;
423 }
424
misc_init_r(void)425 int misc_init_r(void)
426 {
427 #ifdef CONFIG_TARGET_HI3519AV100
428 boot_medium_init();
429 #endif
430
431 #ifdef CONFIG_RANDOM_ETHADDR
432 random_init_r();
433 #endif
434 env_set("verify", "n");
435
436 /* bare chip program flag */
437 if (is_bare_program())
438 bare_chip_program = 1;
439 else
440 bare_chip_program = 0;
441
442 #if (CONFIG_AUTO_UPDATE == 1)
443 /* auto update flag */
444 if (is_auto_update())
445 auto_update_flag = 1;
446 else
447 auto_update_flag = 0;
448
449 #ifdef CFG_MMU_HANDLEOK
450 dcache_stop();
451 #endif
452
453 #ifdef CFG_MMU_HANDLEOK
454 dcache_start();
455 #endif
456
457 #endif
458
459 #if (CONFIG_AUTO_UPDATE == 1)
460 if (auto_update_flag) {
461 #ifdef CONFIG_TARGET_HI3519AV100
462 select_upgrade_dev();
463 int result = do_auto_update();
464 if (result == 0) {
465 unsigned int uregval = readl(UPGRADE_STATUS_REG_ADDR);
466 udelay(10000); /* delay 10000 us */
467 if ((uregval & UPGRADE_STATUS_PROCESSING) != NUM_0) {
468 writel(UPGRADE_STATUS_FINISH, UPGRADE_STATUS_REG_ADDR);
469 printf("upgrade status: finish\n");
470 }
471 printf("update success\n");
472 do_reset(NULL, 0, 0, NULL);
473 }
474 #else
475 do_auto_update();
476 #endif
477 }
478
479 #endif
480
481 if (bare_chip_program && !auto_update_flag)
482 save_bootdata_to_flash();
483 return 0;
484 }
485
board_init(void)486 int board_init(void)
487 {
488 DECLARE_GLOBAL_DATA_PTR;
489
490 gd->bd->bi_arch_number = MACH_TYPE_HI3519AV100;
491 gd->bd->bi_boot_params = CFG_BOOT_PARAMS;
492
493 boot_flag_init();
494
495 return 0;
496 }
497
dram_init(void)498 int dram_init(void)
499 {
500 DECLARE_GLOBAL_DATA_PTR;
501
502 gd->ram_size = PHYS_SDRAM_1_SIZE;
503 return 0;
504 }
505
reset_cpu(ulong addr)506 void reset_cpu(ulong addr)
507 {
508 /* 0x12345678:writing any value will cause a reset. */
509 writel(0x12345678, REG_BASE_SCTL + REG_SC_SYSRES);
510 while (1);
511 }
512
timer_init(void)513 int timer_init(void)
514 {
515 /*
516 * Under uboot, 0xffffffff is set to load register,]
517 * timer_clk equals BUSCLK/2/256.
518 * e.g. BUSCLK equals 50M, it will roll back after 0xffffffff/timer_clk
519 * 43980s equals 12hours
520 */
521 __raw_writel(0, CFG_TIMERBASE + REG_TIMER_CONTROL);
522 __raw_writel(~0, CFG_TIMERBASE + REG_TIMER_RELOAD);
523
524 /* 32 bit, periodic */
525 __raw_writel(CFG_TIMER_CTRL, CFG_TIMERBASE + REG_TIMER_CONTROL);
526
527 __raw_writel(0, TIMER8_REG_BASE + REG_TIMER_CONTROL);
528 __raw_writel(~0, TIMER8_REG_BASE + REG_TIMER_RELOAD);
529 /* 32 bit, periodic */
530 __raw_writel(CFG_TIMER_CTRL, TIMER8_REG_BASE + REG_TIMER_CONTROL);
531 return 0;
532 }
533
board_eth_init(bd_t * bis)534 int board_eth_init(bd_t *bis)
535 {
536 int rc = 0;
537
538 #ifdef CONFIG_HIGMACV300_ETH
539 rc = higmac_initialize(bis);
540 #endif
541 return rc;
542 }
543 #ifdef CONFIG_GENERIC_MMC
board_mmc_init(bd_t * bis)544 int board_mmc_init(bd_t *bis)
545 {
546 int ret = 0;
547
548 #ifdef CONFIG_HISI_SDHCI
549
550 #if !defined(CONFIG_HIFMC) || defined(CONFIG_AUTO_SD_UPDATE)
551 int dev_num = 0;
552 #endif
553
554 #ifndef CONFIG_HIFMC
555 ret = hisi_sdhci_add_port(0, EMMC_BASE_REG, MMC_TYPE_MMC);
556 if (!ret) {
557 ret = hisi_mmc_init(dev_num);
558 if (ret)
559 printf("No EMMC device found !\n");
560 }
561 dev_num++;
562 #endif
563
564 #ifdef CONFIG_AUTO_SD_UPDATE
565 if (is_auto_update()) {
566 ret = hisi_sdhci_add_port(1, SDIO0_BASE_REG, MMC_TYPE_SD);
567 if (ret)
568 return ret;
569
570 ret = hisi_mmc_init(dev_num);
571 if (ret)
572 printf("No SD device found !\n");
573 }
574 #endif
575 #endif
576
577 return ret;
578 }
579 #endif
580
581
582 #ifdef CONFIG_SECURE_SCHEME_ENABLE
583
584 /* macros to get secure register's offset address */
585 #define sec_rgn_map_ofst(region_idx) (0x1100 + 0x10 * (region_idx))
586 #define sec_rgn_map_ext_ofst(region_idx) (0x1200 + 0x10 * (region_idx))
587
588 #define sec_rgn_attrib_ofst(region_idx) (0x1104 + 0x10 * (region_idx))
589
590 #define sec_mid_wr_ofst(region_idx) (0x1108 + 0x10 * (region_idx))
591 #define sec_mid_wr_ext_ofst(region_idx) (0x1204 + 0x10 * (region_idx))
592
593 #define sec_mid_rd_ofst(region_idx) (0x110c + 0x10 * (region_idx))
594 #define sec_mid_rd_ext_ofst(region_idx) (0x1208 + 0x10 * (region_idx))
595
596 #define SEC_BYPASS_OFST 0x1004
597 #define SEC_INT_EN_OFST 0x1020
598
599 /* macros for register value */
600 #define SECURITY_ENABLE 0xff
601
602 #define SEC_INV_EN (0x1 << 4)
603 #define SHARE_REGN_EN (0xf)
604 #define SECUR_REGN_EN (0xc)
605 #define NON_SEC_REGN_EN (0x3)
606
607 #define A53CPU0_MID 0xf
608 #define A53CPU1_MID 0x11
609 #define DSP_M0_MID 0x13
610 #define AVSP_M2_MID 0x18
611 #define DSP_M1_MID 0x1c
612
613 #define MID_HIGH_START_BIT 0x20
614 #define FMC_MID 0x21
615 #define EMMC_MID 0x28
616
617 #define IPCM_REGN_WR_MID_MASK ((0x1 << A53CPU0_MID) | (0x1 << A53CPU1_MID))
618 #define IPCM_REGN_RD_MID_MASK IPCM_REGN_WR_MID_MASK
619
620 #define DSP_REGN_WR_MID_MASK ((0x1 << A53CPU0_MID) | (0x1 << DSP_M0_MID)\
621 | (0x1 << AVSP_M2_MID) | (0x1 << DSP_M1_MID))
622 #define DSP_REGN_RD_MID_MASK DSP_REGN_WR_MID_MASK
623
624 #define LITEOS_REGN_WR_MID_MASK (0x1 << A53CPU1_MID)
625 #define LITEOS_REGN_RD_MID_MASK LITEOS_REGN_WR_MID_MASK
626
627 #define LINUX_REGN_WR_MID_MASK ((0x1 << A53CPU0_MID))
628 #define LINUX_REGN_RD_MID_MASK LINUX_REGN_WR_MID_MASK
629
630 #define LINUX_REGN_WR_MID_HIGH_MASK ((0x1 << (FMC_MID - MID_HIGH_START_BIT))\
631 | (0x1 << (EMMC_MID - MID_HIGH_START_BIT)))
632 #define LINUX_REGN_RD_MID_HIGH_MASK LINUX_REGN_WR_MID_HIGH_MASK
633
634 #define REGN_CTRL_ENABLE (0x1 << 31)
635
636 #define IPCM_REGN_HIGH_ADDR 0x2000 /* high 16 bit of address */
637 #define IPCM_REGN_SIZE 0x20 /* 0x20 * 64K Byte */
638
639 #define DSP_REGN_HIGH_ADDR 0x2020 /* high 16 bit of address */
640 #define DSP_REGN_SIZE 0x1e0 /* 0x1e0 * 64K Byte */
641
642 #define LITEOS_REGN_HIGH_ADDR 0x2200 /* high 16 bit of address */
643 #define LITEOS_REGN_SIZE 0x1000 /* 0x1000 * 64K Byte */
644
645 #define LINUX_REGN_HIGH_ADDR 0x3200 /* high 16 bit of address */
646 #define LINUX_REGN_SIZE 0x1000 /* 0x1000 * 64K Byte */
647
648 #define IPCM_DDR_REGN_IDX 1
649 #define DSP_DDR_REGN_IDX 2
650 #define LITEOS_DDR_REGN_IDX 3
651 #define LINUX_DDR_REGN_IDX 4
652
ipcm_tzasc_init(void)653 static void ipcm_tzasc_init(void)
654 {
655 /* Set the share access authority */
656 writel(SEC_INV_EN | SHARE_REGN_EN,
657 DDRC0_REG_BASE + sec_rgn_attrib_ofst(IPCM_DDR_REGN_IDX));
658
659 /* Set the master id mask of write command */
660 writel(IPCM_REGN_WR_MID_MASK,
661 DDRC0_REG_BASE + sec_mid_wr_ofst(IPCM_DDR_REGN_IDX));
662 writel(0, DDRC0_REG_BASE + sec_mid_wr_ext_ofst(IPCM_DDR_REGN_IDX));
663
664 /* Set the master id mask of read command */
665 writel(IPCM_REGN_RD_MID_MASK,
666 DDRC0_REG_BASE + sec_mid_rd_ofst(IPCM_DDR_REGN_IDX));
667 writel(0, DDRC0_REG_BASE + sec_mid_rd_ext_ofst(IPCM_DDR_REGN_IDX));
668
669 /* Set the start address and enable bit */
670 writel(REGN_CTRL_ENABLE | IPCM_REGN_HIGH_ADDR,
671 DDRC0_REG_BASE + sec_rgn_map_ofst(IPCM_DDR_REGN_IDX));
672
673 /* Set the size of ipcm ddr region */
674 writel(IPCM_REGN_SIZE, DDRC0_REG_BASE + sec_rgn_map_ext_ofst(
675 IPCM_DDR_REGN_IDX));
676 }
677
dsp_tzasc_init(void)678 static void dsp_tzasc_init(void)
679 {
680 /* Set the share access authority */
681 writel(SEC_INV_EN | SHARE_REGN_EN,
682 DDRC0_REG_BASE + sec_rgn_attrib_ofst(DSP_DDR_REGN_IDX));
683
684 /* Set the master id mask of write command */
685 writel(DSP_REGN_WR_MID_MASK,
686 DDRC0_REG_BASE + sec_mid_wr_ofst(DSP_DDR_REGN_IDX));
687 writel(0, DDRC0_REG_BASE + sec_mid_wr_ext_ofst(DSP_DDR_REGN_IDX));
688
689 /* Set the master id mask of read command */
690 writel(DSP_REGN_RD_MID_MASK,
691 DDRC0_REG_BASE + sec_mid_rd_ofst(DSP_DDR_REGN_IDX));
692 writel(0, DDRC0_REG_BASE + sec_mid_rd_ext_ofst(DSP_DDR_REGN_IDX));
693
694 /* Set the start address and enable bit */
695 writel(REGN_CTRL_ENABLE | DSP_REGN_HIGH_ADDR,
696 DDRC0_REG_BASE + sec_rgn_map_ofst(DSP_DDR_REGN_IDX));
697
698 /* Set the size of dsp ddr region */
699 writel(DSP_REGN_SIZE, DDRC0_REG_BASE + sec_rgn_map_ext_ofst(DSP_DDR_REGN_IDX));
700 }
701
liteos_tzasc_init(void)702 static void liteos_tzasc_init(void)
703 {
704 /* Set the secure access authority */
705 writel(SEC_INV_EN | SECUR_REGN_EN,
706 DDRC0_REG_BASE + sec_rgn_attrib_ofst(LITEOS_DDR_REGN_IDX));
707
708 /* Set the master id mask of write command */
709 writel(LITEOS_REGN_WR_MID_MASK,
710 DDRC0_REG_BASE + sec_mid_wr_ofst(LITEOS_DDR_REGN_IDX));
711 writel(0, DDRC0_REG_BASE + sec_mid_wr_ext_ofst(LITEOS_DDR_REGN_IDX));
712
713 /* Set the master id mask of read command */
714 writel(LITEOS_REGN_RD_MID_MASK,
715 DDRC0_REG_BASE + sec_mid_rd_ofst(LITEOS_DDR_REGN_IDX));
716 writel(0, DDRC0_REG_BASE + sec_mid_rd_ext_ofst(LITEOS_DDR_REGN_IDX));
717
718 /* Set the start address and enable bit */
719 writel(REGN_CTRL_ENABLE | LITEOS_REGN_HIGH_ADDR,
720 DDRC0_REG_BASE + sec_rgn_map_ofst(LITEOS_DDR_REGN_IDX));
721
722 /* Set the size of dsp ddr region */
723 writel(LITEOS_REGN_SIZE,
724 DDRC0_REG_BASE + sec_rgn_map_ext_ofst(LITEOS_DDR_REGN_IDX));
725 }
726
linux_tzasc_init(void)727 static void linux_tzasc_init(void)
728 {
729 /* Set the non-secure access authority */
730 writel(SEC_INV_EN | NON_SEC_REGN_EN,
731 DDRC0_REG_BASE + sec_rgn_attrib_ofst(LINUX_DDR_REGN_IDX));
732
733 /* Set the master id mask of write command */
734 writel(LINUX_REGN_WR_MID_MASK,
735 DDRC0_REG_BASE + sec_mid_wr_ofst(LINUX_DDR_REGN_IDX));
736 writel(LINUX_REGN_WR_MID_HIGH_MASK,
737 DDRC0_REG_BASE + sec_mid_wr_ext_ofst(LINUX_DDR_REGN_IDX));
738
739 /* Set the master id mask of read command */
740 writel(LINUX_REGN_RD_MID_MASK,
741 DDRC0_REG_BASE + sec_mid_rd_ofst(LINUX_DDR_REGN_IDX));
742 writel(LINUX_REGN_RD_MID_HIGH_MASK,
743 DDRC0_REG_BASE + sec_mid_rd_ext_ofst(LINUX_DDR_REGN_IDX));
744
745 /* Set the start address and enable bit */
746 writel(REGN_CTRL_ENABLE | LINUX_REGN_HIGH_ADDR,
747 DDRC0_REG_BASE + sec_rgn_map_ofst(LINUX_DDR_REGN_IDX));
748
749 /* Set the size of dsp ddr region */
750 writel(LINUX_REGN_SIZE, DDRC0_REG_BASE + sec_rgn_map_ext_ofst(
751 LINUX_DDR_REGN_IDX));
752 }
753
tzasc_init(void)754 static int tzasc_init(void)
755 {
756 /*
757 * Set IPCM ddr region attribution(0x20000000 ~ 0x20200000)*]
758 * */
759 ipcm_tzasc_init();
760
761 /*
762 * Set DSP ddr region attribution(0x20200000 ~ 0x22000000)*]
763 * */
764 dsp_tzasc_init();
765
766 /*
767 * Set Liteos ddr region attribution(0x22000000 ~ 0x10000000)*]
768 * */
769 liteos_tzasc_init();
770
771 /*
772 * Set Linux ddr region attribution(0x32000000 ~ 0x10000000)*]
773 * */
774 linux_tzasc_init();
775
776 /* Disable interrupt */
777 writel(0, DDRC0_REG_BASE + SEC_INT_EN_OFST);
778
779 /* Enable security */
780 writel(SECURITY_ENABLE, DDRC0_REG_BASE + SEC_BYPASS_OFST);
781
782 return 0;
783 }
784 #endif
785
786 #ifdef CONFIG_TARGET_HI3519AV100
787 #define PAGE_SIZE 4096
788 #define page_size_align(x) (((x)+(PAGE_SIZE)-1) / (PAGE_SIZE)*(PAGE_SIZE))
789
__run_a53cpu1(unsigned int addr)790 static int __run_a53cpu1(unsigned int addr)
791 {
792 unsigned int start_phys = 0;
793 unsigned int crg_phys = 0x04510000; /* 0x04510000:crg base */
794 unsigned int regval;
795
796 printf("## Starting A53 at 0x%08X ...\n", addr);
797
798 /* 0xe51ff004 = "ldr pc, [pc, #-4]" */
799 writel(0xe51ff004, start_phys);
800 /* 0x4:next addr value will be the "go_a53" addr */
801 writel(addr, (start_phys + 0x4));
802
803 asm("dsb");
804 asm("isb");
805
806 /* clear the slave cpu reset */
807 regval = readl(crg_phys + 0xcc);
808 regval &= ~(0x1 << 5); /* 0x1,5:corel soft reset request */
809 regval &= ~(0x1 << 25); /* 0x1,25:cluster1 soft reset request */
810 writel(regval, (crg_phys + 0xcc));
811
812 return 0;
813 }
814
start_a53cpu1(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])815 static int start_a53cpu1(cmd_tbl_t *cmdtp, int flag,
816 int argc, char *const argv[])
817 {
818 int ret = 0;
819 unsigned int addr;
820 unsigned int srcaddr;
821 unsigned int offset;
822 unsigned int maxsize = 0;
823 int size_compressed;
824 int size_uncompressed = 0;
825
826 if (argc == NUM_2) {
827 addr = simple_strtoul(argv[NUM_1], NULL, 16); /* 16:base */
828 flush_dcache_all();
829 return __run_a53cpu1(addr);
830 }
831 if (argc != NUM_5)
832 return CMD_RET_USAGE;
833
834 #ifdef CONFIG_SECURE_SCHEME_ENABLE
835 tzasc_init();
836 #endif
837 addr = simple_strtoul(argv[NUM_1], NULL, 16); /* 16:base */
838 srcaddr = simple_strtoul(argv[NUM_2], NULL, 16); /* 16:base */
839 offset = simple_strtoul(argv[NUM_3], NULL, 16); /* 16:base */
840 maxsize = simple_strtoul(argv[NUM_4], NULL, 16); /* 16:base */
841
842 /* 0x80:Read A53bin size */
843 ret = boot_intf_p->read(offset, 0x80, (void *)srcaddr);
844 flush_dcache_all();
845
846 /* read A53bin to DDR */
847 size_compressed = *(int *)(srcaddr + COMPRESSED_SIZE_OFFSET);
848 if (page_size_align(size_compressed) > maxsize) {
849 printf("->a53 Image size infor error !\n");
850 return 0;
851 }
852
853 boot_intf_p->read(offset, page_size_align(size_compressed), (void *)srcaddr);
854 flush_dcache_all();
855
856 size_compressed = *(int *)(srcaddr + COMPRESSED_SIZE_OFFSET);
857 size_uncompressed = *(int *)(srcaddr + UNCOMPRESSED_SIZE_OFFSET);
858
859 hw_dec_init();
860 ret = hw_dec_decompress(NULL, (unsigned char *)(uintptr_t)addr, &size_uncompressed,
861 NULL, ((unsigned char *)(uintptr_t)srcaddr + HIGZIP_HEAD_SIZE), size_compressed, NULL);
862 if (ret)
863 printf("->a53 decompress Fail!\n");
864
865 hw_dec_uinit();
866
867 return __run_a53cpu1(addr);
868 }
869
870 U_BOOT_CMD(
871 go_a53cpu1, CONFIG_SYS_MAXARGS, 3, start_a53cpu1,
872 "start a53-cpu1 at address 'addr'",
873 "addr [arg ...]\n - start a53 application at address 'addr'\n"
874 " passing 'arg' as arguments"
875 );
876 #else
start_a53cpu1(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])877 static int start_a53cpu1(cmd_tbl_t *cmdtp, int flag,
878 int argc, char *const argv[])
879 {
880 unsigned int addr;
881
882 if (argc < NUM_2)
883 return CMD_RET_USAGE;
884
885 #ifdef CONFIG_SECURE_SCHEME_ENABLE
886 tzasc_init();
887 #endif
888 addr = simple_strtoul(argv[NUM_1], NULL, 16); /* 16:base */
889 printf("## Starting A53 at 0x%08X ...\n", addr);
890 /* start up a53 */
891 {
892 unsigned int start_phys = 0;
893 unsigned int crg_phys = 0x04510000; /* 0x04510000:crg base */
894 unsigned int regval;
895
896 /* 0xe51ff004 = "ldr pc, [pc, #-4]" */
897 writel(0xe51ff004, start_phys);
898 /* 0x4:next addr value will be the "go_a53" addr */
899 writel(addr, (start_phys + 0x4));
900
901 asm("dsb");
902 asm("isb");
903
904 /* clear the slave cpu reset */
905 regval = readl(crg_phys + 0xcc);
906 regval &= ~(0x1 << 5); /* 0x1,5:corel soft reset request */
907 regval &= ~(0x1 << 25); /* 0x1,25:cluster1 soft reset request */
908 writel(regval, (crg_phys + 0xcc));
909 }
910 return 0;
911 }
912
913 U_BOOT_CMD(
914 go_a53cpu1, CONFIG_SYS_MAXARGS, 1, start_a53cpu1,
915 "start a53-cpu1 at address 'addr'",
916 "addr [arg ...]\n - start a53 application at address 'addr'\n"
917 " passing 'arg' as arguments"
918 );
919
920 #endif
921