1 /*
2 * hi3535av100.c
3 *
4 * The board init for hisilicon
5 *
6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22 #include <config.h>
23 #include <common.h>
24 #include <asm/io.h>
25 #include <asm/arch/platform.h>
26 #include <spi_flash.h>
27 #include <linux/mtd/mtd.h>
28 #include <nand.h>
29 #include <netdev.h>
30 #include <mmc.h>
31 #include <sdhci.h>
32 #include <asm/armv8/mmu.h>
33 #include <command.h>
34 #include <hicpu_common.h>
35 #include <asm/mach-types.h>
36
37 static struct mm_region hi3535av100_mem_map[] = {
38 {
39 .virt = 0x0UL,
40 .phys = 0x0UL,
41 .size = 0x05000000UL,
42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
43 PTE_BLOCK_NON_SHARE
44 },
45 {
46 .virt = 0x05000000UL,
47 .phys = 0x05000000UL,
48 .size = 0x40000000UL - 0x05000000UL,
49 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
50 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
51 },
52 {
53 .virt = 0x40000000UL,
54 .phys = 0x40000000UL,
55 .size = 0x200000000UL, /* PHYS_SDRAM_1_SIZE */
56 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
57 PTE_BLOCK_INNER_SHARE
58 },
59 {
60 /* List terminator */
61 0,
62 }
63 };
64
65 struct mm_region *mem_map = hi3535av100_mem_map;
66 static int boot_media = BOOT_MEDIA_UNKNOWN;
67
68 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)69 void show_boot_progress(int progress)
70 {
71 printf("Boot reached stage %d\n", progress);
72 }
73 #endif
74
75 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
76
delay(unsigned long loops)77 static inline void delay(unsigned long loops)
78 {
79 __asm__ volatile ("1:\n"
80 "subs %0, %1, #1\n"
81 "bne 1b" : "=r" (loops) : "0" (loops));
82 }
83
84 /* get uboot start media. */
get_boot_media(void)85 int get_boot_media(void)
86 {
87 return boot_media;
88 }
89
get_text_base(void)90 int get_text_base(void)
91 {
92 return CONFIG_SYS_TEXT_BASE;
93 }
94
boot_flag_init(void)95 static void boot_flag_init(void)
96 {
97 unsigned int regval, boot_mode;
98
99 /* get boot mode */
100 regval = __raw_readl(SYS_CTRL_REG_BASE + REG_SYSSTAT);
101 boot_mode = get_sys_boot_mode(regval);
102
103 switch (boot_mode) {
104 /* [3:2] 00b - boot from Spi Nor device */
105 case BOOT_FROM_SPI:
106 boot_media = BOOT_MEDIA_SPIFLASH;
107 break;
108 /* [3:2] 01b - boot from Spi Nand device */
109 case BOOT_FROM_SPI_NAND:
110 boot_media = BOOT_MEDIA_NAND;
111 break;
112 /* [3:2] 11b - boot from emmc */
113 case BOOT_FROM_EMMC:
114 boot_media = BOOT_MEDIA_EMMC;
115 break;
116 default:
117 boot_media = BOOT_MEDIA_UNKNOWN;
118 break;
119 }
120 }
121
board_early_init_f(void)122 int board_early_init_f(void)
123 {
124 return 0;
125 }
126
127 #define PCIE0_CLK_SRST_CTRL 0x3A40
128 #define PCIE_TST_SRST_REQ_SEL 25
__arch_pcie0_tst_srst_req_sel(void * crg_base)129 static void __arch_pcie0_tst_srst_req_sel(void *crg_base)
130 {
131 unsigned int reg_val;
132
133 reg_val = readl(crg_base + PCIE0_CLK_SRST_CTRL);
134 reg_val |= (0x1 << PCIE_TST_SRST_REQ_SEL);
135 writel(reg_val, crg_base + PCIE0_CLK_SRST_CTRL);
136 }
137
138
139 #define PHY1_PORTA_CLK_SRST_CTRL 0x3B70
140 #define PHY1_PORTB_CLK_SRST_CTRL 0x3B90
141 #define PHY_TST_SRST_REQ 1
__arch_phy1_porta_unreset(void * crg_base)142 static void __arch_phy1_porta_unreset(void *crg_base)
143 {
144 unsigned int reg_val;
145
146 reg_val = readl(crg_base + PHY1_PORTA_CLK_SRST_CTRL);
147 reg_val &= ~(0x1 << PHY_TST_SRST_REQ);
148 writel(reg_val, crg_base + PHY1_PORTA_CLK_SRST_CTRL);
149 }
150
__arch_phy1_portb_unreset(void * crg_base)151 static void __arch_phy1_portb_unreset(void *crg_base)
152 {
153 unsigned int reg_val;
154
155 reg_val = readl(crg_base + PHY1_PORTB_CLK_SRST_CTRL);
156 reg_val &= ~(0x1 << PHY_TST_SRST_REQ);
157 writel(reg_val, crg_base + PHY1_PORTB_CLK_SRST_CTRL);
158 }
159
160 #define PHY1_PARA_SET_REG 0x1cc
__arch_phy1_porta_para_config(void * misc_base)161 static void __arch_phy1_porta_para_config(void *misc_base)
162 {
163 writel(0x11100, misc_base + PHY1_PARA_SET_REG);
164 udelay(1);
165 writel(0x11101, misc_base + PHY1_PARA_SET_REG);
166 udelay(1);
167 writel(0x11100, misc_base + PHY1_PARA_SET_REG);
168 writel(0x0, misc_base + PHY1_PARA_SET_REG);
169 }
170
__arch_phy1_portb_para_config(void * misc_base)171 static void __arch_phy1_portb_para_config(void *misc_base)
172 {
173 writel(0x19100, misc_base + PHY1_PARA_SET_REG);
174 udelay(1);
175 writel(0x19101, misc_base + PHY1_PARA_SET_REG);
176 udelay(1);
177 writel(0x19100, misc_base + PHY1_PARA_SET_REG);
178 writel(0x0, misc_base + PHY1_PARA_SET_REG);
179 }
180
181
182 #define PCIE_MODE_SHIFT 16
183 #define PCIE_MODE_MASK 0x7
__arch_get_ups_mode(void)184 static int __arch_get_ups_mode(void)
185 {
186 unsigned int val;
187 unsigned int mode;
188
189 val = readl((uintptr_t)(SYS_CTRL_REG_BASE + REG_SYSSTAT));
190 mode = (val >> PCIE_MODE_SHIFT) & PCIE_MODE_MASK;
191
192 return mode;
193 }
194
__arch_pcie_set_phy_para(void)195 static void __arch_pcie_set_phy_para(void)
196 {
197 unsigned int ups_mode;
198 void *misc_base_addr = (void *)(uintptr_t)MISC_REG_BASE;
199 void *crg_base = (void *)(uintptr_t)CRG_REG_BASE;
200
201 ups_mode = __arch_get_ups_mode();
202 switch (ups_mode) {
203 case NUM_0:
204 __arch_phy1_porta_unreset(crg_base);
205 __arch_phy1_portb_unreset(crg_base);
206
207 __arch_pcie0_tst_srst_req_sel(crg_base);
208
209 __arch_phy1_porta_para_config(misc_base_addr);
210 __arch_phy1_portb_para_config(misc_base_addr);
211 break;
212 case NUM_1:
213 __arch_phy1_porta_unreset(crg_base);
214
215 __arch_pcie0_tst_srst_req_sel(crg_base);
216
217 __arch_phy1_porta_para_config(misc_base_addr);
218 break;
219
220 default:
221 break;
222 }
223 }
224
is_auto_update(void)225 int is_auto_update(void)
226 {
227 #if (defined CONFIG_AUTO_USB_UPDATE)
228 /* to add some judgement if neccessary */
229 return 1; /* update enable */
230
231 #else
232 return 0;
233 #endif
234 }
235
misc_init_r(void)236 int misc_init_r(void)
237 {
238 #ifdef CONFIG_RANDOM_ETHADDR
239 random_init_r();
240 #endif
241 env_set("verify", "n");
242
243 #if (CONFIG_AUTO_UPDATE == 1)
244 /* auto update flag */
245 if (is_auto_update())
246 do_auto_update();
247 #endif /* CONFIG_AUTO_UPDATE */
248
249 __arch_pcie_set_phy_para();
250
251 return 0;
252 }
253
board_init(void)254 int board_init(void)
255 {
256 DECLARE_GLOBAL_DATA_PTR;
257
258 gd->bd->bi_arch_number = MACH_TYPE_HI3535AV100;
259 gd->bd->bi_boot_params = CFG_BOOT_PARAMS;
260
261 boot_flag_init();
262
263 return 0;
264 }
265
dram_init(void)266 int dram_init(void)
267 {
268 DECLARE_GLOBAL_DATA_PTR;
269
270 gd->ram_size = PHYS_SDRAM_1_SIZE;
271 return 0;
272 }
273
reset_cpu(ulong addr)274 void reset_cpu(ulong addr)
275 {
276 /* 0x12345678:writing any value will cause a reset. */
277 writel(0x12345678, REG_BASE_SCTL + REG_SC_SYSRES);
278 while(1) ;
279 }
280
timer_init(void)281 int timer_init(void)
282 {
283 /*
284 * Under uboot, 0xffffffff is set to load register,
285 * timer_clk equals BUSCLK/2/256.
286 * e.g. BUSCLK equals 50M, it will roll back after 0xffffffff/timer_clk
287 * 43980s equals 12hours
288 */
289 __raw_writel(0, CFG_TIMERBASE + REG_TIMER_CONTROL);
290 __raw_writel(~0, CFG_TIMERBASE + REG_TIMER_RELOAD);
291
292 /* 32 bit, periodic */
293 __raw_writel(CFG_TIMER_CTRL, CFG_TIMERBASE + REG_TIMER_CONTROL);
294
295 return 0;
296 }
297
board_eth_init(bd_t * bis)298 int board_eth_init(bd_t *bis)
299 {
300 int rc = 0;
301
302 #ifdef CONFIG_HIGMACV300_ETH
303 rc = higmac_initialize(bis);
304 #endif
305 return rc;
306 }
307
308 #ifdef CONFIG_GENERIC_MMC
309
board_mmc_init(bd_t * bis)310 int board_mmc_init(bd_t *bis)
311 {
312 int ret = 0;
313 int dev_num = 0;
314
315 #ifdef CONFIG_EMMC
316 ret = hisi_sdhci_add_port(0, EMMC_BASE_REG, MMC_TYPE_MMC);
317 if (!ret) {
318 ret = hisi_mmc_init(dev_num);
319 if (ret)
320 printf("No EMMC device found !\n");
321 }
322 dev_num++;
323 #endif
324
325 #ifdef CONFIG_AUTO_SD_UPDATE
326 if (is_auto_update()) {
327 ret = hisi_sdhci_add_port(1, SDIO0_BASE_REG, MMC_TYPE_SD);
328 if (ret)
329 return ret;
330
331 ret = hisi_mmc_init(dev_num);
332 if (ret)
333 printf("No SD device found !\n");
334 }
335 #endif
336 return ret;
337 }
338 #endif
339
340
341