1 /*
2 * hi3556av100.c
3 *
4 * The board init for hisilicon
5 *
6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22 #include "../../../lib/hw_dec/hw_decompress_v2.h"
23 #include <config.h>
24 #include <common.h>
25 #include <command.h>
26 #include <asm/io.h>
27 #include <asm/arch/platform.h>
28 #include <spi_flash.h>
29 #include <linux/mtd/mtd.h>
30 #include <nand.h>
31 #include <netdev.h>
32 #include <mmc.h>
33 #include <sdhci.h>
34 #include <blk.h>
35 #include <hicpu_common.h>
36 #include <asm/mach-types.h>
37 #include <cpu_func.h>
38
39 #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)40 void enable_caches(void)
41 {
42 /* Enable D-cache. I-cache is already enabled in start.S */
43 dcache_enable();
44 }
45 #endif
46
47 static int boot_media = BOOT_MEDIA_UNKNOWN;
48
49 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)50 void show_boot_progress(int progress)
51 {
52 printf("Boot reached stage %d\n", progress);
53 }
54 #endif
55
56 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
57
delay(unsigned long loops)58 static inline void delay(unsigned long loops)
59 {
60 __asm__ volatile("1:\n"
61 "subs %0, %1, #1\n"
62 "bne 1b" : "=r"(loops) : "0"(loops));
63 }
64
65 /* get uboot start media. */
get_boot_media(void)66 int get_boot_media(void)
67 {
68 return boot_media;
69 }
70
get_text_base(void)71 int get_text_base(void)
72 {
73 return CONFIG_SYS_TEXT_BASE;
74 }
75
boot_flag_init(void)76 static void boot_flag_init(void)
77 {
78 unsigned int regval, boot_mode;
79
80 /* get boot mode */
81 regval = __raw_readl(SYS_CTRL_REG_BASE + REG_SYSSTAT);
82 boot_mode = get_sys_boot_mode(regval);
83
84 switch (boot_mode) {
85 /* [5:4] 00b - boot from spi device */
86 case BOOT_FROM_SPI:
87 if (get_spi_device_type(regval))
88 boot_media = BOOT_MEDIA_NAND;
89 else
90 boot_media = BOOT_MEDIA_SPIFLASH;
91 break;
92 /* [5:4] 01b - boot from spi nand device */
93 case BOOT_FROM_SPI_NAND:
94 boot_media = BOOT_MEDIA_NAND;
95 break;
96 /* [5:4] 01b - boot from Nand device */
97 case BOOT_FROM_NAND:
98 boot_media = BOOT_MEDIA_NAND;
99 break;
100 /* [5:4] 10b - boot from emmc */
101 case BOOT_FROM_EMMC:
102 boot_media = BOOT_MEDIA_EMMC;
103 break;
104 default:
105 boot_media = BOOT_MEDIA_UNKNOWN;
106 break;
107 }
108 }
109
board_early_init_f(void)110 int board_early_init_f(void)
111 {
112 return 0;
113 }
114
115 #define UBOOT_DATA_ADDR 0x21000000ul
116 #define UBOOT_DATA_SIZE 0x80000UL
data_to_spiflash(void)117 int data_to_spiflash(void)
118 {
119 static struct spi_flash *flash = NULL;
120 void *buf = NULL;
121 unsigned int val;
122
123 /* 0:bus 0:cs 1000000:max_hz 0x3:spi_mode */
124 flash = spi_flash_probe(0, 0, 1000000, 0x3);
125 if (!flash) {
126 printf("Failed to initialize SPI flash\n");
127 return -1; /* -1:failed */
128 }
129
130 /* erase the address range. */
131 printf("Spi flash erase...\n");
132 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE);
133 if (val) {
134 printf("SPI flash sector erase failed\n");
135 return 1; /* 1:failed */
136 }
137
138 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
139 UBOOT_DATA_SIZE, MAP_WRBACK);
140 if (!buf) {
141 puts("Failed to map physical memory\n");
142 return 1; /* 1:failed */
143 }
144
145 /* copy the data from RAM to FLASH */
146 printf("Spi flash write...\n");
147 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf);
148 if (val) {
149 printf("SPI flash write failed, return %u\n",
150 val);
151 unmap_physmem(buf, UBOOT_DATA_SIZE);
152 return 1; /* 1:failed */
153 }
154
155 unmap_physmem(buf, UBOOT_DATA_SIZE);
156 return 0; /* 0:success */
157 }
158
data_to_nandflash(void)159 int data_to_nandflash(void)
160 {
161 struct mtd_info *nand_flash = NULL;
162 void *buf = NULL;
163 size_t length = UBOOT_DATA_SIZE;
164 unsigned int val;
165
166 nand_flash = nand_info[0];
167
168 printf("Nand flash erase...\n");
169 val = nand_erase(nand_flash, 0, UBOOT_DATA_SIZE);
170 if (val) {
171 printf("Nand flash erase failed\n");
172 return 1;
173 }
174
175 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
176 UBOOT_DATA_SIZE, MAP_WRBACK);
177 if (!buf) {
178 puts("Failed to map physical memory\n");
179 return 1;
180 }
181
182 printf("Nand flash write...\n");
183 val = nand_write(nand_flash, 0, &length, buf);
184 if (val) {
185 printf("Nand flash write failed, return %u\n",
186 val);
187 unmap_physmem(buf, UBOOT_DATA_SIZE);
188 return 1;
189 }
190
191 unmap_physmem(buf, UBOOT_DATA_SIZE);
192 return 0;
193 }
194
data_to_emmc(void)195 int data_to_emmc(void)
196 {
197 struct mmc *mmc = find_mmc_device(0);
198 void *buf = NULL;
199
200 if (!mmc)
201 return 1;
202
203 (void)mmc_init(mmc);
204
205 buf = map_physmem((unsigned long)UBOOT_DATA_ADDR,
206 UBOOT_DATA_SIZE, MAP_WRBACK);
207 if (!buf) {
208 puts("Failed to map physical memory\n");
209 return 1;
210 }
211
212 printf("MMC write...\n");
213 blk_dwrite(mmc_get_blk_desc(mmc), 0, (UBOOT_DATA_SIZE >> NUM_9), buf);
214 unmap_physmem(buf, UBOOT_DATA_SIZE);
215 return 0;
216 }
save_bootdata_to_flash(void)217 int save_bootdata_to_flash(void)
218 {
219 unsigned int sd_update_flag = 0;
220 int ret = 0;
221 sd_update_flag = readl(REG_BASE_SCTL + REG_SC_GEN4);
222 if (sd_update_flag == START_MAGIC) {
223 #if defined(CONFIG_HIFMC)
224 if (boot_media == BOOT_MEDIA_SPIFLASH) {
225 ret = data_to_spiflash();
226 if (ret != 0)
227 return ret;
228 }
229 if (boot_media == BOOT_MEDIA_NAND) {
230 ret = data_to_nandflash();
231 if (ret != 0)
232 return ret;
233 }
234 #endif
235 #if defined(CONFIG_MMC)
236 if (boot_media == BOOT_MEDIA_EMMC) {
237 ret = data_to_emmc();
238 if (ret != 0)
239 return ret;
240 }
241 #endif
242
243 printf("update success!\n");
244 }
245
246 return 0;
247 }
248
249 int auto_update_flag = 0;
250 int bare_chip_program = 0;
251
252 #define REG_BASE_GPIO4 0x045f4000
253 #define GPIO4_3_DATA_OFST 0x20
254 #define GPIO_DIR_OFST 0x400
255
256 #ifdef CONFIG_TARGET_HI3556AV100
257 /* * upgrade status register address */
258 #define UPGRADE_STATUS_REG_ADDR (0x04590048)
259
260 typedef enum tagUPGRADE_STATUS_E {
261 UPGRADE_STATUS_IDLE = 0,
262 UPGRADE_STATUS_PROCESSING,
263 UPGRADE_STATUS_FINISH,
264 UPGRADE_STATUS_BUTT
265 } upgrade_status_e;
266 #endif
267
is_bare_program(void)268 int is_bare_program(void)
269 {
270 return 1;
271 }
272
273 #if (CONFIG_AUTO_UPDATE == 1)
is_auto_update(void)274 int is_auto_update(void)
275 {
276 #if (defined CONFIG_AUTO_SD_UPDATE) || (defined CONFIG_AUTO_USB_UPDATE)
277 /* to add some judgement if neccessary */
278 unsigned int val[NUM_3];
279
280 #ifdef CONFIG_TARGET_HI3556AV100
281 unsigned int *puregval = (unsigned int *)UPGRADE_STATUS_REG_ADDR;
282 if (((*puregval) & (UPGRADE_STATUS_PROCESSING)) != 0)
283 return 1; /* update enable */
284 #endif
285
286 writel(0, REG_BASE_GPIO4 + GPIO_DIR_OFST);
287
288 val[NUM_0] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST);
289 if (val[NUM_0])
290 return 0;
291
292 udelay(10000); /* delay 10000 us */
293 val[NUM_1] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST);
294 udelay(10000); /* delay 10000 us */
295 val[NUM_2] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST);
296 udelay(10000); /* delay 10000 us */
297
298 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0)
299 return 1; /* update enable */
300 else
301 return 0;
302
303 #else
304 return 0;
305 #endif
306 }
307 #endif /* CONFIG_AUTO_UPDATE */
308
309 #ifdef CONFIG_TARGET_HI3556AV100
310 struct boot_medium_interface {
311 char name[0x10]; /* 0x10:name len */
312 int (*init)(void);
313 int (*read)(unsigned long offset, unsigned long len, void *buf);
314 };
315
316 /* spi nand configure */
317 #if defined(CONFIG_HIFMC_SPI_NAND)|| defined(CONFIG_HIFMC_NAND)
318 #define NAND_MAX_SIZE 0xFFFFFFFF
nand_flash_read(unsigned long offset,unsigned long len,void * buf)319 static int nand_flash_read(unsigned long offset, unsigned long len, void *buf)
320 {
321 struct mtd_info *mtd = nand_info[NUM_0];
322 size_t rwsize = len;
323 return nand_read_skip_bad(mtd, offset, &rwsize, NULL, NAND_MAX_SIZE,
324 (unsigned char *)buf);
325 }
326 #endif
327
328 #ifdef CONFIG_HIFMC_SPI_NOR /* spi nor configure */
329 struct spi_flash *spiflash;
330
331 #include "spi_flash.h"
spinor_flash_read(unsigned long offset,unsigned long len,void * buf)332 static int spinor_flash_read(unsigned long offset, unsigned long len, void *buf)
333 {
334 /* 0,0,0,0:bus,cs,max_hz,spi_mode */
335 spiflash = spi_flash_probe(0, 0, 0, 0);
336 if (!spiflash)
337 printf("spiflash is null!\n");
338 spi_flash_read(spiflash, offset, len, buf);
339 return 0;
340 }
341 #endif
342
343 #ifdef CONFIG_MMC
mmc_read_data(unsigned long offset,unsigned long len,void * buf)344 static int mmc_read_data(unsigned long offset, unsigned long len, void *buf)
345 {
346 unsigned long ret;
347 struct mmc *mmc = find_mmc_device(0);
348 if (!mmc)
349 return 1;
350 (void)mmc_init(mmc);
351 ret = blk_dread(mmc_get_blk_desc(mmc), offset, len, buf);
352 return ret;
353 }
354 #endif
355
356 static struct boot_medium_interface boot_intf[NUM_1] = {0};
357 static struct boot_medium_interface *boot_intf_p;
358
boot_medium_init(void)359 void boot_medium_init(void)
360 {
361 /* register boot media interface */
362 if (get_boot_media() == BOOT_MEDIA_SPIFLASH) {
363 printf("boot_media spinor!\n");
364 boot_intf[NUM_0].init = NULL;
365 #ifdef CONFIG_HIFMC_SPI_NOR
366 boot_intf[NUM_0].read = spinor_flash_read;
367 #endif
368 strncpy(boot_intf[NUM_0].name, "spinor", sizeof(boot_intf[NUM_0].name));
369 } else if (get_boot_media() == BOOT_MEDIA_NAND) {
370 printf("boot_media nand!\n");
371 boot_intf[NUM_0].init = NULL;
372 #if defined(CONFIG_HIFMC_SPI_NAND)|| defined(CONFIG_HIFMC_NAND)
373 boot_intf[NUM_0].read = nand_flash_read;
374 #endif
375 strncpy(boot_intf[NUM_0].name, "nand", sizeof(boot_intf[NUM_0].name));
376 } else if (get_boot_media() == BOOT_MEDIA_EMMC) {
377 printf("boot_media emmc!\n");
378 boot_intf[NUM_0].init = NULL;
379 #ifdef CONFIG_MMC
380 boot_intf[NUM_0].read = mmc_read_data;
381 #endif
382 strncpy(boot_intf[NUM_0].name, "emmc", sizeof(boot_intf[NUM_0].name));
383 } else {
384 printf("boot_media unkonw error !\n");
385 }
386
387 boot_intf_p = &boot_intf[NUM_0];
388
389 /* boot media init */
390 if (boot_intf_p->init)
391 boot_intf_p->init();
392 }
393 #endif
394
select_upgrade_dev(void)395 void select_upgrade_dev(void)
396 {
397 #ifdef CONFIG_EMMC
398 unsigned int uval = readl(UPGRADE_STATUS_REG_ADDR);
399 unsigned int stor_dev = 0;
400 unsigned int stor_paration = 0;
401 stor_dev = (uval >> 16) & 0x03; /* 16,0x03: store dev */
402 stor_paration = (uval >> 18) & 0x1f; /* 18,0x1f: store paration */
403 if (((uval) & (UPGRADE_STATUS_PROCESSING)) != NUM_0) {
404 /* the upgrade startup by linux application */
405 if (stor_dev == NUM_0) {
406 /* emmc */
407 target_dev = NUM_0;
408 target_paratition = stor_paration;
409 } else {
410 /* sd */
411 target_dev = NUM_1;
412 }
413 } else {
414 /* the upgrade startup by upgrade key on the board, os defaule upgrade style */
415 target_dev = NUM_1;
416 }
417
418 printf("update dev is %d: paratition is %d\n",
419 target_dev, target_paratition);
420 #endif
421 return;
422 }
423
misc_init_r(void)424 int misc_init_r(void)
425 {
426 #ifdef CONFIG_TARGET_HI3556AV100
427 boot_medium_init();
428 #endif
429
430 #ifdef CONFIG_RANDOM_ETHADDR
431 random_init_r();
432 #endif
433 env_set("verify", "n");
434
435 /* bare chip program flag */
436 if (is_bare_program())
437 bare_chip_program = 1;
438 else
439 bare_chip_program = 0;
440
441 #if (CONFIG_AUTO_UPDATE == 1)
442 /* auto update flag */
443 if (is_auto_update())
444 auto_update_flag = 1;
445 else
446 auto_update_flag = 0;
447
448 #ifdef CFG_MMU_HANDLEOK
449 dcache_stop();
450 #endif
451
452 #ifdef CFG_MMU_HANDLEOK
453 dcache_start();
454 #endif
455
456 #endif
457
458 #if (CONFIG_AUTO_UPDATE == 1)
459 if (auto_update_flag) {
460 #ifdef CONFIG_TARGET_HI3556AV100
461 select_upgrade_dev();
462 int result = do_auto_update();
463 if (result == 0) {
464 unsigned int uregval = readl(UPGRADE_STATUS_REG_ADDR);
465 udelay(10000); /* delay 10000 us */
466 if ((uregval & UPGRADE_STATUS_PROCESSING) != NUM_0) {
467 writel(UPGRADE_STATUS_FINISH,
468 UPGRADE_STATUS_REG_ADDR);
469 printf("upgrade status: finish\n");
470 }
471 printf("update success\n");
472 do_reset(NULL, 0, 0, NULL);
473 }
474 #else
475 do_auto_update();
476 #endif
477 }
478
479 #endif
480
481 if (bare_chip_program && !auto_update_flag)
482 save_bootdata_to_flash();
483
484 return 0;
485 }
486
board_init(void)487 int board_init(void)
488 {
489 DECLARE_GLOBAL_DATA_PTR;
490
491 gd->bd->bi_arch_number = MACH_TYPE_HI3556AV100;
492 gd->bd->bi_boot_params = CFG_BOOT_PARAMS;
493
494 boot_flag_init();
495
496 return 0;
497 }
498
dram_init(void)499 int dram_init(void)
500 {
501 DECLARE_GLOBAL_DATA_PTR;
502
503 gd->ram_size = PHYS_SDRAM_1_SIZE;
504 return 0;
505 }
506
reset_cpu(ulong addr)507 void reset_cpu(ulong addr)
508 {
509 /* 0x12345678:writing any value will cause a reset. */
510 writel(0x12345678, REG_BASE_SCTL + REG_SC_SYSRES);
511 while (1);
512 }
513
timer_init(void)514 int timer_init(void)
515 {
516 /*
517 * Under uboot, 0xffffffff is set to load register,]
518 * timer_clk equals BUSCLK/2/256.
519 * e.g. BUSCLK equals 50M, it will roll back after 0xffffffff/timer_clk
520 * 43980s equals 12hours
521 */
522 __raw_writel(0, CFG_TIMERBASE + REG_TIMER_CONTROL);
523 __raw_writel(~0, CFG_TIMERBASE + REG_TIMER_RELOAD);
524
525 /* 32 bit, periodic */
526 __raw_writel(CFG_TIMER_CTRL, CFG_TIMERBASE + REG_TIMER_CONTROL);
527
528 __raw_writel(0, TIMER8_REG_BASE + REG_TIMER_CONTROL);
529 __raw_writel(~0, TIMER8_REG_BASE + REG_TIMER_RELOAD);
530 /* 32 bit, periodic */
531 __raw_writel(CFG_TIMER_CTRL, TIMER8_REG_BASE + REG_TIMER_CONTROL);
532 return 0;
533 }
534
board_eth_init(bd_t * bis)535 int board_eth_init(bd_t *bis)
536 {
537 int rc = 0;
538
539 #ifdef CONFIG_HIGMACV300_ETH
540 rc = higmac_initialize(bis);
541 #endif
542 return rc;
543 }
544 #ifdef CONFIG_GENERIC_MMC
board_mmc_init(bd_t * bis)545 int board_mmc_init(bd_t *bis)
546 {
547 int ret = 0;
548
549 #ifdef CONFIG_HISI_SDHCI
550
551 #if !defined(CONFIG_HIFMC) || defined(CONFIG_AUTO_SD_UPDATE)
552 int dev_num = 0;
553 #endif
554
555 #ifndef CONFIG_HIFMC
556 ret = hisi_sdhci_add_port(0, EMMC_BASE_REG, MMC_TYPE_MMC);
557 if (!ret) {
558 ret = hisi_mmc_init(dev_num);
559 if (ret)
560 printf("No EMMC device found !\n");
561 }
562 dev_num++;
563 #endif
564
565 #ifdef CONFIG_AUTO_SD_UPDATE
566 if (is_auto_update()) {
567 ret = hisi_sdhci_add_port(1, SDIO0_BASE_REG, MMC_TYPE_SD);
568 if (ret)
569 return ret;
570
571 ret = hisi_mmc_init(dev_num);
572 if (ret)
573 printf("No SD device found !\n");
574 }
575 #endif
576 #endif
577
578 return ret;
579 }
580 #endif
581
582
583 #ifdef CONFIG_SECURE_SCHEME_ENABLE
584
585 /* macros to get secure register's offset address */
586 #define sec_rgn_map_ofst(region_idx) (0x1100 + 0x10 * (region_idx))
587 #define sec_rgn_map_ext_ofst(region_idx) (0x1200 + 0x10 * (region_idx))
588
589 #define sec_rgn_attrib_ofst(region_idx) (0x1104 + 0x10 * (region_idx))
590
591 #define sec_mid_wr_ofst(region_idx) (0x1108 + 0x10 * (region_idx))
592 #define sec_mid_wr_ext_ofst(region_idx) (0x1204 + 0x10 * (region_idx))
593
594 #define sec_mid_rd_ofst(region_idx) (0x110c + 0x10 * (region_idx))
595 #define sec_mid_rd_ext_ofst(region_idx) (0x1208 + 0x10 * (region_idx))
596
597 #define SEC_BYPASS_OFST 0x1004
598 #define SEC_INT_EN_OFST 0x1020
599
600 /* macros for register value */
601 #define SECURITY_ENABLE 0xff
602
603 #define SEC_INV_EN (0x1 << 4)
604 #define SHARE_REGN_EN (0xf)
605 #define SECUR_REGN_EN (0xc)
606 #define NON_SEC_REGN_EN (0x3)
607
608 #define A53CPU0_MID 0xf
609 #define A53CPU1_MID 0x11
610 #define DSP_M0_MID 0x13
611 #define AVSP_M2_MID 0x18
612 #define DSP_M1_MID 0x1c
613
614 #define MID_HIGH_START_BIT 0x20
615 #define FMC_MID 0x21
616 #define EMMC_MID 0x28
617
618 #define IPCM_REGN_WR_MID_MASK ((0x1 << A53CPU0_MID) | (0x1 << A53CPU1_MID))
619 #define IPCM_REGN_RD_MID_MASK IPCM_REGN_WR_MID_MASK
620
621 #define DSP_REGN_WR_MID_MASK ((0x1 << A53CPU0_MID) | (0x1 << DSP_M0_MID) | \
622 (0x1 << AVSP_M2_MID) | (0x1 << DSP_M1_MID))
623 #define DSP_REGN_RD_MID_MASK DSP_REGN_WR_MID_MASK
624
625 #define LITEOS_REGN_WR_MID_MASK (0x1 << A53CPU1_MID)
626 #define LITEOS_REGN_RD_MID_MASK LITEOS_REGN_WR_MID_MASK
627
628 #define LINUX_REGN_WR_MID_MASK ((0x1 << A53CPU0_MID))
629 #define LINUX_REGN_RD_MID_MASK LINUX_REGN_WR_MID_MASK
630
631 #define LINUX_REGN_WR_MID_HIGH_MASK ((0x1 << (FMC_MID - MID_HIGH_START_BIT)) | \
632 (0x1 << (EMMC_MID - MID_HIGH_START_BIT)))
633 #define LINUX_REGN_RD_MID_HIGH_MASK LINUX_REGN_WR_MID_HIGH_MASK
634
635 #define REGN_CTRL_ENABLE (0x1 << 31)
636
637 #define IPCM_REGN_HIGH_ADDR 0x2000 /* high 16 bit of address */
638 #define IPCM_REGN_SIZE 0x20 /* 0x20 * 64K Byte */
639
640 #define DSP_REGN_HIGH_ADDR 0x2020 /* high 16 bit of address */
641 #define DSP_REGN_SIZE 0x1e0 /* 0x1e0 * 64K Byte */
642
643 #define LITEOS_REGN_HIGH_ADDR 0x2200 /* high 16 bit of address */
644 #define LITEOS_REGN_SIZE 0x1000 /* 0x1000 * 64K Byte */
645
646 #define LINUX_REGN_HIGH_ADDR 0x3200 /* high 16 bit of address */
647 #define LINUX_REGN_SIZE 0x1000 /* 0x1000 * 64K Byte */
648
649 #define IPCM_DDR_REGN_IDX 1
650 #define DSP_DDR_REGN_IDX 2
651 #define LITEOS_DDR_REGN_IDX 3
652 #define LINUX_DDR_REGN_IDX 4
653
ipcm_tzasc_init(void)654 static void ipcm_tzasc_init(void)
655 {
656 /* Set the share access authority */
657 writel(SEC_INV_EN | SHARE_REGN_EN,
658 DDRC0_REG_BASE + sec_rgn_attrib_ofst(IPCM_DDR_REGN_IDX));
659
660 /* Set the master id mask of write command */
661 writel(IPCM_REGN_WR_MID_MASK,
662 DDRC0_REG_BASE + sec_mid_wr_ofst(IPCM_DDR_REGN_IDX));
663 writel(0, DDRC0_REG_BASE + sec_mid_wr_ext_ofst(IPCM_DDR_REGN_IDX));
664
665 /* Set the master id mask of read command */
666 writel(IPCM_REGN_RD_MID_MASK,
667 DDRC0_REG_BASE + sec_mid_rd_ofst(IPCM_DDR_REGN_IDX));
668 writel(0, DDRC0_REG_BASE + sec_mid_rd_ext_ofst(IPCM_DDR_REGN_IDX));
669
670 /* Set the start address and enable bit */
671 writel(REGN_CTRL_ENABLE | IPCM_REGN_HIGH_ADDR,
672 DDRC0_REG_BASE + sec_rgn_map_ofst(IPCM_DDR_REGN_IDX));
673
674 /* Set the size of ipcm ddr region */
675 writel(IPCM_REGN_SIZE, DDRC0_REG_BASE + sec_rgn_map_ext_ofst(
676 IPCM_DDR_REGN_IDX));
677 }
678
dsp_tzasc_init(void)679 static void dsp_tzasc_init(void)
680 {
681 /* Set the share access authority */
682 writel(SEC_INV_EN | SHARE_REGN_EN,
683 DDRC0_REG_BASE + sec_rgn_attrib_ofst(DSP_DDR_REGN_IDX));
684
685 /* Set the master id mask of write command */
686 writel(DSP_REGN_WR_MID_MASK,
687 DDRC0_REG_BASE + sec_mid_wr_ofst(DSP_DDR_REGN_IDX));
688 writel(0, DDRC0_REG_BASE + sec_mid_wr_ext_ofst(DSP_DDR_REGN_IDX));
689
690 /* Set the master id mask of read command */
691 writel(DSP_REGN_RD_MID_MASK,
692 DDRC0_REG_BASE + sec_mid_rd_ofst(DSP_DDR_REGN_IDX));
693 writel(0, DDRC0_REG_BASE + sec_mid_rd_ext_ofst(DSP_DDR_REGN_IDX));
694
695 /* Set the start address and enable bit */
696 writel(REGN_CTRL_ENABLE | DSP_REGN_HIGH_ADDR,
697 DDRC0_REG_BASE + sec_rgn_map_ofst(DSP_DDR_REGN_IDX));
698
699 /* Set the size of dsp ddr region */
700 writel(DSP_REGN_SIZE, DDRC0_REG_BASE +
701 sec_rgn_map_ext_ofst(DSP_DDR_REGN_IDX));
702 }
703
liteos_tzasc_init(void)704 static void liteos_tzasc_init(void)
705 {
706 /* Set the secure access authority */
707 writel(SEC_INV_EN | SECUR_REGN_EN,
708 DDRC0_REG_BASE + sec_rgn_attrib_ofst(LITEOS_DDR_REGN_IDX));
709
710 /* Set the master id mask of write command */
711 writel(LITEOS_REGN_WR_MID_MASK,
712 DDRC0_REG_BASE + sec_mid_wr_ofst(LITEOS_DDR_REGN_IDX));
713 writel(0, DDRC0_REG_BASE + sec_mid_wr_ext_ofst(LITEOS_DDR_REGN_IDX));
714
715 /* Set the master id mask of read command */
716 writel(LITEOS_REGN_RD_MID_MASK,
717 DDRC0_REG_BASE + sec_mid_rd_ofst(LITEOS_DDR_REGN_IDX));
718 writel(0, DDRC0_REG_BASE + sec_mid_rd_ext_ofst(LITEOS_DDR_REGN_IDX));
719
720 /* Set the start address and enable bit */
721 writel(REGN_CTRL_ENABLE | LITEOS_REGN_HIGH_ADDR,
722 DDRC0_REG_BASE + sec_rgn_map_ofst(LITEOS_DDR_REGN_IDX));
723
724 /* Set the size of dsp ddr region */
725 writel(LITEOS_REGN_SIZE,
726 DDRC0_REG_BASE + sec_rgn_map_ext_ofst(LITEOS_DDR_REGN_IDX));
727 }
728
linux_tzasc_init(void)729 static void linux_tzasc_init(void)
730 {
731 /* Set the non-secure access authority */
732 writel(SEC_INV_EN | NON_SEC_REGN_EN,
733 DDRC0_REG_BASE + sec_rgn_attrib_ofst(LINUX_DDR_REGN_IDX));
734
735 /* Set the master id mask of write command */
736 writel(LINUX_REGN_WR_MID_MASK,
737 DDRC0_REG_BASE + sec_mid_wr_ofst(LINUX_DDR_REGN_IDX));
738 writel(LINUX_REGN_WR_MID_HIGH_MASK,
739 DDRC0_REG_BASE + sec_mid_wr_ext_ofst(LINUX_DDR_REGN_IDX));
740
741 /* Set the master id mask of read command */
742 writel(LINUX_REGN_RD_MID_MASK,
743 DDRC0_REG_BASE + sec_mid_rd_ofst(LINUX_DDR_REGN_IDX));
744 writel(LINUX_REGN_RD_MID_HIGH_MASK,
745 DDRC0_REG_BASE + sec_mid_rd_ext_ofst(LINUX_DDR_REGN_IDX));
746
747 /* Set the start address and enable bit */
748 writel(REGN_CTRL_ENABLE | LINUX_REGN_HIGH_ADDR,
749 DDRC0_REG_BASE + sec_rgn_map_ofst(LINUX_DDR_REGN_IDX));
750
751 /* Set the size of dsp ddr region */
752 writel(LINUX_REGN_SIZE, DDRC0_REG_BASE + sec_rgn_map_ext_ofst(
753 LINUX_DDR_REGN_IDX));
754 }
755
tzasc_init(void)756 static int tzasc_init(void)
757 {
758 /*
759 * Set IPCM ddr region attribution(0x20000000 ~ 0x20200000)*]
760 * */
761 ipcm_tzasc_init();
762
763 /*
764 * Set DSP ddr region attribution(0x20200000 ~ 0x22000000)*]
765 * */
766 dsp_tzasc_init();
767
768 /*
769 * Set Liteos ddr region attribution(0x22000000 ~ 0x10000000)*]
770 * */
771 liteos_tzasc_init();
772
773 /*
774 * Set Linux ddr region attribution(0x32000000 ~ 0x10000000)*]
775 * */
776 linux_tzasc_init();
777
778 /* Disable interrupt */
779 writel(0, DDRC0_REG_BASE + SEC_INT_EN_OFST);
780
781 /* Enable security */
782 writel(SECURITY_ENABLE, DDRC0_REG_BASE + SEC_BYPASS_OFST);
783
784 return 0;
785 }
786 #endif
787
788 #ifdef CONFIG_TARGET_HI3556AV100
789 #define PAGE_SIZE 4096
790 #define page_size_align(x) (((x)+(PAGE_SIZE)-1) / (PAGE_SIZE)*(PAGE_SIZE))
791
__run_a53cpu1(unsigned int addr)792 static int __run_a53cpu1(unsigned int addr)
793 {
794 unsigned int start_phys = 0;
795 unsigned int crg_phys = 0x04510000; /* 0x04510000:crg base */
796 unsigned int regval;
797
798 printf("## Starting A53 at 0x%08X ...\n", addr);
799 /* 0xe51ff004 = "ldr pc, [pc, #-4]" */
800 writel(0xe51ff004, start_phys);
801 /* 0x4:next addr value will be the "go_a53" addr */
802 writel(addr, (start_phys + 0x4));
803
804 asm("dsb");
805 asm("isb");
806
807 /* clear the slave cpu reset */
808 regval = readl(crg_phys + 0xcc);
809 regval &= ~(0x1 << 5); /* 0x1,5:corel soft reset request */
810 regval &= ~(0x1 << 25); /* 0x1,25:cluster1 soft reset request */
811 writel(regval, (crg_phys + 0xcc));
812
813 return 0;
814 }
815
start_a53cpu1(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])816 static int start_a53cpu1(cmd_tbl_t *cmdtp, int flag, int argc,
817 char *const argv[])
818 {
819 int ret = 0;
820 unsigned int addr;
821 unsigned int srcaddr;
822 unsigned int offset;
823 unsigned int maxsize = 0;
824 int size_compressed;
825 int size_uncompressed = 0;
826
827 if (argc == NUM_2) {
828 addr = simple_strtoul(argv[NUM_1], NULL, 16); /* 16:base */
829 flush_dcache_all();
830 return __run_a53cpu1(addr);
831 }
832 if (argc != NUM_5)
833 return CMD_RET_USAGE;
834
835 #ifdef CONFIG_SECURE_SCHEME_ENABLE
836 tzasc_init();
837 #endif
838 addr = simple_strtoul(argv[NUM_1], NULL, 16); /* 16:base */
839 srcaddr = simple_strtoul(argv[NUM_2], NULL, 16); /* 16:base */
840 offset = simple_strtoul(argv[NUM_3], NULL, 16); /* 16:base */
841 maxsize = simple_strtoul(argv[NUM_4], NULL, 16); /* 16:base */
842
843 /* 0x80:Read A53bin size */
844 ret = boot_intf_p->read(offset, 0x80, (void *)srcaddr);
845 flush_dcache_all();
846
847 /* read A53bin to DDR */
848 size_compressed = *(int *)(srcaddr + COMPRESSED_SIZE_OFFSET);
849 if (page_size_align(size_compressed) > maxsize) {
850 printf("->a53 Image size infor error !\n");
851 return 0;
852 }
853
854 boot_intf_p->read(offset, page_size_align(size_compressed),
855 (void *)srcaddr);
856 flush_dcache_all();
857
858 size_compressed = *(int *)(srcaddr + COMPRESSED_SIZE_OFFSET);
859 size_uncompressed = *(int *)(srcaddr + UNCOMPRESSED_SIZE_OFFSET);
860
861 hw_dec_init();
862 ret = hw_dec_decompress(NULL, (unsigned char *)(uintptr_t)addr, &size_uncompressed,
863 NULL, ((unsigned char *)(uintptr_t)srcaddr +
864 HIGZIP_HEAD_SIZE), size_compressed, NULL);
865 if (ret)
866 printf("->a53 decompress Fail!\n");
867
868 hw_dec_uinit();
869
870 return __run_a53cpu1(addr);
871 }
872
873 U_BOOT_CMD(
874 go_a53cpu1, CONFIG_SYS_MAXARGS, 3, start_a53cpu1,
875 "start a53-cpu1 at address 'addr'",
876 "addr [arg ...]\n - start a53 application at address 'addr'\n"
877 " passing 'arg' as arguments"
878 );
879 #else
start_a53cpu1(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])880 static int start_a53cpu1(cmd_tbl_t *cmdtp, int flag, int argc,
881 char *const argv[])
882 {
883 unsigned int addr;
884
885 if (argc < NUM_2)
886 return CMD_RET_USAGE;
887
888 #ifdef CONFIG_SECURE_SCHEME_ENABLE
889 tzasc_init();
890 #endif
891 addr = simple_strtoul(argv[NUM_1], NULL, 16); /* 16:base */
892 printf("## Starting A53 at 0x%08X ...\n", addr);
893 /* start up a53 */
894 {
895 unsigned int start_phys = 0;
896 unsigned int crg_phys = 0x04510000; /* 0x04510000:crg base */
897 unsigned int regval;
898
899 /* 0xe51ff004 = "ldr pc, [pc, #-4]" */
900 writel(0xe51ff004, start_phys);
901 /* 0x4:next addr value will be the "go_a53" addr */
902 writel(addr, (start_phys + 0x4));
903
904 asm("dsb");
905 asm("isb");
906
907 /* clear the slave cpu reset */
908 regval = readl(crg_phys + 0xcc);
909 regval &= ~(0x1 << 5); /* 0x1,5:corel soft reset request */
910 regval &= ~(0x1 << 25); /* 0x1,25:cluster1 soft reset request */
911 writel(regval, (crg_phys + 0xcc));
912 }
913 return 0;
914 }
915
916 U_BOOT_CMD(
917 go_a53cpu1, CONFIG_SYS_MAXARGS, 1, start_a53cpu1,
918 "start a53-cpu1 at address 'addr'",
919 "addr [arg ...]\n - start a53 application at address 'addr'\n"
920 " passing 'arg' as arguments"
921 );
922
923 #endif
924