1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <init.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/spi.h>
20 #include <env.h>
21 #include <linux/errno.h>
22 #include <asm/gpio.h>
23 #include <mmc.h>
24 #include <i2c.h>
25 #include <fsl_esdhc_imx.h>
26 #include <nand.h>
27 #include <miiphy.h>
28 #include <netdev.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/sections.h>
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
35 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
36 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
39 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
44
45 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
46 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
47
48 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51
52 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
53
54 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
55 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
56
57 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
58 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
59
60 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
61 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
62 #define GREEN_LED IMX_GPIO_NR(2, 31)
63 #define RED_LED IMX_GPIO_NR(1, 30)
64 #define IMX6Q_DRIVE_STRENGTH 0x30
65
dram_init(void)66 int dram_init(void)
67 {
68 gd->ram_size = imx_ddr_size();
69 return 0;
70 }
71
72 static iomux_v3_cfg_t const uart4_pads[] = {
73 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
74 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
75 };
76
77 static iomux_v3_cfg_t const enet_pads[] = {
78 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
86 MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
88 MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
92 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
94 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
95 MUX_PAD_CTRL(ENET_PAD_CTRL)),
96 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 };
98
99 static iomux_v3_cfg_t const ecspi3_pads[] = {
100 IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
101 IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
102 IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
103 IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
104 };
105
106 static iomux_v3_cfg_t const gpios_pads[] = {
107 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
108 IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
109 IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
110 IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
111 IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
113 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
114 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
115 };
116
117 #ifdef CONFIG_CMD_NAND
118 /* NAND */
119 static iomux_v3_cfg_t const nfc_pads[] = {
120 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
121 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
122 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
123 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
124 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
125 IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
126 IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
127 IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
128 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
129 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
130 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
131 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
132 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
133 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
134 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
135 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
136 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
137 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
138 IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)),
139 };
140 #endif
141
142 static struct i2c_pads_info i2c_pad_info = {
143 .scl = {
144 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
145 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
146 .gp = IMX_GPIO_NR(3, 21)
147 },
148 .sda = {
149 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
150 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
151 .gp = IMX_GPIO_NR(3, 28)
152 }
153 };
154
155 static struct fsl_esdhc_cfg usdhc_cfg[] = {
156 {USDHC3_BASE_ADDR,
157 .max_bus_width = 4},
158 {.esdhc_base = USDHC2_BASE_ADDR,
159 .max_bus_width = 4},
160 };
161
162 #if !defined(CONFIG_SPL_BUILD)
163 static iomux_v3_cfg_t const usdhc2_pads[] = {
164 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
165 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
166 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
167 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
168 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
169 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
170 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
171 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
172 };
173 #endif
174
175 static iomux_v3_cfg_t const usdhc3_pads[] = {
176 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
177 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
178 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
179 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
180 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
181 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
182 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
183 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
184 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
185 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
186 };
187
board_mmc_get_env_dev(int devno)188 int board_mmc_get_env_dev(int devno)
189 {
190 return devno - 1;
191 }
192
board_mmc_getcd(struct mmc * mmc)193 int board_mmc_getcd(struct mmc *mmc)
194 {
195 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
196 int ret = 0;
197
198 switch (cfg->esdhc_base) {
199 case USDHC2_BASE_ADDR:
200 ret = !gpio_get_value(USDHC2_CD_GPIO);
201 ret = 1;
202 break;
203 case USDHC3_BASE_ADDR:
204 ret = 1;
205 break;
206 }
207
208 return ret;
209 }
210
211 #ifndef CONFIG_SPL_BUILD
board_mmc_init(bd_t * bis)212 int board_mmc_init(bd_t *bis)
213 {
214 int ret;
215 int i;
216
217 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
218 switch (i) {
219 case 0:
220 SETUP_IOMUX_PADS(usdhc3_pads);
221 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
222 break;
223 case 1:
224 SETUP_IOMUX_PADS(usdhc2_pads);
225 gpio_direction_input(USDHC2_CD_GPIO);
226 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
227 break;
228 default:
229 printf("Warning: you configured more USDHC controllers"
230 "(%d) then supported by the board (%d)\n",
231 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
232 return -EINVAL;
233 }
234
235 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
236 if (ret)
237 return ret;
238 }
239
240 return 0;
241 }
242 #endif
243
setup_iomux_uart(void)244 static void setup_iomux_uart(void)
245 {
246 SETUP_IOMUX_PADS(uart4_pads);
247 }
248
setup_iomux_enet(void)249 static void setup_iomux_enet(void)
250 {
251 SETUP_IOMUX_PADS(enet_pads);
252
253 gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
254 mdelay(10);
255 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
256 mdelay(30);
257 }
258
setup_spi(void)259 static void setup_spi(void)
260 {
261 gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
262 gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
263
264 SETUP_IOMUX_PADS(ecspi3_pads);
265
266 enable_spi_clk(true, 2);
267 }
268
setup_gpios(void)269 static void setup_gpios(void)
270 {
271 SETUP_IOMUX_PADS(gpios_pads);
272 }
273
274 #ifdef CONFIG_CMD_NAND
setup_gpmi_nand(void)275 static void setup_gpmi_nand(void)
276 {
277 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
278
279 /* config gpmi nand iomux */
280 SETUP_IOMUX_PADS(nfc_pads);
281
282 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
283 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
284
285 /* config gpmi and bch clock to 100 MHz */
286 clrsetbits_le32(&mxc_ccm->cs2cdr,
287 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
288 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
289 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
290 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
291 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
292 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
293
294 /* enable ENFC_CLK_ROOT clock */
295 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
296
297 /* enable gpmi and bch clock gating */
298 setbits_le32(&mxc_ccm->CCGR4,
299 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
300 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
301 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
302 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
303 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
304
305 /* enable apbh clock gating */
306 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
307 }
308 #endif
309
310 /*
311 * Board revision is coded in 4 GPIOs
312 */
get_board_rev(void)313 u32 get_board_rev(void)
314 {
315 u32 rev;
316 int i;
317
318 for (i = 0, rev = 0; i < 4; i++)
319 rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
320
321 return 16 - rev;
322 }
323
board_spi_cs_gpio(unsigned bus,unsigned cs)324 int board_spi_cs_gpio(unsigned bus, unsigned cs)
325 {
326 if (bus != 2 || (cs != 0))
327 return -EINVAL;
328
329 return IMX_GPIO_NR(4, 24);
330 }
331
board_eth_init(bd_t * bis)332 int board_eth_init(bd_t *bis)
333 {
334 setup_iomux_enet();
335
336 return cpu_eth_init(bis);
337 }
338
board_early_init_f(void)339 int board_early_init_f(void)
340 {
341 setup_iomux_uart();
342
343 return 0;
344 }
345
board_init(void)346 int board_init(void)
347 {
348 /* address of boot parameters */
349 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
350
351 #ifdef CONFIG_SYS_I2C_MXC
352 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
353 #endif
354
355 #ifdef CONFIG_MXC_SPI
356 setup_spi();
357 #endif
358
359 setup_gpios();
360
361 #ifdef CONFIG_CMD_NAND
362 setup_gpmi_nand();
363 #endif
364 return 0;
365 }
366
367
368 #ifdef CONFIG_CMD_BMODE
369 /*
370 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
371 * see Table 8-11 and Table 5-9
372 * BOOT_CFG1[7] = 1 (boot from NAND)
373 * BOOT_CFG1[5] = 0 - raw NAND
374 * BOOT_CFG1[4] = 0 - default pad settings
375 * BOOT_CFG1[3:2] = 00 - devices = 1
376 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
377 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
378 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
379 * BOOT_CFG2[0] = 0 - Reset time 12ms
380 */
381 static const struct boot_mode board_boot_modes[] = {
382 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
383 {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
384 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
385 {NULL, 0},
386 };
387 #endif
388
board_late_init(void)389 int board_late_init(void)
390 {
391 char buf[10];
392 #ifdef CONFIG_CMD_BMODE
393 add_board_boot_modes(board_boot_modes);
394 #endif
395
396 snprintf(buf, sizeof(buf), "%d", get_board_rev());
397 env_set("board_rev", buf);
398
399 return 0;
400 }
401
402 #ifdef CONFIG_SPL_BUILD
403 #include <asm/arch/mx6-ddr.h>
404 #include <spl.h>
405 #include <linux/libfdt.h>
406
407 #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
phyflex_err006282_workaround(void)408 static void phyflex_err006282_workaround(void)
409 {
410 /*
411 * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
412 * to the CMIC. If this pin isn't toggled within 10s the boards
413 * reset. The pin is unconnected on older boards, so we do not
414 * need a check for older boards before applying this fixup.
415 */
416
417 gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
418 mdelay(2);
419 gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
420 mdelay(2);
421 gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
422
423 gpio_direction_input(MX6_PHYFLEX_ERR006282);
424 }
425
426 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
427 .dram_sdclk_0 = 0x00000030,
428 .dram_sdclk_1 = 0x00000030,
429 .dram_cas = 0x00000030,
430 .dram_ras = 0x00000030,
431 .dram_reset = 0x00000030,
432 .dram_sdcke0 = 0x00003000,
433 .dram_sdcke1 = 0x00003000,
434 .dram_sdba2 = 0x00000030,
435 .dram_sdodt0 = 0x00000030,
436 .dram_sdodt1 = 0x00000030,
437
438 .dram_sdqs0 = 0x00000028,
439 .dram_sdqs1 = 0x00000028,
440 .dram_sdqs2 = 0x00000028,
441 .dram_sdqs3 = 0x00000028,
442 .dram_sdqs4 = 0x00000028,
443 .dram_sdqs5 = 0x00000028,
444 .dram_sdqs6 = 0x00000028,
445 .dram_sdqs7 = 0x00000028,
446 .dram_dqm0 = 0x00000028,
447 .dram_dqm1 = 0x00000028,
448 .dram_dqm2 = 0x00000028,
449 .dram_dqm3 = 0x00000028,
450 .dram_dqm4 = 0x00000028,
451 .dram_dqm5 = 0x00000028,
452 .dram_dqm6 = 0x00000028,
453 .dram_dqm7 = 0x00000028,
454 };
455
456 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
457 .grp_ddr_type = 0x000C0000,
458 .grp_ddrmode_ctl = 0x00020000,
459 .grp_ddrpke = 0x00000000,
460 .grp_addds = IMX6Q_DRIVE_STRENGTH,
461 .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
462 .grp_ddrmode = 0x00020000,
463 .grp_b0ds = 0x00000028,
464 .grp_b1ds = 0x00000028,
465 .grp_b2ds = 0x00000028,
466 .grp_b3ds = 0x00000028,
467 .grp_b4ds = 0x00000028,
468 .grp_b5ds = 0x00000028,
469 .grp_b6ds = 0x00000028,
470 .grp_b7ds = 0x00000028,
471 };
472
473 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
474 .p0_mpwldectrl0 = 0x00110011,
475 .p0_mpwldectrl1 = 0x00240024,
476 .p1_mpwldectrl0 = 0x00260038,
477 .p1_mpwldectrl1 = 0x002C0038,
478 .p0_mpdgctrl0 = 0x03400350,
479 .p0_mpdgctrl1 = 0x03440340,
480 .p1_mpdgctrl0 = 0x034C0354,
481 .p1_mpdgctrl1 = 0x035C033C,
482 .p0_mprddlctl = 0x322A2A2A,
483 .p1_mprddlctl = 0x302C2834,
484 .p0_mpwrdlctl = 0x34303834,
485 .p1_mpwrdlctl = 0x422A3E36,
486 };
487
488 /* Index in RAM Chip array */
489 enum {
490 RAM_MT64K,
491 RAM_MT128K,
492 RAM_MT256K
493 };
494
495 static struct mx6_ddr3_cfg mt41k_xx[] = {
496 /* MT41K64M16JT-125 (1Gb density) */
497 {
498 .mem_speed = 1600,
499 .density = 1,
500 .width = 16,
501 .banks = 8,
502 .rowaddr = 13,
503 .coladdr = 10,
504 .pagesz = 2,
505 .trcd = 1375,
506 .trcmin = 4875,
507 .trasmin = 3500,
508 .SRT = 1,
509 },
510
511 /* MT41K256M16JT-125 (2Gb density) */
512 {
513 .mem_speed = 1600,
514 .density = 2,
515 .width = 16,
516 .banks = 8,
517 .rowaddr = 14,
518 .coladdr = 10,
519 .pagesz = 2,
520 .trcd = 1375,
521 .trcmin = 4875,
522 .trasmin = 3500,
523 .SRT = 1,
524 },
525
526 /* MT41K256M16JT-125 (4Gb density) */
527 {
528 .mem_speed = 1600,
529 .density = 4,
530 .width = 16,
531 .banks = 8,
532 .rowaddr = 15,
533 .coladdr = 10,
534 .pagesz = 2,
535 .trcd = 1375,
536 .trcmin = 4875,
537 .trasmin = 3500,
538 .SRT = 1,
539 }
540 };
541
ccgr_init(void)542 static void ccgr_init(void)
543 {
544 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
545
546 writel(0x00C03F3F, &ccm->CCGR0);
547 writel(0x0030FC03, &ccm->CCGR1);
548 writel(0x0FFFC000, &ccm->CCGR2);
549 writel(0x3FF00000, &ccm->CCGR3);
550 writel(0x00FFF300, &ccm->CCGR4);
551 writel(0x0F0000C3, &ccm->CCGR5);
552 writel(0x000003FF, &ccm->CCGR6);
553 }
554
spl_dram_init(struct mx6_ddr_sysinfo * sysinfo,struct mx6_ddr3_cfg * mem_ddr)555 static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
556 struct mx6_ddr3_cfg *mem_ddr)
557 {
558 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
559 mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
560 }
561
board_mmc_init(bd_t * bis)562 int board_mmc_init(bd_t *bis)
563 {
564 if (spl_boot_device() == BOOT_DEVICE_SPI)
565 printf("MMC SEtup, Boot SPI");
566
567 SETUP_IOMUX_PADS(usdhc3_pads);
568 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
569 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
570 usdhc_cfg[0].max_bus_width = 4;
571 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
572
573 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
574 }
575
576
board_boot_order(u32 * spl_boot_list)577 void board_boot_order(u32 *spl_boot_list)
578 {
579 spl_boot_list[0] = spl_boot_device();
580 printf("Boot device %x\n", spl_boot_list[0]);
581 switch (spl_boot_list[0]) {
582 case BOOT_DEVICE_SPI:
583 spl_boot_list[1] = BOOT_DEVICE_UART;
584 break;
585 case BOOT_DEVICE_MMC1:
586 spl_boot_list[1] = BOOT_DEVICE_SPI;
587 spl_boot_list[2] = BOOT_DEVICE_UART;
588 break;
589 default:
590 printf("Boot device %x\n", spl_boot_list[0]);
591 }
592 }
593
594 /*
595 * This is used because get_ram_size() does not
596 * take care of cache, resulting a wrong size
597 * pfla02 has just 1, 2 or 4 GB option
598 * Function checks for mirrors in the first CS
599 */
600 #define RAM_TEST_PATTERN 0xaa5555aa
601 #define MIN_BANK_SIZE (512 * 1024 * 1024)
602
pfla02_detect_chiptype(void)603 static unsigned int pfla02_detect_chiptype(void)
604 {
605 u32 *p, *p1;
606 unsigned int offset = MIN_BANK_SIZE;
607 int i;
608
609 for (i = 0; i < 2; i++) {
610 p = (u32 *)PHYS_SDRAM;
611 p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
612
613 *p1 = 0;
614 *p = RAM_TEST_PATTERN;
615
616 /*
617 * This is required to detect mirroring
618 * else we read back values from cache
619 */
620 flush_dcache_all();
621
622 if (*p == *p1)
623 return i;
624 }
625 return RAM_MT256K;
626 }
627
board_init_f(ulong dummy)628 void board_init_f(ulong dummy)
629 {
630 unsigned int ramchip;
631
632 struct mx6_ddr_sysinfo sysinfo = {
633 /* width of data bus:0=16,1=32,2=64 */
634 .dsize = 2,
635 /* config for full 4GB range so that get_mem_size() works */
636 .cs_density = 32, /* 512 MB */
637 /* single chip select */
638 #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
639 .ncs = 1,
640 #else
641 .ncs = 2,
642 #endif
643 .cs1_mirror = 1,
644 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
645 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
646 .walat = 1, /* Write additional latency */
647 .ralat = 5, /* Read additional latency */
648 .mif3_mode = 3, /* Command prediction working mode */
649 .bi_on = 1, /* Bank interleaving enabled */
650 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
651 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
652 .ddr_type = DDR_TYPE_DDR3,
653 .refsel = 1, /* Refresh cycles at 32KHz */
654 .refr = 7, /* 8 refresh commands per refresh cycle */
655 };
656
657 #ifdef CONFIG_CMD_NAND
658 /* Enable NAND */
659 setup_gpmi_nand();
660 #endif
661
662 /* setup clock gating */
663 ccgr_init();
664
665 /* setup AIPS and disable watchdog */
666 arch_cpu_init();
667
668 /* setup AXI */
669 gpr_init();
670
671 board_early_init_f();
672
673 /* setup GP timer */
674 timer_init();
675
676 /* UART clocks enabled and gd valid - init serial console */
677 preloader_console_init();
678
679 setup_spi();
680
681 setup_gpios();
682
683 /* DDR initialization */
684 spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
685 ramchip = pfla02_detect_chiptype();
686 debug("Detected chip %d\n", ramchip);
687 #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
688 switch (ramchip) {
689 case RAM_MT64K:
690 sysinfo.cs_density = 6;
691 break;
692 case RAM_MT128K:
693 sysinfo.cs_density = 10;
694 break;
695 case RAM_MT256K:
696 sysinfo.cs_density = 18;
697 break;
698 }
699 #endif
700 spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
701
702 /* Clear the BSS. */
703 memset(__bss_start, 0, __bss_end - __bss_start);
704
705 phyflex_err006282_workaround();
706
707 /* load/boot image from boot device */
708 board_init_r(NULL, 0);
709 }
710 #endif
711