1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Renesas Solutions Corp.
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <init.h>
9 #include <malloc.h>
10 #include <asm/processor.h>
11 #include <asm/io.h>
12 #include <asm/mmc.h>
13 #include <spi.h>
14 #include <spi_flash.h>
15
checkboard(void)16 int checkboard(void)
17 {
18 puts("BOARD: SH7753 EVB\n");
19
20 return 0;
21 }
22
init_gpio(void)23 static void init_gpio(void)
24 {
25 struct gpio_regs *gpio = GPIO_BASE;
26 struct sermux_regs *sermux = SERMUX_BASE;
27
28 /* GPIO */
29 writew(0x0000, &gpio->pacr); /* GETHER */
30 writew(0x0001, &gpio->pbcr); /* INTC */
31 writew(0x0000, &gpio->pccr); /* PWMU, INTC */
32 writew(0x0000, &gpio->pdcr); /* SPI0 */
33 writew(0xeaff, &gpio->pecr); /* GPIO */
34 writew(0x0000, &gpio->pfcr); /* WDT */
35 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
36 writew(0x0000, &gpio->phcr); /* SPI1 */
37 writew(0x0000, &gpio->picr); /* SDHI */
38 writew(0x0000, &gpio->pjcr); /* SCIF4 */
39 writew(0x0003, &gpio->pkcr); /* SerMux */
40 writew(0x0000, &gpio->plcr); /* SerMux */
41 writew(0x0000, &gpio->pmcr); /* RIIC */
42 writew(0x0000, &gpio->pncr); /* USB, SGPIO */
43 writew(0x0000, &gpio->pocr); /* SGPIO */
44 writew(0xd555, &gpio->pqcr); /* GPIO */
45 writew(0x0000, &gpio->prcr); /* RIIC */
46 writew(0x0000, &gpio->pscr); /* RIIC */
47 writew(0x0000, &gpio->ptcr); /* STATUS */
48 writeb(0x00, &gpio->pudr);
49 writew(0x5555, &gpio->pucr); /* Debug LED */
50 writew(0x0000, &gpio->pvcr); /* RSPI */
51 writew(0x0000, &gpio->pwcr); /* EVC */
52 writew(0x0000, &gpio->pxcr); /* LBSC */
53 writew(0x0000, &gpio->pycr); /* LBSC */
54 writew(0x0000, &gpio->pzcr); /* eMMC */
55 writew(0xfe00, &gpio->psel0);
56 writew(0x0000, &gpio->psel1);
57 writew(0x3000, &gpio->psel2);
58 writew(0xff00, &gpio->psel3);
59 writew(0x771f, &gpio->psel4);
60 writew(0x0ffc, &gpio->psel5);
61 writew(0x00ff, &gpio->psel6);
62 writew(0xfc00, &gpio->psel7);
63
64 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
65 }
66
init_usb_phy(void)67 static void init_usb_phy(void)
68 {
69 struct usb_common_regs *common0 = USB0_COMMON_BASE;
70 struct usb_common_regs *common1 = USB1_COMMON_BASE;
71 struct usb0_phy_regs *phy = USB0_PHY_BASE;
72 struct usb1_port_regs *port = USB1_PORT_BASE;
73 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
74
75 writew(0x0100, &phy->reset); /* set reset */
76 /* port0 = USB0, port1 = USB1 */
77 writew(0x0002, &phy->portsel);
78 writel(0x0001, &port->port1sel); /* port1 = Host */
79 writew(0x0111, &phy->reset); /* clear reset */
80
81 writew(0x4000, &common0->suspmode);
82 writew(0x4000, &common1->suspmode);
83
84 #if defined(__LITTLE_ENDIAN)
85 writel(0x00000000, &align->ehcidatac);
86 writel(0x00000000, &align->ohcidatac);
87 #endif
88 }
89
init_gether_mdio(void)90 static void init_gether_mdio(void)
91 {
92 struct gpio_regs *gpio = GPIO_BASE;
93
94 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
95 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
96 }
97
set_mac_to_sh_giga_eth_register(int channel,char * mac_string)98 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
99 {
100 struct ether_mac_regs *ether;
101 unsigned char mac[6];
102 unsigned long val;
103
104 string_to_enetaddr(mac_string, mac);
105
106 if (!channel)
107 ether = GETHER0_MAC_BASE;
108 else
109 ether = GETHER1_MAC_BASE;
110
111 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
112 writel(val, ðer->mahr);
113 val = (mac[4] << 8) | mac[5];
114 writel(val, ðer->malr);
115 }
116
117 #if defined(CONFIG_SH_32BIT)
118 /*****************************************************************
119 * This PMB must be set on this timing. The lowlevel_init is run on
120 * Area 0(phys 0x00000000), so we have to map it.
121 *
122 * The new PMB table is following:
123 * ent virt phys v sz c wt
124 * 0 0xa0000000 0x40000000 1 128M 0 1
125 * 1 0xa8000000 0x48000000 1 128M 0 1
126 * 2 0xb0000000 0x50000000 1 128M 0 1
127 * 3 0xb8000000 0x58000000 1 128M 0 1
128 * 4 0x80000000 0x40000000 1 128M 1 1
129 * 5 0x88000000 0x48000000 1 128M 1 1
130 * 6 0x90000000 0x50000000 1 128M 1 1
131 * 7 0x98000000 0x58000000 1 128M 1 1
132 */
set_pmb_on_board_init(void)133 static void set_pmb_on_board_init(void)
134 {
135 struct mmu_regs *mmu = MMU_BASE;
136
137 /* clear ITLB */
138 writel(0x00000004, &mmu->mmucr);
139
140 /* delete PMB for SPIBOOT */
141 writel(0, PMB_ADDR_BASE(0));
142 writel(0, PMB_DATA_BASE(0));
143
144 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
145 /* ppn ub v s1 s0 c wt */
146 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
147 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
148 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
149 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
150 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
151 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
152 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
153 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
154 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
155 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
156 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
157 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
158 }
159 #endif
160
board_init(void)161 int board_init(void)
162 {
163 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
164
165 init_gpio();
166 #if defined(CONFIG_SH_32BIT)
167 set_pmb_on_board_init();
168 #endif
169
170 /* Sets TXnDLY to B'010 */
171 writel(0x00000202, &gether->gbecont);
172
173 init_usb_phy();
174 init_gether_mdio();
175
176 return 0;
177 }
178
board_mmc_init(bd_t * bis)179 int board_mmc_init(bd_t *bis)
180 {
181 struct gpio_regs *gpio = GPIO_BASE;
182
183 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
184 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
185 udelay(1);
186 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
187 udelay(200);
188
189 return mmcif_mmc_init();
190 }
191
get_sh_eth_mac_raw(unsigned char * buf,int size)192 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
193 {
194 #ifdef CONFIG_DEPRECATED
195 struct spi_flash *spi;
196 int ret;
197
198 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
199 if (spi == NULL) {
200 printf("%s: spi_flash probe failed.\n", __func__);
201 return 1;
202 }
203
204 ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
205 if (ret) {
206 printf("%s: spi_flash read failed.\n", __func__);
207 spi_flash_free(spi);
208 return 1;
209 }
210 spi_flash_free(spi);
211 #endif
212
213 return 0;
214 }
215
get_sh_eth_mac(int channel,char * mac_string,unsigned char * buf)216 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
217 {
218 memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
219 SH7753EVB_ETHERNET_MAC_SIZE);
220 mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
221
222 return 0;
223 }
224
init_ethernet_mac(void)225 static void init_ethernet_mac(void)
226 {
227 char mac_string[64];
228 char env_string[64];
229 int i;
230 unsigned char *buf;
231
232 buf = malloc(256);
233 if (!buf) {
234 printf("%s: malloc failed.\n", __func__);
235 return;
236 }
237 get_sh_eth_mac_raw(buf, 256);
238
239 /* Gigabit Ethernet */
240 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
241 get_sh_eth_mac(i, mac_string, buf);
242 if (i == 0)
243 env_set("ethaddr", mac_string);
244 else {
245 sprintf(env_string, "eth%daddr", i);
246 env_set(env_string, mac_string);
247 }
248 set_mac_to_sh_giga_eth_register(i, mac_string);
249 }
250
251 free(buf);
252 }
253
board_late_init(void)254 int board_late_init(void)
255 {
256 init_ethernet_mac();
257
258 return 0;
259 }
260
261 #ifdef CONFIG_DEPRECATED
do_write_mac(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])262 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
263 {
264 int i, ret;
265 char mac_string[256];
266 struct spi_flash *spi;
267 unsigned char *buf;
268
269 if (argc != 3) {
270 buf = malloc(256);
271 if (!buf) {
272 printf("%s: malloc failed.\n", __func__);
273 return 1;
274 }
275
276 get_sh_eth_mac_raw(buf, 256);
277
278 /* print current MAC address */
279 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
280 get_sh_eth_mac(i, mac_string, buf);
281 printf("GETHERC ch%d = %s\n", i, mac_string);
282 }
283 free(buf);
284 return 0;
285 }
286
287 /* new setting */
288 memset(mac_string, 0xff, sizeof(mac_string));
289 sprintf(mac_string, "%s\t%s",
290 argv[1], argv[2]);
291
292 /* write MAC data to SPI rom */
293 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
294 if (!spi) {
295 printf("%s: spi_flash probe failed.\n", __func__);
296 return 1;
297 }
298
299 ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
300 SH7753EVB_SPI_SECTOR_SIZE);
301 if (ret) {
302 printf("%s: spi_flash erase failed.\n", __func__);
303 return 1;
304 }
305
306 ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
307 sizeof(mac_string), mac_string);
308 if (ret) {
309 printf("%s: spi_flash write failed.\n", __func__);
310 spi_flash_free(spi);
311 return 1;
312 }
313 spi_flash_free(spi);
314
315 puts("The writing of the MAC address to SPI ROM was completed.\n");
316
317 return 0;
318 }
319
320 U_BOOT_CMD(
321 write_mac, 3, 1, do_write_mac,
322 "write MAC address for GETHERC",
323 "[GETHERC ch0] [GETHERC ch1]\n"
324 );
325 #endif
326