1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 Renesas Solutions Corp.
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <init.h>
9 #include <malloc.h>
10 #include <asm/processor.h>
11 #include <asm/io.h>
12 #include <asm/mmc.h>
13 #include <spi.h>
14 #include <spi_flash.h>
15
checkboard(void)16 int checkboard(void)
17 {
18 puts("BOARD: R0P7757LC0030RL board\n");
19
20 return 0;
21 }
22
init_gctrl(void)23 static void init_gctrl(void)
24 {
25 struct gctrl_regs *gctrl = GCTRL_BASE;
26 unsigned long graofst;
27
28 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
29 writel(graofst | 0x20000f00, &gctrl->gracr3);
30 }
31
init_pcie_bridge_from_spi(void * buf,size_t size)32 static int init_pcie_bridge_from_spi(void *buf, size_t size)
33 {
34 #ifdef CONFIG_DEPRECATED
35 struct spi_flash *spi;
36 int ret;
37 unsigned long pcie_addr;
38
39 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
40 if (!spi) {
41 printf("%s: spi_flash probe error.\n", __func__);
42 return 1;
43 }
44
45 if (is_sh7757_b0())
46 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
47 else
48 pcie_addr = SH7757LCR_PCIEBRG_ADDR;
49
50 ret = spi_flash_read(spi, pcie_addr, size, buf);
51 if (ret) {
52 printf("%s: spi_flash read error.\n", __func__);
53 spi_flash_free(spi);
54 return 1;
55 }
56 spi_flash_free(spi);
57
58 return 0;
59 #else
60 printf("No SPI support so no PCIe support\n");
61 return 1;
62 #endif
63 }
64
init_pcie_bridge(void)65 static void init_pcie_bridge(void)
66 {
67 struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
68 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
69 int i;
70 unsigned char *data;
71 unsigned short tmp;
72 unsigned long pcie_size;
73
74 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
75 return;
76
77 if (is_sh7757_b0())
78 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
79 else
80 pcie_size = SH7757LCR_PCIEBRG_SIZE;
81
82 data = malloc(pcie_size);
83 if (!data) {
84 printf("%s: malloc error.\n", __func__);
85 return;
86 }
87 if (init_pcie_bridge_from_spi(data, pcie_size)) {
88 free(data);
89 return;
90 }
91
92 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
93 data[3] == 0xff) {
94 free(data);
95 printf("%s: skipped initialization\n", __func__);
96 return;
97 }
98
99 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
100 writew(0x0000, &pciebrg->cp_ctrl);
101 writew(0x0000, &pciebrg->cp_addr);
102
103 for (i = 0; i < pcie_size; i += 2) {
104 tmp = (data[i] << 8) | data[i + 1];
105 writew(tmp, &pciebrg->cp_data);
106 }
107
108 writew(0xa500, &pciebrg->ctrl_h8s); /* start */
109 if (!is_sh7757_b0())
110 writel(0x00000001, &pcie_setup->pbictl3);
111
112 free(data);
113 }
114
init_usb_phy(void)115 static void init_usb_phy(void)
116 {
117 struct usb_common_regs *common0 = USB0_COMMON_BASE;
118 struct usb_common_regs *common1 = USB1_COMMON_BASE;
119 struct usb0_phy_regs *phy = USB0_PHY_BASE;
120 struct usb1_port_regs *port = USB1_PORT_BASE;
121 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
122
123 writew(0x0100, &phy->reset); /* set reset */
124 /* port0 = USB0, port1 = USB1 */
125 writew(0x0002, &phy->portsel);
126 writel(0x0001, &port->port1sel); /* port1 = Host */
127 writew(0x0111, &phy->reset); /* clear reset */
128
129 writew(0x4000, &common0->suspmode);
130 writew(0x4000, &common1->suspmode);
131
132 #if defined(__LITTLE_ENDIAN)
133 writel(0x00000000, &align->ehcidatac);
134 writel(0x00000000, &align->ohcidatac);
135 #endif
136 }
137
set_mac_to_sh_eth_register(int channel,char * mac_string)138 static void set_mac_to_sh_eth_register(int channel, char *mac_string)
139 {
140 struct ether_mac_regs *ether;
141 unsigned char mac[6];
142 unsigned long val;
143
144 string_to_enetaddr(mac_string, mac);
145
146 if (!channel)
147 ether = ETHER0_MAC_BASE;
148 else
149 ether = ETHER1_MAC_BASE;
150
151 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
152 writel(val, ðer->mahr);
153 val = (mac[4] << 8) | mac[5];
154 writel(val, ðer->malr);
155 }
156
set_mac_to_sh_giga_eth_register(int channel,char * mac_string)157 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
158 {
159 struct ether_mac_regs *ether;
160 unsigned char mac[6];
161 unsigned long val;
162
163 string_to_enetaddr(mac_string, mac);
164
165 if (!channel)
166 ether = GETHER0_MAC_BASE;
167 else
168 ether = GETHER1_MAC_BASE;
169
170 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
171 writel(val, ðer->mahr);
172 val = (mac[4] << 8) | mac[5];
173 writel(val, ðer->malr);
174 }
175
176 /*****************************************************************
177 * This PMB must be set on this timing. The lowlevel_init is run on
178 * Area 0(phys 0x00000000), so we have to map it.
179 *
180 * The new PMB table is following:
181 * ent virt phys v sz c wt
182 * 0 0xa0000000 0x40000000 1 128M 0 1
183 * 1 0xa8000000 0x48000000 1 128M 0 1
184 * 2 0xb0000000 0x50000000 1 128M 0 1
185 * 3 0xb8000000 0x58000000 1 128M 0 1
186 * 4 0x80000000 0x40000000 1 128M 1 1
187 * 5 0x88000000 0x48000000 1 128M 1 1
188 * 6 0x90000000 0x50000000 1 128M 1 1
189 * 7 0x98000000 0x58000000 1 128M 1 1
190 */
set_pmb_on_board_init(void)191 static void set_pmb_on_board_init(void)
192 {
193 struct mmu_regs *mmu = MMU_BASE;
194
195 /* clear ITLB */
196 writel(0x00000004, &mmu->mmucr);
197
198 /* delete PMB for SPIBOOT */
199 writel(0, PMB_ADDR_BASE(0));
200 writel(0, PMB_DATA_BASE(0));
201
202 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
203 /* ppn ub v s1 s0 c wt */
204 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
205 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
206 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
207 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
208 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
209 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
210 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
211 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
212 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
213 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
214 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
215 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
216 }
217
board_init(void)218 int board_init(void)
219 {
220 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
221
222 set_pmb_on_board_init();
223
224 /* enable RMII's MDIO (disable GRMII's MDIO) */
225 writel(0x00030000, &gether->gbecont);
226
227 init_gctrl();
228 init_usb_phy();
229
230 return 0;
231 }
232
board_mmc_init(bd_t * bis)233 int board_mmc_init(bd_t *bis)
234 {
235 return mmcif_mmc_init();
236 }
237
get_sh_eth_mac_raw(unsigned char * buf,int size)238 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
239 {
240 #ifdef CONFIG_DEPRECATED
241 struct spi_flash *spi;
242 int ret;
243
244 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
245 if (spi == NULL) {
246 printf("%s: spi_flash probe error.\n", __func__);
247 return 1;
248 }
249
250 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
251 if (ret) {
252 printf("%s: spi_flash read error.\n", __func__);
253 spi_flash_free(spi);
254 return 1;
255 }
256 spi_flash_free(spi);
257 #endif
258
259 return 0;
260 }
261
get_sh_eth_mac(int channel,char * mac_string,unsigned char * buf)262 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
263 {
264 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
265 SH7757LCR_ETHERNET_MAC_SIZE);
266 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
267
268 return 0;
269 }
270
init_ethernet_mac(void)271 static void init_ethernet_mac(void)
272 {
273 char mac_string[64];
274 char env_string[64];
275 int i;
276 unsigned char *buf;
277
278 buf = malloc(256);
279 if (!buf) {
280 printf("%s: malloc error.\n", __func__);
281 return;
282 }
283 get_sh_eth_mac_raw(buf, 256);
284
285 /* Fast Ethernet */
286 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
287 get_sh_eth_mac(i, mac_string, buf);
288 if (i == 0)
289 env_set("ethaddr", mac_string);
290 else {
291 sprintf(env_string, "eth%daddr", i);
292 env_set(env_string, mac_string);
293 }
294
295 set_mac_to_sh_eth_register(i, mac_string);
296 }
297
298 /* Gigabit Ethernet */
299 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
300 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
301 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
302 env_set(env_string, mac_string);
303
304 set_mac_to_sh_giga_eth_register(i, mac_string);
305 }
306
307 free(buf);
308 }
309
init_pcie(void)310 static void init_pcie(void)
311 {
312 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
313 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
314
315 writel(0x00000ff2, &pcie_setup->ladmsk0);
316 writel(0x00000001, &pcie_setup->barmap);
317 writel(0xffcaa000, &pcie_setup->lad0);
318 writel(0x00030000, &pcie_sysbus->endictl0);
319 writel(0x00000003, &pcie_sysbus->endictl1);
320 writel(0x00000004, &pcie_setup->pbictl2);
321 }
322
finish_spiboot(void)323 static void finish_spiboot(void)
324 {
325 struct gctrl_regs *gctrl = GCTRL_BASE;
326 /*
327 * SH7757 B0 does not use LBSC.
328 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
329 * This setting is not cleared by manual reset, So we have to set it
330 * to 0.
331 */
332 writel(0x00000000, &gctrl->spibootcan);
333 }
334
board_late_init(void)335 int board_late_init(void)
336 {
337 init_ethernet_mac();
338 init_pcie_bridge();
339 init_pcie();
340 finish_spiboot();
341
342 return 0;
343 }
344
do_sh_g200(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])345 int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
346 {
347 struct gctrl_regs *gctrl = GCTRL_BASE;
348 unsigned long graofst;
349
350 writel(0xfedcba98, &gctrl->wprotect);
351 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
352 writel(graofst | 0xa0000f00, &gctrl->gracr3);
353
354 return 0;
355 }
356
357 U_BOOT_CMD(
358 sh_g200, 1, 1, do_sh_g200,
359 "enable sh-g200",
360 "enable SH-G200 bus (disable PCIe-G200)"
361 );
362
363 #ifdef CONFIG_DEPRECATED
do_write_mac(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])364 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
365 {
366 int i, ret;
367 char mac_string[256];
368 struct spi_flash *spi;
369 unsigned char *buf;
370
371 if (argc != 5) {
372 buf = malloc(256);
373 if (!buf) {
374 printf("%s: malloc error.\n", __func__);
375 return 1;
376 }
377
378 get_sh_eth_mac_raw(buf, 256);
379
380 /* print current MAC address */
381 for (i = 0; i < 4; i++) {
382 get_sh_eth_mac(i, mac_string, buf);
383 if (i < 2)
384 printf(" ETHERC ch%d = %s\n", i, mac_string);
385 else
386 printf("GETHERC ch%d = %s\n", i-2, mac_string);
387 }
388 free(buf);
389 return 0;
390 }
391
392 /* new setting */
393 memset(mac_string, 0xff, sizeof(mac_string));
394 sprintf(mac_string, "%s\t%s\t%s\t%s",
395 argv[1], argv[2], argv[3], argv[4]);
396
397 /* write MAC data to SPI rom */
398 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
399 if (!spi) {
400 printf("%s: spi_flash probe error.\n", __func__);
401 return 1;
402 }
403
404 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
405 SH7757LCR_SPI_SECTOR_SIZE);
406 if (ret) {
407 printf("%s: spi_flash erase error.\n", __func__);
408 return 1;
409 }
410
411 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
412 sizeof(mac_string), mac_string);
413 if (ret) {
414 printf("%s: spi_flash write error.\n", __func__);
415 spi_flash_free(spi);
416 return 1;
417 }
418 spi_flash_free(spi);
419
420 puts("The writing of the MAC address to SPI ROM was completed.\n");
421
422 return 0;
423 }
424
425 U_BOOT_CMD(
426 write_mac, 5, 1, do_write_mac,
427 "write MAC address for ETHERC/GETHERC",
428 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
429 );
430 #endif
431