1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
11 */
12
13 #include <common.h>
14 #include <dm.h>
15 #include <env.h>
16 #include <mmc.h>
17 #include <axp_pmic.h>
18 #include <generic-phy.h>
19 #include <phy-sun4i-usb.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/display.h>
23 #include <asm/arch/dram.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/mmc.h>
26 #include <asm/arch/spl.h>
27 #include <u-boot/crc.h>
28 #ifndef CONFIG_ARM64
29 #include <asm/armv7.h>
30 #endif
31 #include <asm/gpio.h>
32 #include <asm/io.h>
33 #include <u-boot/crc.h>
34 #include <env_internal.h>
35 #include <linux/libfdt.h>
36 #include <nand.h>
37 #include <net.h>
38 #include <spl.h>
39 #include <sy8106a.h>
40 #include <asm/setup.h>
41
42 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
43 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
44 int soft_i2c_gpio_sda;
45 int soft_i2c_gpio_scl;
46
soft_i2c_board_init(void)47 static int soft_i2c_board_init(void)
48 {
49 int ret;
50
51 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
52 if (soft_i2c_gpio_sda < 0) {
53 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
54 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
55 return soft_i2c_gpio_sda;
56 }
57 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
58 if (ret) {
59 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
60 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
61 return ret;
62 }
63
64 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
65 if (soft_i2c_gpio_scl < 0) {
66 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
67 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
68 return soft_i2c_gpio_scl;
69 }
70 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
71 if (ret) {
72 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
73 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
74 return ret;
75 }
76
77 return 0;
78 }
79 #else
soft_i2c_board_init(void)80 static int soft_i2c_board_init(void) { return 0; }
81 #endif
82
83 DECLARE_GLOBAL_DATA_PTR;
84
i2c_init_board(void)85 void i2c_init_board(void)
86 {
87 #ifdef CONFIG_I2C0_ENABLE
88 #if defined(CONFIG_MACH_SUN4I) || \
89 defined(CONFIG_MACH_SUN5I) || \
90 defined(CONFIG_MACH_SUN7I) || \
91 defined(CONFIG_MACH_SUN8I_R40)
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
94 clock_twi_onoff(0, 1);
95 #elif defined(CONFIG_MACH_SUN6I)
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
98 clock_twi_onoff(0, 1);
99 #elif defined(CONFIG_MACH_SUN8I)
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
102 clock_twi_onoff(0, 1);
103 #elif defined(CONFIG_MACH_SUN50I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
106 clock_twi_onoff(0, 1);
107 #endif
108 #endif
109
110 #ifdef CONFIG_I2C1_ENABLE
111 #if defined(CONFIG_MACH_SUN4I) || \
112 defined(CONFIG_MACH_SUN7I) || \
113 defined(CONFIG_MACH_SUN8I_R40)
114 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
115 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
116 clock_twi_onoff(1, 1);
117 #elif defined(CONFIG_MACH_SUN5I)
118 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
119 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
120 clock_twi_onoff(1, 1);
121 #elif defined(CONFIG_MACH_SUN6I)
122 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
123 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
124 clock_twi_onoff(1, 1);
125 #elif defined(CONFIG_MACH_SUN8I)
126 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
127 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
128 clock_twi_onoff(1, 1);
129 #elif defined(CONFIG_MACH_SUN50I)
130 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
131 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
132 clock_twi_onoff(1, 1);
133 #endif
134 #endif
135
136 #ifdef CONFIG_I2C2_ENABLE
137 #if defined(CONFIG_MACH_SUN4I) || \
138 defined(CONFIG_MACH_SUN7I) || \
139 defined(CONFIG_MACH_SUN8I_R40)
140 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
141 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
142 clock_twi_onoff(2, 1);
143 #elif defined(CONFIG_MACH_SUN5I)
144 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
145 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
146 clock_twi_onoff(2, 1);
147 #elif defined(CONFIG_MACH_SUN6I)
148 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
149 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
150 clock_twi_onoff(2, 1);
151 #elif defined(CONFIG_MACH_SUN8I)
152 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
153 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
154 clock_twi_onoff(2, 1);
155 #elif defined(CONFIG_MACH_SUN50I)
156 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
157 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
158 clock_twi_onoff(2, 1);
159 #endif
160 #endif
161
162 #ifdef CONFIG_I2C3_ENABLE
163 #if defined(CONFIG_MACH_SUN6I)
164 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
165 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
166 clock_twi_onoff(3, 1);
167 #elif defined(CONFIG_MACH_SUN7I) || \
168 defined(CONFIG_MACH_SUN8I_R40)
169 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
170 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
171 clock_twi_onoff(3, 1);
172 #endif
173 #endif
174
175 #ifdef CONFIG_I2C4_ENABLE
176 #if defined(CONFIG_MACH_SUN7I) || \
177 defined(CONFIG_MACH_SUN8I_R40)
178 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
179 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
180 clock_twi_onoff(4, 1);
181 #endif
182 #endif
183
184 #ifdef CONFIG_R_I2C_ENABLE
185 #ifdef CONFIG_MACH_SUN50I
186 clock_twi_onoff(5, 1);
187 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
188 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
189 #else
190 clock_twi_onoff(5, 1);
191 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
192 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
193 #endif
194 #endif
195 }
196
197 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
env_get_location(enum env_operation op,int prio)198 enum env_location env_get_location(enum env_operation op, int prio)
199 {
200 switch (prio) {
201 case 0:
202 return ENVL_FAT;
203
204 case 1:
205 return ENVL_MMC;
206
207 default:
208 return ENVL_UNKNOWN;
209 }
210 }
211 #endif
212
213 #ifdef CONFIG_DM_MMC
214 static void mmc_pinmux_setup(int sdc);
215 #endif
216
217 /* add board specific code here */
board_init(void)218 int board_init(void)
219 {
220 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
221
222 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
223
224 #ifndef CONFIG_ARM64
225 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
226 debug("id_pfr1: 0x%08x\n", id_pfr1);
227 /* Generic Timer Extension available? */
228 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
229 uint32_t freq;
230
231 debug("Setting CNTFRQ\n");
232
233 /*
234 * CNTFRQ is a secure register, so we will crash if we try to
235 * write this from the non-secure world (read is OK, though).
236 * In case some bootcode has already set the correct value,
237 * we avoid the risk of writing to it.
238 */
239 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
240 if (freq != COUNTER_FREQUENCY) {
241 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
242 freq, COUNTER_FREQUENCY);
243 #ifdef CONFIG_NON_SECURE
244 printf("arch timer frequency is wrong, but cannot adjust it\n");
245 #else
246 asm volatile("mcr p15, 0, %0, c14, c0, 0"
247 : : "r"(COUNTER_FREQUENCY));
248 #endif
249 }
250 }
251 #endif /* !CONFIG_ARM64 */
252
253 ret = axp_gpio_init();
254 if (ret)
255 return ret;
256
257 #ifdef CONFIG_SATAPWR
258 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
259 gpio_request(satapwr_pin, "satapwr");
260 gpio_direction_output(satapwr_pin, 1);
261 /* Give attached sata device time to power-up to avoid link timeouts */
262 mdelay(500);
263 #endif
264 #ifdef CONFIG_MACPWR
265 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
266 gpio_request(macpwr_pin, "macpwr");
267 gpio_direction_output(macpwr_pin, 1);
268 #endif
269
270 #ifdef CONFIG_DM_I2C
271 /*
272 * Temporary workaround for enabling I2C clocks until proper sunxi DM
273 * clk, reset and pinctrl drivers land.
274 */
275 i2c_init_board();
276 #endif
277
278 #ifdef CONFIG_DM_MMC
279 /*
280 * Temporary workaround for enabling MMC clocks until a sunxi DM
281 * pinctrl driver lands.
282 */
283 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
284 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
285 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
286 #endif
287 #endif /* CONFIG_DM_MMC */
288
289 /* Uses dm gpio code so do this here and not in i2c_init_board() */
290 return soft_i2c_board_init();
291 }
292
293 /*
294 * On older SoCs the SPL is actually at address zero, so using NULL as
295 * an error value does not work.
296 */
297 #define INVALID_SPL_HEADER ((void *)~0UL)
298
get_spl_header(uint8_t req_version)299 static struct boot_file_head * get_spl_header(uint8_t req_version)
300 {
301 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
302 uint8_t spl_header_version = spl->spl_signature[3];
303
304 /* Is there really the SPL header (still) there? */
305 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
306 return INVALID_SPL_HEADER;
307
308 if (spl_header_version < req_version) {
309 printf("sunxi SPL version mismatch: expected %u, got %u\n",
310 req_version, spl_header_version);
311 return INVALID_SPL_HEADER;
312 }
313
314 return spl;
315 }
316
dram_init(void)317 int dram_init(void)
318 {
319 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
320
321 if (spl == INVALID_SPL_HEADER)
322 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
323 PHYS_SDRAM_0_SIZE);
324 else
325 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
326
327 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
328 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
329
330 return 0;
331 }
332
333 #if defined(CONFIG_NAND_SUNXI)
nand_pinmux_setup(void)334 static void nand_pinmux_setup(void)
335 {
336 unsigned int pin;
337
338 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
339 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
340
341 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
342 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
343 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
344 #endif
345 /* sun4i / sun7i do have a PC23, but it is not used for nand,
346 * only sun7i has a PC24 */
347 #ifdef CONFIG_MACH_SUN7I
348 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
349 #endif
350 }
351
nand_clock_setup(void)352 static void nand_clock_setup(void)
353 {
354 struct sunxi_ccm_reg *const ccm =
355 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
356
357 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
358 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
359 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
360 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
361 #endif
362 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
363 }
364
board_nand_init(void)365 void board_nand_init(void)
366 {
367 nand_pinmux_setup();
368 nand_clock_setup();
369 #ifndef CONFIG_SPL_BUILD
370 sunxi_nand_init();
371 #endif
372 }
373 #endif
374
375 #ifdef CONFIG_MMC
mmc_pinmux_setup(int sdc)376 static void mmc_pinmux_setup(int sdc)
377 {
378 unsigned int pin;
379 __maybe_unused int pins;
380
381 switch (sdc) {
382 case 0:
383 /* SDC0: PF0-PF5 */
384 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
385 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
386 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
387 sunxi_gpio_set_drv(pin, 2);
388 }
389 break;
390
391 case 1:
392 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
393
394 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
395 defined(CONFIG_MACH_SUN8I_R40)
396 if (pins == SUNXI_GPIO_H) {
397 /* SDC1: PH22-PH-27 */
398 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
399 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
400 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
401 sunxi_gpio_set_drv(pin, 2);
402 }
403 } else {
404 /* SDC1: PG0-PG5 */
405 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
406 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
407 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
408 sunxi_gpio_set_drv(pin, 2);
409 }
410 }
411 #elif defined(CONFIG_MACH_SUN5I)
412 /* SDC1: PG3-PG8 */
413 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
414 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
415 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
416 sunxi_gpio_set_drv(pin, 2);
417 }
418 #elif defined(CONFIG_MACH_SUN6I)
419 /* SDC1: PG0-PG5 */
420 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
421 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
423 sunxi_gpio_set_drv(pin, 2);
424 }
425 #elif defined(CONFIG_MACH_SUN8I)
426 if (pins == SUNXI_GPIO_D) {
427 /* SDC1: PD2-PD7 */
428 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
429 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
430 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
431 sunxi_gpio_set_drv(pin, 2);
432 }
433 } else {
434 /* SDC1: PG0-PG5 */
435 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
436 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(pin, 2);
439 }
440 }
441 #endif
442 break;
443
444 case 2:
445 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
446
447 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
448 /* SDC2: PC6-PC11 */
449 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
450 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
451 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
452 sunxi_gpio_set_drv(pin, 2);
453 }
454 #elif defined(CONFIG_MACH_SUN5I)
455 if (pins == SUNXI_GPIO_E) {
456 /* SDC2: PE4-PE9 */
457 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
458 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
459 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
460 sunxi_gpio_set_drv(pin, 2);
461 }
462 } else {
463 /* SDC2: PC6-PC15 */
464 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
465 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
466 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
467 sunxi_gpio_set_drv(pin, 2);
468 }
469 }
470 #elif defined(CONFIG_MACH_SUN6I)
471 if (pins == SUNXI_GPIO_A) {
472 /* SDC2: PA9-PA14 */
473 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
474 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
475 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
476 sunxi_gpio_set_drv(pin, 2);
477 }
478 } else {
479 /* SDC2: PC6-PC15, PC24 */
480 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
481 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
482 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
483 sunxi_gpio_set_drv(pin, 2);
484 }
485
486 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
487 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
488 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
489 }
490 #elif defined(CONFIG_MACH_SUN8I_R40)
491 /* SDC2: PC6-PC15, PC24 */
492 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
493 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
494 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
495 sunxi_gpio_set_drv(pin, 2);
496 }
497
498 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
499 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
500 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
501 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
502 /* SDC2: PC5-PC6, PC8-PC16 */
503 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
504 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
505 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
506 sunxi_gpio_set_drv(pin, 2);
507 }
508
509 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
510 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
511 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
512 sunxi_gpio_set_drv(pin, 2);
513 }
514 #elif defined(CONFIG_MACH_SUN50I_H6)
515 /* SDC2: PC4-PC14 */
516 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
517 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
518 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
519 sunxi_gpio_set_drv(pin, 2);
520 }
521 #elif defined(CONFIG_MACH_SUN9I)
522 /* SDC2: PC6-PC16 */
523 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
524 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
525 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
526 sunxi_gpio_set_drv(pin, 2);
527 }
528 #endif
529 break;
530
531 case 3:
532 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
533
534 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
535 defined(CONFIG_MACH_SUN8I_R40)
536 /* SDC3: PI4-PI9 */
537 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
538 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
539 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
540 sunxi_gpio_set_drv(pin, 2);
541 }
542 #elif defined(CONFIG_MACH_SUN6I)
543 if (pins == SUNXI_GPIO_A) {
544 /* SDC3: PA9-PA14 */
545 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
546 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
547 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
548 sunxi_gpio_set_drv(pin, 2);
549 }
550 } else {
551 /* SDC3: PC6-PC15, PC24 */
552 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
553 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
554 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
555 sunxi_gpio_set_drv(pin, 2);
556 }
557
558 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
559 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
560 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
561 }
562 #endif
563 break;
564
565 default:
566 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
567 break;
568 }
569 }
570
board_mmc_init(bd_t * bis)571 int board_mmc_init(bd_t *bis)
572 {
573 __maybe_unused struct mmc *mmc0, *mmc1;
574
575 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
576 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
577 if (!mmc0)
578 return -1;
579
580 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
581 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
582 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
583 if (!mmc1)
584 return -1;
585 #endif
586
587 return 0;
588 }
589 #endif
590
591 #ifdef CONFIG_SPL_BUILD
592
sunxi_spl_store_dram_size(phys_addr_t dram_size)593 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
594 {
595 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
596
597 if (spl == INVALID_SPL_HEADER)
598 return;
599
600 /* Promote the header version for U-Boot proper, if needed. */
601 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
602 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
603
604 spl->dram_size = dram_size >> 20;
605 }
606
sunxi_board_init(void)607 void sunxi_board_init(void)
608 {
609 int power_failed = 0;
610
611 #ifdef CONFIG_SY8106A_POWER
612 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
613 #endif
614
615 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
616 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
617 defined CONFIG_AXP818_POWER
618 power_failed = axp_init();
619
620 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
621 defined CONFIG_AXP818_POWER
622 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
623 #endif
624 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
625 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
626 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
627 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
628 #endif
629 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
630 defined CONFIG_AXP818_POWER
631 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
632 #endif
633
634 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
635 defined CONFIG_AXP818_POWER
636 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
637 #endif
638 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
639 #if !defined(CONFIG_AXP152_POWER)
640 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
641 #endif
642 #ifdef CONFIG_AXP209_POWER
643 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
644 #endif
645
646 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
647 defined(CONFIG_AXP818_POWER)
648 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
649 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
650 #if !defined CONFIG_AXP809_POWER
651 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
652 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
653 #endif
654 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
655 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
656 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
657 #endif
658
659 #ifdef CONFIG_AXP818_POWER
660 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
661 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
662 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
663 #endif
664
665 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
666 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
667 #endif
668 #endif
669 printf("DRAM:");
670 gd->ram_size = sunxi_dram_init();
671 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
672 if (!gd->ram_size)
673 hang();
674
675 sunxi_spl_store_dram_size(gd->ram_size);
676
677 /*
678 * Only clock up the CPU to full speed if we are reasonably
679 * assured it's being powered with suitable core voltage
680 */
681 if (!power_failed)
682 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
683 else
684 printf("Failed to set core voltage! Can't set CPU frequency\n");
685 }
686 #endif
687
688 #ifdef CONFIG_USB_GADGET
g_dnl_board_usb_cable_connected(void)689 int g_dnl_board_usb_cable_connected(void)
690 {
691 struct udevice *dev;
692 struct phy phy;
693 int ret;
694
695 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
696 if (ret) {
697 pr_err("%s: Cannot find USB device\n", __func__);
698 return ret;
699 }
700
701 ret = generic_phy_get_by_name(dev, "usb", &phy);
702 if (ret) {
703 pr_err("failed to get %s USB PHY\n", dev->name);
704 return ret;
705 }
706
707 ret = generic_phy_init(&phy);
708 if (ret) {
709 pr_err("failed to init %s USB PHY\n", dev->name);
710 return ret;
711 }
712
713 ret = sun4i_usb_phy_vbus_detect(&phy);
714 if (ret == 1) {
715 pr_err("A charger is plugged into the OTG\n");
716 return -ENODEV;
717 }
718
719 return ret;
720 }
721 #endif
722
723 #ifdef CONFIG_SERIAL_TAG
get_board_serial(struct tag_serialnr * serialnr)724 void get_board_serial(struct tag_serialnr *serialnr)
725 {
726 char *serial_string;
727 unsigned long long serial;
728
729 serial_string = env_get("serial#");
730
731 if (serial_string) {
732 serial = simple_strtoull(serial_string, NULL, 16);
733
734 serialnr->high = (unsigned int) (serial >> 32);
735 serialnr->low = (unsigned int) (serial & 0xffffffff);
736 } else {
737 serialnr->high = 0;
738 serialnr->low = 0;
739 }
740 }
741 #endif
742
743 /*
744 * Check the SPL header for the "sunxi" variant. If found: parse values
745 * that might have been passed by the loader ("fel" utility), and update
746 * the environment accordingly.
747 */
parse_spl_header(const uint32_t spl_addr)748 static void parse_spl_header(const uint32_t spl_addr)
749 {
750 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
751
752 if (spl == INVALID_SPL_HEADER)
753 return;
754
755 if (!spl->fel_script_address)
756 return;
757
758 if (spl->fel_uEnv_length != 0) {
759 /*
760 * data is expected in uEnv.txt compatible format, so "env
761 * import -t" the string(s) at fel_script_address right away.
762 */
763 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
764 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
765 return;
766 }
767 /* otherwise assume .scr format (mkimage-type script) */
768 env_set_hex("fel_scriptaddr", spl->fel_script_address);
769 }
770
771 /*
772 * Note this function gets called multiple times.
773 * It must not make any changes to env variables which already exist.
774 */
setup_environment(const void * fdt)775 static void setup_environment(const void *fdt)
776 {
777 char serial_string[17] = { 0 };
778 unsigned int sid[4];
779 uint8_t mac_addr[6];
780 char ethaddr[16];
781 int i, ret;
782
783 ret = sunxi_get_sid(sid);
784 if (ret == 0 && sid[0] != 0) {
785 /*
786 * The single words 1 - 3 of the SID have quite a few bits
787 * which are the same on many models, so we take a crc32
788 * of all 3 words, to get a more unique value.
789 *
790 * Note we only do this on newer SoCs as we cannot change
791 * the algorithm on older SoCs since those have been using
792 * fixed mac-addresses based on only using word 3 for a
793 * long time and changing a fixed mac-address with an
794 * u-boot update is not good.
795 */
796 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
797 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
798 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
799 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
800 #endif
801
802 /* Ensure the NIC specific bytes of the mac are not all 0 */
803 if ((sid[3] & 0xffffff) == 0)
804 sid[3] |= 0x800000;
805
806 for (i = 0; i < 4; i++) {
807 sprintf(ethaddr, "ethernet%d", i);
808 if (!fdt_get_alias(fdt, ethaddr))
809 continue;
810
811 if (i == 0)
812 strcpy(ethaddr, "ethaddr");
813 else
814 sprintf(ethaddr, "eth%daddr", i);
815
816 if (env_get(ethaddr))
817 continue;
818
819 /* Non OUI / registered MAC address */
820 mac_addr[0] = (i << 4) | 0x02;
821 mac_addr[1] = (sid[0] >> 0) & 0xff;
822 mac_addr[2] = (sid[3] >> 24) & 0xff;
823 mac_addr[3] = (sid[3] >> 16) & 0xff;
824 mac_addr[4] = (sid[3] >> 8) & 0xff;
825 mac_addr[5] = (sid[3] >> 0) & 0xff;
826
827 eth_env_set_enetaddr(ethaddr, mac_addr);
828 }
829
830 if (!env_get("serial#")) {
831 snprintf(serial_string, sizeof(serial_string),
832 "%08x%08x", sid[0], sid[3]);
833
834 env_set("serial#", serial_string);
835 }
836 }
837 }
838
misc_init_r(void)839 int misc_init_r(void)
840 {
841 uint boot;
842
843 env_set("fel_booted", NULL);
844 env_set("fel_scriptaddr", NULL);
845 env_set("mmc_bootdev", NULL);
846
847 boot = sunxi_get_boot_device();
848 /* determine if we are running in FEL mode */
849 if (boot == BOOT_DEVICE_BOARD) {
850 env_set("fel_booted", "1");
851 parse_spl_header(SPL_ADDR);
852 /* or if we booted from MMC, and which one */
853 } else if (boot == BOOT_DEVICE_MMC1) {
854 env_set("mmc_bootdev", "0");
855 } else if (boot == BOOT_DEVICE_MMC2) {
856 env_set("mmc_bootdev", "1");
857 }
858
859 setup_environment(gd->fdt_blob);
860
861 #ifdef CONFIG_USB_ETHER
862 usb_ether_init();
863 #endif
864
865 return 0;
866 }
867
ft_board_setup(void * blob,bd_t * bd)868 int ft_board_setup(void *blob, bd_t *bd)
869 {
870 int __maybe_unused r;
871
872 /*
873 * Call setup_environment again in case the boot fdt has
874 * ethernet aliases the u-boot copy does not have.
875 */
876 setup_environment(blob);
877
878 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
879 r = sunxi_simplefb_setup(blob);
880 if (r)
881 return r;
882 #endif
883 return 0;
884 }
885
886 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)887 int board_fit_config_name_match(const char *name)
888 {
889 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
890 const char *cmp_str = (const char *)spl;
891
892 /* Check if there is a DT name stored in the SPL header and use that. */
893 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
894 cmp_str += spl->dt_name_offset;
895 } else {
896 #ifdef CONFIG_DEFAULT_DEVICE_TREE
897 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
898 #else
899 return 0;
900 #endif
901 };
902
903 #ifdef CONFIG_PINE64_DT_SELECTION
904 /* Differentiate the two Pine64 board DTs by their DRAM size. */
905 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
906 if ((gd->ram_size > 512 * 1024 * 1024))
907 return !strstr(name, "plus");
908 else
909 return !!strstr(name, "plus");
910 } else {
911 return strcmp(name, cmp_str);
912 }
913 #endif
914 return strcmp(name, cmp_str);
915 }
916 #endif
917