1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 */
5
6 #include <common.h>
7 #include <dwmmc.h>
8 #include <malloc.h>
9
10 #include <asm/arcregs.h>
11
12 DECLARE_GLOBAL_DATA_PTR;
13
14 #define ARC_PERIPHERAL_BASE 0xF0000000
15
16 #define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84)
17 #define CGU_ARC_FMEAS_ARC_START BIT(31)
18 #define CGU_ARC_FMEAS_ARC_DONE BIT(30)
19 #define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0)
20 #define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0
21 #define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15
22
23 #define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000)
24
mach_cpu_init(void)25 int mach_cpu_init(void)
26 {
27 int rcnt, fcnt;
28 u32 data;
29
30 /* Start frequency measurement */
31 writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC);
32
33 /* Poll DONE bit */
34 do {
35 data = readl(CGU_ARC_FMEAS_ARC);
36 } while (!(data & CGU_ARC_FMEAS_ARC_DONE));
37
38 /* Amount of reference 100 MHz clocks */
39 rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) &
40 CGU_ARC_FMEAS_ARC_CNT_MASK);
41
42 /* Amount of CPU clocks */
43 fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) &
44 CGU_ARC_FMEAS_ARC_CNT_MASK);
45
46 gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000;
47
48 return 0;
49 }
50
board_early_init_r(void)51 int board_early_init_r(void)
52 {
53 #define EMSDP_PSRAM_BASE 0xf2001000
54 #define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10)
55 #define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14)
56 #define CRE_ENABLE BIT(31)
57 #define CRE_DRIVE_CMD BIT(6)
58
59 #define PSRAM_RCR_DPD BIT(1)
60 #define PSRAM_RCR_PAGE_MODE BIT(7)
61
62 /*
63 * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
64 * thus "<< 1".
65 */
66 #define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
67
68 // Switch PSRAM controller to command mode
69 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
70 // Program Refresh Configuration Register (RCR) for BANK0
71 writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
72 // Switch PSRAM controller back to memory mode
73 writel(0, PSRAM_FLASH_CONFIG_REG_0);
74
75
76 // Switch PSRAM controller to command mode
77 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
78 // Program Refresh Configuration Register (RCR) for BANK1
79 writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
80 // Switch PSRAM controller back to memory mode
81 writel(0, PSRAM_FLASH_CONFIG_REG_1);
82
83 printf("PSRAM initialized.\n");
84
85 return 0;
86 }
87
88 #define CREG_BASE 0xF0001000
89 #define CREG_BOOT (void *)(CREG_BASE + 0x0FF0)
90 #define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0)
91 #define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8)
92
93 /* Bits in CREG_BOOT register */
94 #define CREG_BOOT_WP_BIT BIT(8)
95
reset_cpu(ulong addr)96 void reset_cpu(ulong addr)
97 {
98 writel(1, CREG_IP_SW_RESET);
99 while (1)
100 ; /* loop forever till reset */
101 }
102
do_emsdp_rom(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])103 static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
104 {
105 u32 creg_boot = readl(CREG_BOOT);
106
107 if (!strcmp(argv[1], "unlock"))
108 creg_boot &= ~CREG_BOOT_WP_BIT;
109 else if (!strcmp(argv[1], "lock"))
110 creg_boot |= CREG_BOOT_WP_BIT;
111 else
112 return CMD_RET_USAGE;
113
114 writel(creg_boot, CREG_BOOT);
115
116 return CMD_RET_SUCCESS;
117 }
118
119 cmd_tbl_t cmd_emsdp[] = {
120 U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""),
121 };
122
do_emsdp(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])123 static int do_emsdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
124 {
125 cmd_tbl_t *c;
126
127 c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp));
128
129 /* Strip off leading 'emsdp' command */
130 argc--;
131 argv++;
132
133 if (c == NULL || argc > c->maxargs)
134 return CMD_RET_USAGE;
135
136 return c->cmd(cmdtp, flag, argc, argv);
137 }
138
139 U_BOOT_CMD(
140 emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp,
141 "Synopsys EMSDP specific commands",
142 "rom unlock - Unlock non-volatile memory for writing\n"
143 "emsdp rom lock - Lock non-volatile memory to prevent writing\n"
144 );
145
checkboard(void)146 int checkboard(void)
147 {
148 int version = readl(CREG_IP_VERSION);
149
150 printf("Board: ARC EM Software Development Platform v%d.%d\n",
151 (version >> 16) & 0xff, version & 0xff);
152 return 0;
153 };
154