1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Soeren Moch <smoch@web.de>
4 */
5
6 #include <asm/arch/clock.h>
7 #include <asm/arch/imx-regs.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/mx6-pins.h>
10 #include <linux/errno.h>
11 #include <asm/gpio.h>
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/mach-imx/boot_mode.h>
14 #include <asm/mach-imx/video.h>
15 #include <mmc.h>
16 #include <fsl_esdhc_imx.h>
17 #include <asm/arch/mxc_hdmi.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/io.h>
20 #include <asm/arch/sys_proto.h>
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
24 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
25 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
26
27 static iomux_v3_cfg_t const uart1_pads[] = {
28 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
29 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
30 };
31
32 static iomux_v3_cfg_t const uart2_pads[] = {
33 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
34 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
35 };
36
dram_init(void)37 int dram_init(void)
38 {
39 gd->ram_size = 2048ul * 1024 * 1024;
40 return 0;
41 }
42
setup_iomux_uart(void)43 static void setup_iomux_uart(void)
44 {
45 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
46 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
47 }
48
49 #ifdef CONFIG_FSL_ESDHC_IMX
50 /* set environment device to boot device when booting from SD */
board_mmc_get_env_dev(int devno)51 int board_mmc_get_env_dev(int devno)
52 {
53 return devno - 1;
54 }
55
board_mmc_get_env_part(int devno)56 int board_mmc_get_env_part(int devno)
57 {
58 return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
59 }
60 #endif /* CONFIG_FSL_ESDHC_IMX */
61
62 #ifdef CONFIG_VIDEO_IPUV3
do_enable_hdmi(struct display_info_t const * dev)63 static void do_enable_hdmi(struct display_info_t const *dev)
64 {
65 imx_enable_hdmi_phy();
66 }
67
68 struct display_info_t const displays[] = {{
69 .bus = -1,
70 .addr = 0,
71 .pixfmt = IPU_PIX_FMT_RGB24,
72 .detect = detect_hdmi,
73 .enable = do_enable_hdmi,
74 .mode = {
75 .name = "HDMI",
76 /* 1024x768@60Hz (VESA)*/
77 .refresh = 60,
78 .xres = 1024,
79 .yres = 768,
80 .pixclock = 15384,
81 .left_margin = 160,
82 .right_margin = 24,
83 .upper_margin = 29,
84 .lower_margin = 3,
85 .hsync_len = 136,
86 .vsync_len = 6,
87 .sync = FB_SYNC_EXT,
88 .vmode = FB_VMODE_NONINTERLACED
89 } } };
90 size_t display_count = ARRAY_SIZE(displays);
91
setup_display(void)92 static void setup_display(void)
93 {
94 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
95 int reg;
96 s32 timeout = 100000;
97
98 enable_ipu_clock();
99 imx_setup_hdmi();
100
101 /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
102 reg = readl(&ccm->analog_pll_video);
103 reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
104 writel(reg, &ccm->analog_pll_video);
105
106 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
107 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
108 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
109 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
110 writel(reg, &ccm->analog_pll_video);
111
112 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
113 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
114
115 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
116 writel(reg, &ccm->analog_pll_video);
117
118 while (timeout--)
119 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
120 break;
121 if (timeout < 0)
122 printf("Warning: video pll lock timeout!\n");
123
124 reg = readl(&ccm->analog_pll_video);
125 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
126 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
127 writel(reg, &ccm->analog_pll_video);
128
129 /* gate ipu1_di0_clk */
130 reg = readl(&ccm->CCGR3);
131 reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
132 writel(reg, &ccm->CCGR3);
133
134 /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
135 reg = readl(&ccm->chsccdr);
136 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
137 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
138 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
139 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
140 (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
141 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
142 writel(reg, &ccm->chsccdr);
143
144 /* enable ipu1_di0_clk */
145 reg = readl(&ccm->CCGR3);
146 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
147 writel(reg, &ccm->CCGR3);
148 }
149 #endif /* CONFIG_VIDEO_IPUV3 */
150
board_early_init_f(void)151 int board_early_init_f(void)
152 {
153 setup_iomux_uart();
154 return 0;
155 }
156
157 #ifdef CONFIG_CMD_BMODE
158 static const struct boot_mode board_boot_modes[] = {
159 /* 4 bit bus width */
160 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
161 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
162 /* 8 bit bus width */
163 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
164 {NULL, 0},
165 };
166 #endif
167
board_init(void)168 int board_init(void)
169 {
170 /* address of boot parameters */
171 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
172
173 #ifdef CONFIG_VIDEO_IPUV3
174 setup_display();
175 #endif
176 #ifdef CONFIG_CMD_BMODE
177 add_board_boot_modes(board_boot_modes);
178 #endif
179 return 0;
180 }
181