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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
4  * Copyright (C) 2014 O.S. Systems Software LTDA.
5  *
6  * Author: Fabio Estevam <festevam@gmail.com>
7  */
8 
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/arch/mxc_hdmi.h>
17 #include <asm/mach-imx/video.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/io.h>
20 #include <linux/sizes.h>
21 #include <common.h>
22 #include <miiphy.h>
23 #include <netdev.h>
24 #include <phy.h>
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
29 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
30 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
31 
32 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
33 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
34 
35 #define ETH_PHY_RESET		IMX_GPIO_NR(1, 26)
36 #define LVDS0_EN		IMX_GPIO_NR(2, 8)
37 #define LVDS0_BL_EN		IMX_GPIO_NR(2, 9)
38 
dram_init(void)39 int dram_init(void)
40 {
41 	gd->ram_size = imx_ddr_size();
42 
43 	return 0;
44 }
45 
46 static iomux_v3_cfg_t const uart1_pads[] = {
47 	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
48 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
49 };
50 
setup_iomux_uart(void)51 static void setup_iomux_uart(void)
52 {
53 	SETUP_IOMUX_PADS(uart1_pads);
54 }
55 
56 static iomux_v3_cfg_t const lvds_pads[] = {
57 	/* lvds */
58 	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
59 	IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
60 	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
61 	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
62 	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
63 };
64 
65 static iomux_v3_cfg_t const enet_pads[] = {
66 	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
67 	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
74 		   MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
76 		   MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 	/* AR8035 PHY Reset */
84         IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)),
85 };
86 
setup_iomux_enet(void)87 static void setup_iomux_enet(void)
88 {
89 	SETUP_IOMUX_PADS(enet_pads);
90 
91 	/* Reset AR8031 PHY */
92 	gpio_request(ETH_PHY_RESET, "enet_phy_reset");
93 	gpio_direction_output(ETH_PHY_RESET, 0);
94 	udelay(500);
95 	gpio_set_value(ETH_PHY_RESET, 1);
96 }
97 
98 #if defined(CONFIG_VIDEO_IPUV3)
99 static iomux_v3_cfg_t const ft5x06_wvga_pads[] = {
100 	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
101 	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
102 	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
103 	IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04	| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
104 	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
105 	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
106 	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
107 	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
108 	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
109 	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
110 	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
111 	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
112 	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
113 	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
114 	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
115 	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
116 	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
117 	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
118 	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
119 	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
120 	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
121 	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
122 	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
123 	IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
124 	IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
125 	IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
126 	IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
127 	IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
128 	IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
129 	IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
130 	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
131 };
132 
do_enable_hdmi(struct display_info_t const * dev)133 static void do_enable_hdmi(struct display_info_t const *dev)
134 {
135 	imx_enable_hdmi_phy();
136 }
137 
enable_lvds(struct display_info_t const * dev)138 static void enable_lvds(struct display_info_t const *dev)
139 {
140 	struct iomuxc *iomux = (struct iomuxc *)
141 				IOMUXC_BASE_ADDR;
142 
143 	/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
144 	u32 reg = readl(&iomux->gpr[2]);
145 	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
146 	writel(reg, &iomux->gpr[2]);
147 
148 	/* Enable Backlight - use GPIO for Brightness adjustment */
149 	SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
150 	gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable");
151 	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
152 
153 	gpio_request(IMX_GPIO_NR(2, 8), "brightness");
154 	SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
155 	gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
156 }
157 
enable_ft5x06_wvga(struct display_info_t const * dev)158 static void enable_ft5x06_wvga(struct display_info_t const *dev)
159 {
160 	SETUP_IOMUX_PADS(ft5x06_wvga_pads);
161 
162 	gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable");
163 	gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness");
164 	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
165 	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
166 }
167 
168 struct display_info_t const displays[] = {{
169 	.bus	= 1,
170 	.addr	= 0x38,
171 	.pixfmt	= IPU_PIX_FMT_RGB24,
172 	.detect	= NULL,
173 	.enable	= enable_ft5x06_wvga,
174 	.mode	= {
175 		.name           = "FT5x06-WVGA",
176 		.refresh        = 60,
177 		.xres           = 800,
178 		.yres           = 480,
179 		.pixclock       = 30303,
180 		.left_margin    = 45,
181 		.right_margin   = 210,
182 		.upper_margin   = 22,
183 		.lower_margin   = 22,
184 		.hsync_len      = 1,
185 		.vsync_len      = 1,
186 		.sync           = 0,
187 		.vmode          = FB_VMODE_NONINTERLACED
188 } }, {
189 	.bus	= -1,
190 	.addr	= 0,
191 	.pixfmt = IPU_PIX_FMT_RGB24,
192 	.detect = NULL,
193 	.enable = enable_lvds,
194 	.mode	= {
195 		.name		= "hj070na",
196 		.refresh	= 60,
197 		.xres		= 1024,
198 		.yres		= 600,
199 		.pixclock	= 15385,
200 		.left_margin	= 220,
201 		.right_margin	= 40,
202 		.upper_margin	= 21,
203 		.lower_margin	= 7,
204 		.hsync_len	= 60,
205 		.vsync_len	= 10,
206 		.sync		= FB_SYNC_EXT,
207 		.vmode		= FB_VMODE_NONINTERLACED
208 } }, {
209 	.bus	= -1,
210 	.addr	= 0,
211 	.pixfmt	= IPU_PIX_FMT_RGB24,
212 	.detect	= detect_hdmi,
213 	.enable	= do_enable_hdmi,
214 	.mode	= {
215 		.name           = "HDMI",
216 		.refresh        = 60,
217 		.xres           = 1024,
218 		.yres           = 768,
219 		.pixclock       = 15385,
220 		.left_margin    = 220,
221 		.right_margin   = 40,
222 		.upper_margin   = 21,
223 		.lower_margin   = 7,
224 		.hsync_len      = 60,
225 		.vsync_len      = 10,
226 		.sync           = FB_SYNC_EXT,
227 		.vmode          = FB_VMODE_NONINTERLACED
228 } } };
229 size_t display_count = ARRAY_SIZE(displays);
230 
setup_display(void)231 static void setup_display(void)
232 {
233 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
234 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
235 	int reg;
236 
237 	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
238 	SETUP_IOMUX_PADS(lvds_pads);
239 	gpio_request(LVDS0_EN, "lvds0_enable");
240 	gpio_request(LVDS0_BL_EN, "lvds0_bl_enable");
241 	gpio_direction_output(LVDS0_EN, 1);
242 	gpio_direction_output(LVDS0_BL_EN, 1);
243 
244 	enable_ipu_clock();
245 	imx_setup_hdmi();
246 
247 	reg = __raw_readl(&mxc_ccm->CCGR3);
248 	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
249 	writel(reg, &mxc_ccm->CCGR3);
250 
251 	/* set LDB0, LDB1 clk select to 011/011 */
252 	reg = readl(&mxc_ccm->cs2cdr);
253 	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
254 		| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
255 	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
256 		 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
257 	writel(reg, &mxc_ccm->cs2cdr);
258 
259 	reg = readl(&mxc_ccm->cscmr2);
260 	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
261 	writel(reg, &mxc_ccm->cscmr2);
262 
263 	reg = readl(&mxc_ccm->chsccdr);
264 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
265 		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
266 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
267 		<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
268 	writel(reg, &mxc_ccm->chsccdr);
269 
270 	 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
271 		| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
272 		| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
273 		| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
274 		| IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
275 		| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
276 		| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
277 		| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
278 		| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
279 	writel(reg, &iomux->gpr[2]);
280 	reg = readl(&iomux->gpr[3]);
281 
282 	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
283 		| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
284 		| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
285 		<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
286 
287 	writel(reg, &iomux->gpr[3]);
288 }
289 #endif /* CONFIG_VIDEO_IPUV3 */
290 
board_early_init_f(void)291 int board_early_init_f(void)
292 {
293 	setup_iomux_uart();
294 
295 #if defined(CONFIG_VIDEO_IPUV3)
296 	setup_display();
297 #endif
298 
299 	return 0;
300 }
301 
board_eth_init(bd_t * bis)302 int board_eth_init(bd_t *bis)
303 {
304 	setup_iomux_enet();
305 
306 	return cpu_eth_init(bis);
307 }
308 
board_phy_config(struct phy_device * phydev)309 int board_phy_config(struct phy_device *phydev)
310 {
311 	unsigned short val;
312 
313 	/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
314 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
315 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
316 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
317 
318 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
319 	val &= 0xffe7;
320 	val |= 0x18;
321 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
322 
323 	/* introduce tx clock delay */
324 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
325 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
326 	val |= 0x0100;
327 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
328 
329 	if (phydev->drv->config)
330 		phydev->drv->config(phydev);
331 
332 	return 0;
333 }
334 
overwrite_console(void)335 int overwrite_console(void)
336 {
337 	return 1;
338 }
339 
board_late_init(void)340 int board_late_init(void)
341 {
342 	if (is_mx6dq())
343 		env_set("board_rev", "MX6Q");
344 	else
345 		env_set("board_rev", "MX6DL");
346 
347 	return 0;
348 }
349 
board_init(void)350 int board_init(void)
351 {
352 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
353 
354 	return 0;
355 }
356 
checkboard(void)357 int checkboard(void)
358 {
359 	puts("Board: PICO-IMX6\n");
360 
361 	return 0;
362 }
363