1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Technexion Ltd.
4 *
5 * Author: Richard Hu <richard.hu@technexion.com>
6 */
7
8 #include <asm/arch/clock.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/io.h>
17 #include <common.h>
18 #include <miiphy.h>
19 #include <netdev.h>
20 #include <linux/sizes.h>
21 #include <usb.h>
22 #include <power/pmic.h>
23 #include <power/pfuze3000_pmic.h>
24 #include "../../freescale/common/pfuze.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
29 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
30 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
31
32 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
34 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35
36 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
37 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
38
39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
40 PAD_CTL_SPEED_HIGH | \
41 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
42
43 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
44
45 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
46 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
47
48 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
49
50 static iomux_v3_cfg_t const fec_pads[] = {
51 MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
52 MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
53 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
54 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
55 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
56 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
57 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
58 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
59 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
62 };
63
setup_iomux_fec(void)64 static void setup_iomux_fec(void)
65 {
66 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
67 }
68
board_eth_init(bd_t * bis)69 int board_eth_init(bd_t *bis)
70 {
71 setup_iomux_fec();
72
73 gpio_request(RMII_PHY_RESET, "enet_phy_reset");
74 gpio_direction_output(RMII_PHY_RESET, 0);
75 /*
76 * According to KSZ8081MNX-RNB manual:
77 * For warm reset, the reset (RST#) pin should be asserted low for a
78 * minimum of 500μs. The strap-in pin values are read and updated
79 * at the de-assertion of reset.
80 */
81 udelay(500);
82
83 gpio_direction_output(RMII_PHY_RESET, 1);
84 /*
85 * According to KSZ8081MNX-RNB manual:
86 * After the de-assertion of reset, wait a minimum of 100μs before
87 * starting programming on the MIIM (MDC/MDIO) interface.
88 */
89 udelay(100);
90
91 return fecmxc_initialize(bis);
92 }
93
setup_fec(void)94 static int setup_fec(void)
95 {
96 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
97 int ret;
98
99 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
100 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
101
102 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
103 if (ret)
104 return ret;
105
106 enable_enet_clk(1);
107
108 return 0;
109 }
110
111 #ifdef CONFIG_VIDEO_MXS
112 static iomux_v3_cfg_t const lcd_pads[] = {
113 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
114 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
115 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
116 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
117 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
118 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
119 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
120 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
121 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
122 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
123 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
124 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
125 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
126 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
127 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
128 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
129 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
130 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
131 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
132 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
133 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
134 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
135 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
136 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
137 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
138 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
139 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
140 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
141 /* LCD_BLT_CTRL: GPIO for Brightness adjustment */
142 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
143 /* LCD_VDD_EN: LCD enabled */
144 MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
145 };
146
setup_lcd(void)147 void setup_lcd(void)
148 {
149 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
150 gpio_request(IMX_GPIO_NR(4, 10), "lcd_brightness");
151 gpio_request(IMX_GPIO_NR(1, 11), "lcd_enable");
152 /* Set Brightness to high */
153 gpio_direction_output(IMX_GPIO_NR(4, 10) , 1);
154 /* Set LCD enable to high */
155 gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
156 }
157 #endif
158
board_phy_config(struct phy_device * phydev)159 int board_phy_config(struct phy_device *phydev)
160 {
161 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
162
163 if (phydev->drv->config)
164 phydev->drv->config(phydev);
165
166 return 0;
167 }
168
dram_init(void)169 int dram_init(void)
170 {
171 gd->ram_size = imx_ddr_size();
172
173 return 0;
174 }
175
176 static iomux_v3_cfg_t const uart6_pads[] = {
177 MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
178 MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
179 };
180
181 #define USB_OTHERREGS_OFFSET 0x800
182 #define UCTRL_PWR_POL (1 << 9)
183
184 static iomux_v3_cfg_t const usb_otg_pad[] = {
185 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
186 };
187
setup_iomux_uart(void)188 static void setup_iomux_uart(void)
189 {
190 imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
191 }
192
setup_usb(void)193 static void setup_usb(void)
194 {
195 imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
196 }
197
board_early_init_f(void)198 int board_early_init_f(void)
199 {
200 setup_iomux_uart();
201
202 return 0;
203 }
204
205 #ifdef CONFIG_DM_PMIC
power_init_board(void)206 int power_init_board(void)
207 {
208 struct udevice *dev;
209 int ret, dev_id, rev_id;
210
211 ret = pmic_get("pfuze3000", &dev);
212 if (ret == -ENODEV)
213 return 0;
214 if (ret != 0)
215 return ret;
216
217 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
218 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
219 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
220
221 /* disable Low Power Mode during standby mode */
222 pmic_reg_write(dev, PFUZE3000_LDOGCTL, 0x1);
223
224 /* SW1B step ramp up time from 2us to 4us/25mV */
225 pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
226
227 /* SW1B mode to APS/PFM */
228 pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
229
230 /* SW1B standby voltage set to 0.975V */
231 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
232
233 return 0;
234 }
235 #endif
236
board_usb_phy_mode(int port)237 int board_usb_phy_mode(int port)
238 {
239 if (port == 1)
240 return USB_INIT_HOST;
241 else
242 return USB_INIT_DEVICE;
243 }
244
board_ehci_hcd_init(int port)245 int board_ehci_hcd_init(int port)
246 {
247 u32 *usbnc_usb_ctrl;
248
249 if (port > 1)
250 return -EINVAL;
251
252 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
253 port * 4);
254
255 /* Set Power polarity */
256 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
257
258 return 0;
259 }
260
board_init(void)261 int board_init(void)
262 {
263 /* Address of boot parameters */
264 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
265
266 setup_fec();
267 setup_usb();
268 #ifdef CONFIG_VIDEO_MXS
269 setup_lcd();
270 #endif
271 return 0;
272 }
273
checkboard(void)274 int checkboard(void)
275 {
276 puts("Board: PICO-IMX6UL-EMMC\n");
277
278 return 0;
279 }
280