1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7 #include <common.h>
8 #include <fdtdec.h>
9 #include <init.h>
10 #include <malloc.h>
11 #include <time.h>
12 #include <asm/io.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sys_proto.h>
15 #include <dm/device.h>
16 #include <dm/uclass.h>
17 #include <versalpl.h>
18 #include <linux/sizes.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 #if defined(CONFIG_FPGA_VERSALPL)
23 static xilinx_desc versalpl = XILINX_VERSAL_DESC;
24 #endif
25
board_init(void)26 int board_init(void)
27 {
28 printf("EL Level:\tEL%d\n", current_el());
29
30 #if defined(CONFIG_FPGA_VERSALPL)
31 fpga_init();
32 fpga_add(fpga_xilinx, &versalpl);
33 #endif
34
35 return 0;
36 }
37
board_early_init_r(void)38 int board_early_init_r(void)
39 {
40 u32 val;
41
42 if (current_el() != 3)
43 return 0;
44
45 debug("iou_switch ctrl div0 %x\n",
46 readl(&crlapb_base->iou_switch_ctrl));
47
48 writel(IOU_SWITCH_CTRL_CLKACT_BIT |
49 (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
50 &crlapb_base->iou_switch_ctrl);
51
52 /* Global timer init - Program time stamp reference clk */
53 val = readl(&crlapb_base->timestamp_ref_ctrl);
54 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
55 writel(val, &crlapb_base->timestamp_ref_ctrl);
56
57 debug("ref ctrl 0x%x\n",
58 readl(&crlapb_base->timestamp_ref_ctrl));
59
60 /* Clear reset of timestamp reg */
61 writel(0, &crlapb_base->rst_timestamp);
62
63 /*
64 * Program freq register in System counter and
65 * enable system counter.
66 */
67 writel(COUNTER_FREQUENCY,
68 &iou_scntr_secure->base_frequency_id_register);
69
70 debug("counter val 0x%x\n",
71 readl(&iou_scntr_secure->base_frequency_id_register));
72
73 writel(IOU_SCNTRS_CONTROL_EN,
74 &iou_scntr_secure->counter_control_register);
75
76 debug("scntrs control 0x%x\n",
77 readl(&iou_scntr_secure->counter_control_register));
78 debug("timer 0x%llx\n", get_ticks());
79 debug("timer 0x%llx\n", get_ticks());
80
81 return 0;
82 }
83
board_late_init(void)84 int board_late_init(void)
85 {
86 u32 reg = 0;
87 u8 bootmode;
88 struct udevice *dev;
89 int bootseq = -1;
90 int bootseq_len = 0;
91 int env_targets_len = 0;
92 const char *mode;
93 char *new_targets;
94 char *env_targets;
95 ulong initrd_hi;
96
97 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
98 debug("Saved variables - Skipping\n");
99 return 0;
100 }
101
102 reg = readl(&crp_base->boot_mode_usr);
103
104 if (reg >> BOOT_MODE_ALT_SHIFT)
105 reg >>= BOOT_MODE_ALT_SHIFT;
106
107 bootmode = reg & BOOT_MODES_MASK;
108
109 puts("Bootmode: ");
110 switch (bootmode) {
111 case USB_MODE:
112 puts("USB_MODE\n");
113 mode = "dfu_usb";
114 break;
115 case JTAG_MODE:
116 puts("JTAG_MODE\n");
117 mode = "jtag pxe dhcp";
118 break;
119 case QSPI_MODE_24BIT:
120 puts("QSPI_MODE_24\n");
121 mode = "xspi0";
122 break;
123 case QSPI_MODE_32BIT:
124 puts("QSPI_MODE_32\n");
125 mode = "xspi0";
126 break;
127 case OSPI_MODE:
128 puts("OSPI_MODE\n");
129 mode = "xspi0";
130 break;
131 case EMMC_MODE:
132 puts("EMMC_MODE\n");
133 mode = "mmc0";
134 break;
135 case SD_MODE:
136 puts("SD_MODE\n");
137 if (uclass_get_device_by_name(UCLASS_MMC,
138 "sdhci@f1040000", &dev)) {
139 puts("Boot from SD0 but without SD0 enabled!\n");
140 return -1;
141 }
142 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
143
144 mode = "mmc";
145 bootseq = dev->seq;
146 break;
147 case SD1_LSHFT_MODE:
148 puts("LVL_SHFT_");
149 /* fall through */
150 case SD_MODE1:
151 puts("SD_MODE1\n");
152 if (uclass_get_device_by_name(UCLASS_MMC,
153 "sdhci@f1050000", &dev)) {
154 puts("Boot from SD1 but without SD1 enabled!\n");
155 return -1;
156 }
157 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
158
159 mode = "mmc";
160 bootseq = dev->seq;
161 break;
162 default:
163 mode = "";
164 printf("Invalid Boot Mode:0x%x\n", bootmode);
165 break;
166 }
167
168 if (bootseq >= 0) {
169 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
170 debug("Bootseq len: %x\n", bootseq_len);
171 }
172
173 /*
174 * One terminating char + one byte for space between mode
175 * and default boot_targets
176 */
177 env_targets = env_get("boot_targets");
178 if (env_targets)
179 env_targets_len = strlen(env_targets);
180
181 new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
182 bootseq_len);
183 if (!new_targets)
184 return -ENOMEM;
185
186 if (bootseq >= 0)
187 sprintf(new_targets, "%s%x %s", mode, bootseq,
188 env_targets ? env_targets : "");
189 else
190 sprintf(new_targets, "%s %s", mode,
191 env_targets ? env_targets : "");
192
193 env_set("boot_targets", new_targets);
194
195 initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
196 initrd_hi = round_down(initrd_hi, SZ_16M);
197 env_set_addr("initrd_high", (void *)initrd_hi);
198
199 return 0;
200 }
201
dram_init_banksize(void)202 int dram_init_banksize(void)
203 {
204 int ret;
205
206 ret = fdtdec_setup_memory_banksize();
207 if (ret)
208 return ret;
209
210 mem_map_fill();
211
212 return 0;
213 }
214
dram_init(void)215 int dram_init(void)
216 {
217 if (fdtdec_setup_mem_size_base() != 0)
218 return -EINVAL;
219
220 return 0;
221 }
222
reset_cpu(ulong addr)223 void reset_cpu(ulong addr)
224 {
225 }
226