1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Copyright 2019 NXP
5 * Author: Tang Yuantian <b29983@freescale.com>
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <pci.h>
11 #include <command.h>
12 #include <asm/byteorder.h>
13 #include <malloc.h>
14 #include <asm/io.h>
15 #include <fis.h>
16 #include <sata.h>
17 #include <libata.h>
18 #include <sata.h>
19
20 #if CONFIG_IS_ENABLED(BLK)
21 #include <dm.h>
22 #include <blk.h>
23 #endif
24
25 #include "sata_sil.h"
26
27 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
28
29 /* just compatible ahci_ops */
30 struct sil_ops {
31 int *rev0;
32 int *rev1;
33 int (*scan)(struct udevice *dev);
34 };
35
36 static struct sata_info sata_info;
37
38 static struct pci_device_id supported[] = {
39 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
40 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
41 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
42 {}
43 };
44
sil_sata_dump_fis(struct sata_fis_d2h * s)45 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
46 {
47 printf("Status FIS dump:\n");
48 printf("fis_type: %02x\n", s->fis_type);
49 printf("pm_port_i: %02x\n", s->pm_port_i);
50 printf("status: %02x\n", s->status);
51 printf("error: %02x\n", s->error);
52 printf("lba_low: %02x\n", s->lba_low);
53 printf("lba_mid: %02x\n", s->lba_mid);
54 printf("lba_high: %02x\n", s->lba_high);
55 printf("device: %02x\n", s->device);
56 printf("lba_low_exp: %02x\n", s->lba_low_exp);
57 printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
58 printf("lba_high_exp: %02x\n", s->lba_high_exp);
59 printf("res1: %02x\n", s->res1);
60 printf("sector_count: %02x\n", s->sector_count);
61 printf("sector_count_exp: %02x\n", s->sector_count_exp);
62 }
63
sata_spd_string(unsigned int speed)64 static const char *sata_spd_string(unsigned int speed)
65 {
66 static const char * const spd_str[] = {
67 "1.5 Gbps",
68 "3.0 Gbps",
69 "6.0 Gbps",
70 };
71
72 if ((speed - 1) > 2)
73 return "<unknown>";
74
75 return spd_str[speed - 1];
76 }
77
ata_wait_register(void * reg,u32 mask,u32 val,int timeout_msec)78 static u32 ata_wait_register(void *reg, u32 mask,
79 u32 val, int timeout_msec)
80 {
81 u32 tmp;
82
83 tmp = readl(reg);
84 while ((tmp & mask) == val && timeout_msec > 0) {
85 mdelay(1);
86 timeout_msec--;
87 tmp = readl(reg);
88 }
89
90 return tmp;
91 }
92
sil_config_port(void * port)93 static void sil_config_port(void *port)
94 {
95 /* configure IRQ WoC */
96 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
97
98 /* zero error counters. */
99 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
100 writew(0x8000, port + PORT_CRC_ERR_THRESH);
101 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
102 writew(0x0000, port + PORT_DECODE_ERR_CNT);
103 writew(0x0000, port + PORT_CRC_ERR_CNT);
104 writew(0x0000, port + PORT_HSHK_ERR_CNT);
105
106 /* always use 64bit activation */
107 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
108
109 /* clear port multiplier enable and resume bits */
110 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
111 }
112
sil_init_port(void * port)113 static int sil_init_port(void *port)
114 {
115 u32 tmp;
116
117 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
118 ata_wait_register(port + PORT_CTRL_STAT,
119 PORT_CS_INIT, PORT_CS_INIT, 100);
120 tmp = ata_wait_register(port + PORT_CTRL_STAT,
121 PORT_CS_RDY, 0, 100);
122
123 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
124 return 1;
125
126 return 0;
127 }
128
sil_read_fis(struct sil_sata * sata,int tag,struct sata_fis_d2h * fis)129 static void sil_read_fis(struct sil_sata *sata, int tag,
130 struct sata_fis_d2h *fis)
131 {
132 void *port = sata->port;
133 struct sil_prb *prb;
134 int i;
135 u32 *src, *dst;
136
137 prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
138 src = (u32 *)&prb->fis;
139 dst = (u32 *)fis;
140 for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
141 *dst++ = readl(src++);
142 }
143
sil_exec_cmd(struct sil_sata * sata,struct sil_cmd_block * pcmd,int tag)144 static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
145 int tag)
146 {
147 void *port = sata->port;
148 u64 paddr = virt_to_bus(sata->devno, pcmd);
149 u32 irq_mask, irq_stat;
150 int rc;
151
152 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
153
154 /* better to add momery barrior here */
155 writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
156 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
157
158 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
159 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
160 0, 10000);
161
162 /* clear IRQs */
163 writel(irq_mask, port + PORT_IRQ_STAT);
164 irq_stat >>= PORT_IRQ_RAW_SHIFT;
165
166 if (irq_stat & PORT_IRQ_COMPLETE)
167 rc = 0;
168 else {
169 /* force port into known state */
170 sil_init_port(port);
171 if (irq_stat & PORT_IRQ_ERROR)
172 rc = 1; /* error */
173 else
174 rc = 2; /* busy */
175 }
176
177 return rc;
178 }
179
sil_cmd_set_feature(struct sil_sata * sata)180 static int sil_cmd_set_feature(struct sil_sata *sata)
181 {
182 struct sil_cmd_block cmdb, *pcmd = &cmdb;
183 struct sata_fis_d2h fis;
184 u8 udma_cap;
185 int ret;
186
187 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
188 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
189 pcmd->prb.fis.pm_port_c = (1 << 7);
190 pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
191 pcmd->prb.fis.features = SETFEATURES_XFER;
192
193 /* First check the device capablity */
194 udma_cap = (u8)(sata->udma & 0xff);
195 debug("udma_cap %02x\n", udma_cap);
196
197 if (udma_cap == ATA_UDMA6)
198 pcmd->prb.fis.sector_count = XFER_UDMA_6;
199 if (udma_cap == ATA_UDMA5)
200 pcmd->prb.fis.sector_count = XFER_UDMA_5;
201 if (udma_cap == ATA_UDMA4)
202 pcmd->prb.fis.sector_count = XFER_UDMA_4;
203 if (udma_cap == ATA_UDMA3)
204 pcmd->prb.fis.sector_count = XFER_UDMA_3;
205
206 ret = sil_exec_cmd(sata, pcmd, 0);
207 if (ret) {
208 sil_read_fis(sata, 0, &fis);
209 printf("Err: exe cmd(0x%x).\n",
210 readl(sata->port + PORT_SERROR));
211 sil_sata_dump_fis(&fis);
212 return 1;
213 }
214
215 return 0;
216 }
217
sil_sata_init_wcache(struct sil_sata * sata,u16 * id)218 static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
219 {
220 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
221 sata->wcache = 1;
222 if (ata_id_has_flush(id))
223 sata->flush = 1;
224 if (ata_id_has_flush_ext(id))
225 sata->flush_ext = 1;
226 }
227
sil_sata_set_feature_by_id(struct sil_sata * sata,u16 * id)228 static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
229 {
230 #ifdef CONFIG_LBA48
231 /* Check if support LBA48 */
232 if (ata_id_has_lba48(id)) {
233 sata->lba48 = 1;
234 debug("Device supports LBA48\n");
235 } else {
236 debug("Device supports LBA28\n");
237 }
238 #endif
239
240 sil_sata_init_wcache(sata, id);
241 sil_cmd_set_feature(sata);
242 }
243
sil_cmd_identify_device(struct sil_sata * sata,u16 * id)244 static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
245 {
246 struct sil_cmd_block cmdb, *pcmd = &cmdb;
247 struct sata_fis_d2h fis;
248 int ret;
249
250 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
251 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
252 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
253 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
254 pcmd->prb.fis.pm_port_c = (1 << 7);
255 pcmd->prb.fis.command = ATA_CMD_ID_ATA;
256 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
257 pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
258 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
259
260 ret = sil_exec_cmd(sata, pcmd, 0);
261 if (ret) {
262 sil_read_fis(sata, 0, &fis);
263 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
264 sil_sata_dump_fis(&fis);
265 return 1;
266 }
267 ata_swap_buf_le16(id, ATA_ID_WORDS);
268
269 return 0;
270 }
271
sil_cmd_soft_reset(struct sil_sata * sata)272 static int sil_cmd_soft_reset(struct sil_sata *sata)
273 {
274 struct sil_cmd_block cmdb, *pcmd = &cmdb;
275 struct sata_fis_d2h fis;
276 void *port = sata->port;
277 int ret;
278
279 /* put the port into known state */
280 if (sil_init_port(port)) {
281 printf("SRST: port %d not ready\n", sata->id);
282 return 1;
283 }
284
285 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
286
287 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
288 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
289 pcmd->prb.fis.pm_port_c = 0xf;
290
291 ret = sil_exec_cmd(sata, &cmdb, 0);
292 if (ret) {
293 sil_read_fis(sata, 0, &fis);
294 printf("SRST cmd error.\n");
295 sil_sata_dump_fis(&fis);
296 return 1;
297 }
298
299 return 0;
300 }
301
sil_sata_rw_cmd(struct sil_sata * sata,ulong start,ulong blkcnt,u8 * buffer,int is_write)302 static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
303 u8 *buffer, int is_write)
304 {
305 struct sil_cmd_block cmdb, *pcmd = &cmdb;
306 struct sata_fis_d2h fis;
307 u64 block;
308 int ret;
309
310 block = (u64)start;
311 memset(pcmd, 0, sizeof(struct sil_cmd_block));
312 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
313 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
314 pcmd->prb.fis.pm_port_c = (1 << 7);
315 if (is_write) {
316 pcmd->prb.fis.command = ATA_CMD_WRITE;
317 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
318 } else {
319 pcmd->prb.fis.command = ATA_CMD_READ;
320 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
321 }
322
323 pcmd->prb.fis.device = ATA_LBA;
324 pcmd->prb.fis.device |= (block >> 24) & 0xf;
325 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
326 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
327 pcmd->prb.fis.lba_low = block & 0xff;
328 pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
329
330 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
331 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
332 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
333
334 ret = sil_exec_cmd(sata, pcmd, 0);
335 if (ret) {
336 sil_read_fis(sata, 0, &fis);
337 printf("Err: rw cmd(0x%08x).\n",
338 readl(sata->port + PORT_SERROR));
339 sil_sata_dump_fis(&fis);
340 return 1;
341 }
342
343 return blkcnt;
344 }
345
sil_sata_rw_cmd_ext(struct sil_sata * sata,ulong start,ulong blkcnt,u8 * buffer,int is_write)346 static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
347 ulong blkcnt, u8 *buffer, int is_write)
348 {
349 struct sil_cmd_block cmdb, *pcmd = &cmdb;
350 struct sata_fis_d2h fis;
351 u64 block;
352 int ret;
353
354 block = (u64)start;
355 memset(pcmd, 0, sizeof(struct sil_cmd_block));
356 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
357 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
358 pcmd->prb.fis.pm_port_c = (1 << 7);
359 if (is_write) {
360 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
361 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
362 } else {
363 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
364 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
365 }
366
367 pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
368 pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
369 pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
370 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
371 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
372 pcmd->prb.fis.lba_low = block & 0xff;
373 pcmd->prb.fis.device = ATA_LBA;
374 pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
375 pcmd->prb.fis.sector_count = blkcnt & 0xff;
376
377 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
378 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
379 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
380
381 ret = sil_exec_cmd(sata, pcmd, 0);
382 if (ret) {
383 sil_read_fis(sata, 0, &fis);
384 printf("Err: rw ext cmd(0x%08x).\n",
385 readl(sata->port + PORT_SERROR));
386 sil_sata_dump_fis(&fis);
387 return 1;
388 }
389
390 return blkcnt;
391 }
392
sil_sata_rw_lba28(struct sil_sata * sata,ulong blknr,lbaint_t blkcnt,const void * buffer,int is_write)393 static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
394 lbaint_t blkcnt, const void *buffer,
395 int is_write)
396 {
397 ulong start, blks, max_blks;
398 u8 *addr;
399
400 start = blknr;
401 blks = blkcnt;
402 addr = (u8 *)buffer;
403
404 max_blks = ATA_MAX_SECTORS;
405 do {
406 if (blks > max_blks) {
407 sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
408 start += max_blks;
409 blks -= max_blks;
410 addr += ATA_SECT_SIZE * max_blks;
411 } else {
412 sil_sata_rw_cmd(sata, start, blks, addr, is_write);
413 start += blks;
414 blks = 0;
415 addr += ATA_SECT_SIZE * blks;
416 }
417 } while (blks != 0);
418
419 return blkcnt;
420 }
421
sil_sata_rw_lba48(struct sil_sata * sata,ulong blknr,lbaint_t blkcnt,const void * buffer,int is_write)422 static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
423 lbaint_t blkcnt, const void *buffer,
424 int is_write)
425 {
426 ulong start, blks, max_blks;
427 u8 *addr;
428
429 start = blknr;
430 blks = blkcnt;
431 addr = (u8 *)buffer;
432
433 max_blks = ATA_MAX_SECTORS_LBA48;
434 do {
435 if (blks > max_blks) {
436 sil_sata_rw_cmd_ext(sata, start, max_blks,
437 addr, is_write);
438 start += max_blks;
439 blks -= max_blks;
440 addr += ATA_SECT_SIZE * max_blks;
441 } else {
442 sil_sata_rw_cmd_ext(sata, start, blks,
443 addr, is_write);
444 start += blks;
445 blks = 0;
446 addr += ATA_SECT_SIZE * blks;
447 }
448 } while (blks != 0);
449
450 return blkcnt;
451 }
452
sil_sata_cmd_flush_cache(struct sil_sata * sata)453 static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
454 {
455 struct sil_cmd_block cmdb, *pcmd = &cmdb;
456
457 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
458 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
459 pcmd->prb.fis.pm_port_c = (1 << 7);
460 pcmd->prb.fis.command = ATA_CMD_FLUSH;
461
462 sil_exec_cmd(sata, pcmd, 0);
463 }
464
sil_sata_cmd_flush_cache_ext(struct sil_sata * sata)465 static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
466 {
467 struct sil_cmd_block cmdb, *pcmd = &cmdb;
468
469 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
470 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
471 pcmd->prb.fis.pm_port_c = (1 << 7);
472 pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
473
474 sil_exec_cmd(sata, pcmd, 0);
475 }
476
477 /*
478 * SATA interface between low level driver and command layer
479 */
480 #if !CONFIG_IS_ENABLED(BLK)
sata_read(int dev,ulong blknr,lbaint_t blkcnt,void * buffer)481 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
482 {
483 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
484 #else
485 static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
486 void *buffer)
487 {
488 struct sil_sata_priv *priv = dev_get_platdata(dev);
489 int port_number = priv->port_num;
490 struct sil_sata *sata = priv->sil_sata_desc[port_number];
491 #endif
492 ulong rc;
493
494 if (sata->lba48)
495 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
496 else
497 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
498
499 return rc;
500 }
501
502 /*
503 * SATA interface between low level driver and command layer
504 */
505 #if !CONFIG_IS_ENABLED(BLK)
506 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
507 {
508 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
509 #else
510 ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
511 const void *buffer)
512 {
513 struct sil_sata_priv *priv = dev_get_platdata(dev);
514 int port_number = priv->port_num;
515 struct sil_sata *sata = priv->sil_sata_desc[port_number];
516 #endif
517 ulong rc;
518
519 if (sata->lba48) {
520 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
521 if (sata->wcache && sata->flush_ext)
522 sil_sata_cmd_flush_cache_ext(sata);
523 } else {
524 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
525 if (sata->wcache && sata->flush)
526 sil_sata_cmd_flush_cache(sata);
527 }
528
529 return rc;
530 }
531
532 #if !CONFIG_IS_ENABLED(BLK)
533 static int sil_init_sata(int dev)
534 {
535 #else
536 static int sil_init_sata(struct udevice *uc_dev, int dev)
537 {
538 struct sil_sata_priv *priv = dev_get_platdata(uc_dev);
539 #endif
540 struct sil_sata *sata;
541 void *port;
542 u32 tmp;
543 int cnt;
544
545 printf("SATA#%d:\n", dev);
546
547 port = (void *)sata_info.iobase[1] +
548 PORT_REGS_SIZE * (dev - sata_info.portbase);
549
550 /* Initial PHY setting */
551 writel(0x20c, port + PORT_PHY_CFG);
552
553 /* clear port RST */
554 tmp = readl(port + PORT_CTRL_STAT);
555 if (tmp & PORT_CS_PORT_RST) {
556 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
557 tmp = ata_wait_register(port + PORT_CTRL_STAT,
558 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
559 if (tmp & PORT_CS_PORT_RST)
560 printf("Err: Failed to clear port RST\n");
561 }
562
563 /* Check if device is present */
564 for (cnt = 0; cnt < 100; cnt++) {
565 tmp = readl(port + PORT_SSTATUS);
566 if ((tmp & 0xF) == 0x3)
567 break;
568 mdelay(1);
569 }
570
571 tmp = readl(port + PORT_SSTATUS);
572 if ((tmp & 0xf) != 0x3) {
573 printf(" (No RDY)\n");
574 return 1;
575 }
576
577 /* Wait for port ready */
578 tmp = ata_wait_register(port + PORT_CTRL_STAT,
579 PORT_CS_RDY, PORT_CS_RDY, 100);
580 if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
581 printf("%d port not ready.\n", dev);
582 return 1;
583 }
584
585 /* configure port */
586 sil_config_port(port);
587
588 /* Reset port */
589 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
590 readl(port + PORT_CTRL_STAT);
591 tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
592 PORT_CS_DEV_RST, 100);
593 if (tmp & PORT_CS_DEV_RST) {
594 printf("%d port reset failed.\n", dev);
595 return 1;
596 }
597
598 sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
599 if (!sata) {
600 printf("%d no memory.\n", dev);
601 return 1;
602 }
603 memset((void *)sata, 0, sizeof(struct sil_sata));
604
605 /* Save the private struct to block device struct */
606 #if !CONFIG_IS_ENABLED(BLK)
607 sata_dev_desc[dev].priv = (void *)sata;
608 #else
609 priv->sil_sata_desc[dev] = sata;
610 priv->port_num = dev;
611 #endif
612 sata->id = dev;
613 sata->port = port;
614 sata->devno = sata_info.devno;
615 sprintf(sata->name, "SATA#%d", dev);
616 sil_cmd_soft_reset(sata);
617 tmp = readl(port + PORT_SSTATUS);
618 tmp = (tmp >> 4) & 0xf;
619 printf(" (%s)\n", sata_spd_string(tmp));
620
621 return 0;
622 }
623
624 #if !CONFIG_IS_ENABLED(BLK)
625 /*
626 * SATA interface between low level driver and command layer
627 */
628 int init_sata(int dev)
629 {
630 static int init_done, idx;
631 pci_dev_t devno;
632 u16 word;
633
634 if (init_done == 1 && dev < sata_info.maxport)
635 goto init_start;
636
637 init_done = 1;
638
639 /* Find PCI device(s) */
640 devno = pci_find_devices(supported, idx++);
641 if (devno == -1)
642 return 1;
643
644 pci_read_config_word(devno, PCI_DEVICE_ID, &word);
645
646 /* get the port count */
647 word &= 0xf;
648
649 sata_info.portbase = 0;
650 sata_info.maxport = sata_info.portbase + word;
651 sata_info.devno = devno;
652
653 /* Read out all BARs */
654 sata_info.iobase[0] = (ulong)pci_map_bar(devno,
655 PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
656 sata_info.iobase[1] = (ulong)pci_map_bar(devno,
657 PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
658
659 /* mask out the unused bits */
660 sata_info.iobase[0] &= 0xffffff80;
661 sata_info.iobase[1] &= 0xfffffc00;
662
663 /* Enable Bus Mastering and memory region */
664 pci_write_config_word(devno, PCI_COMMAND,
665 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
666
667 /* Check if mem accesses and Bus Mastering are enabled. */
668 pci_read_config_word(devno, PCI_COMMAND, &word);
669 if (!(word & PCI_COMMAND_MEMORY) ||
670 (!(word & PCI_COMMAND_MASTER))) {
671 printf("Error: Can not enable MEM access or Bus Mastering.\n");
672 debug("PCI command: %04x\n", word);
673 return 1;
674 }
675
676 /* GPIO off */
677 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
678 /* clear global reset & mask interrupts during initialization */
679 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
680
681 init_start:
682 return sil_init_sata(dev);
683 }
684
685 int reset_sata(int dev)
686 {
687 return 0;
688 }
689
690 /*
691 * SATA interface between low level driver and command layer
692 */
693 int scan_sata(int dev)
694 {
695 struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
696 #else
697 static int scan_sata(struct udevice *blk_dev, int dev)
698 {
699 struct blk_desc *desc = dev_get_uclass_platdata(blk_dev);
700 struct sil_sata_priv *priv = dev_get_platdata(blk_dev);
701 struct sil_sata *sata = priv->sil_sata_desc[dev];
702 #endif
703 unsigned char serial[ATA_ID_SERNO_LEN + 1];
704 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
705 unsigned char product[ATA_ID_PROD_LEN + 1];
706 u16 *id;
707
708 id = (u16 *)malloc(ATA_ID_WORDS * 2);
709 if (!id) {
710 printf("Id malloc failed\n");
711 return 1;
712 }
713 sil_cmd_identify_device(sata, id);
714
715 sil_sata_set_feature_by_id(sata, id);
716
717 /* Serial number */
718 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
719
720 /* Firmware version */
721 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
722
723 /* Product model */
724 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
725
726 #if !CONFIG_IS_ENABLED(BLK)
727 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
728 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
729 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
730 /* Totoal sectors */
731 sata_dev_desc[dev].lba = ata_id_n_sectors(id);
732 #ifdef CONFIG_LBA48
733 sata_dev_desc[dev].lba48 = sata->lba48;
734 #endif
735 #else
736 memcpy(desc->product, serial, sizeof(serial));
737 memcpy(desc->revision, firmware, sizeof(firmware));
738 memcpy(desc->vendor, product, sizeof(product));
739 desc->lba = ata_id_n_sectors(id);
740 #ifdef CONFIG_LBA48
741 desc->lba48 = sata->lba48;
742 #endif
743 #endif
744
745 #ifdef DEBUG
746 ata_dump_id(id);
747 #endif
748 free((void *)id);
749
750 return 0;
751 }
752
753 #if CONFIG_IS_ENABLED(BLK)
754 static const struct blk_ops sata_sil_blk_ops = {
755 .read = sata_read,
756 .write = sata_write,
757 };
758
759 U_BOOT_DRIVER(sata_sil_driver) = {
760 .name = "sata_sil_blk",
761 .id = UCLASS_BLK,
762 .ops = &sata_sil_blk_ops,
763 .platdata_auto_alloc_size = sizeof(struct sil_sata_priv),
764 };
765
766 static int sil_pci_probe(struct udevice *dev)
767 {
768 struct udevice *blk;
769 char sata_name[10];
770 pci_dev_t devno;
771 u16 word;
772 int ret;
773 int i;
774
775 /* Get PCI device number */
776 devno = dm_pci_get_bdf(dev);
777 if (devno == -1)
778 return 1;
779
780 dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
781
782 /* get the port count */
783 word &= 0xf;
784
785 sata_info.portbase = 0;
786 sata_info.maxport = sata_info.portbase + word;
787 sata_info.devno = devno;
788
789 /* Read out all BARs */
790 sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
791 PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
792 sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
793 PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
794
795 /* mask out the unused bits */
796 sata_info.iobase[0] &= 0xffffff80;
797 sata_info.iobase[1] &= 0xfffffc00;
798
799 /* Enable Bus Mastering and memory region */
800 dm_pci_write_config16(dev, PCI_COMMAND,
801 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
802
803 /* Check if mem accesses and Bus Mastering are enabled. */
804 dm_pci_read_config16(dev, PCI_COMMAND, &word);
805 if (!(word & PCI_COMMAND_MEMORY) ||
806 (!(word & PCI_COMMAND_MASTER))) {
807 printf("Error: Can not enable MEM access or Bus Mastering.\n");
808 debug("PCI command: %04x\n", word);
809 return 1;
810 }
811
812 /* GPIO off */
813 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
814 /* clear global reset & mask interrupts during initialization */
815 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
816
817 for (i = sata_info.portbase; i < sata_info.maxport; i++) {
818 snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
819 ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
820 IF_TYPE_SATA, -1, 512, 0, &blk);
821 if (ret) {
822 debug("Can't create device\n");
823 return ret;
824 }
825
826 ret = sil_init_sata(blk, i);
827 if (ret)
828 return -ENODEV;
829
830 ret = scan_sata(blk, i);
831 if (ret)
832 return -ENODEV;
833 }
834
835 return 0;
836 }
837
838 static int sata_sil_scan(struct udevice *dev)
839 {
840 /* Nothing to do here */
841
842 return 0;
843 }
844
845 struct sil_ops sata_sil_ops = {
846 .scan = sata_sil_scan,
847 };
848
849 static const struct udevice_id sil_pci_ids[] = {
850 { .compatible = "sil-pci-sample" },
851 { }
852 };
853
854 U_BOOT_DRIVER(sil_ahci_pci) = {
855 .name = "sil_ahci_pci",
856 .id = UCLASS_AHCI,
857 .of_match = sil_pci_ids,
858 .ops = &sata_sil_ops,
859 .probe = sil_pci_probe,
860 .priv_auto_alloc_size = sizeof(struct sil_sata_priv),
861 };
862
863 U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
864 #endif
865