1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 18 */ 19 20 #ifndef DDR_PHY_S28_V300_H 21 #define DDR_PHY_S28_V300_H 22 23 /* register offset address */ 24 /* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */ 25 /* control the initialization of the PHY */ 26 #define DDR_PHY_PHYINITCTRL 0x4 27 #define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error */ 28 #define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */ 29 #define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ 30 #define DDR_PHY_TRAINCTRL0 0x48 /* hw training control */ 31 #define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */ 32 #define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */ 33 /* update delay setting in registers to PHY */ 34 #define DDR_PHY_MISC 0x70 35 #define DDR_PHY_DMSEL 0x84 /* DM Swap Selection */ 36 #define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */ 37 /* issue one DQS pulse from PHY to DRAM */ 38 #define DDR_PHY_SWTWLDQS 0xa4 39 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result */ 40 /* Host vref. [5:0]range [17:12]refsel */ 41 #define DDR_PHY_PHYRSCTRL 0xB0 /* PHY Register Slice Contrl */ 42 #define DDR_PHY_IOCTL2 0xB4 43 #define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */ 44 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ 45 #define DDR_PHY_ACADDRBDL(n) (0x140 + ((n) << 2)) 46 #define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */ 47 #define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */ 48 #define DDR_PHY_CATSWAPINDEX 0x01B8 /* CA SWAP index register */ 49 #define DDR_PHY_CATSWAPSEL 0x01BC /* CA SWAP select register */ 50 #define DDR_PHY_CATCONFIG 0x1C8 /* CA Training Configuration */ 51 #define DDR_PHY_PHYDQRESULT 0x1D0 /* SW CA Training DQ result from PHY */ 52 #define DDR_PHY_ADDRPHBOUND 0x1D4 /* CA Training addr phase boundary */ 53 #define DDR_PHY_SWCATPATTERN_P 0x1D8 /* pattern for positive CK edge */ 54 #define DDR_PHY_SWCATPATTERN_N 0x1DC /* pattern for negative CK edge */ 55 56 /* AC command bit delay line setting */ 57 #define DDR_PHY_ACCMDBDL2 0x128 58 59 /* WR DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line 60 on write path */ 61 #define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + (((m) & 0) << 10) + ((n) << 7)) 62 /* WR DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] */ 63 #define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + (((m) & 0) << 10) + ((n) << 7)) 64 /* WR DM [6:0] the delay value of the bit delay line on DQM */ 65 #define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + (((m) & 0) << 10) + ((n) << 7)) 66 /* RD DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line 67 on read path */ 68 #define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7)) 69 /* RD DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line 70 on read path */ 71 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) 72 /* [6:0]RD DM */ 73 #define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7)) 74 75 /* [CUSTOM] */ 76 #define DDR_PHY_DXNOEBDL(m, n) (0x228 + (((m) & 0) << 10) + ((n) << 7)) 77 /* [8:0] rdqs_bdl [24:16]rdqs_cyc. 78 phase shift of the Read DQS to create 90 degree delays */ 79 #define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7)) 80 /* [6:0] the delay value of delay applied on WDQS for write leveling */ 81 #define DDR_PHY_DXWDQSDLY(m, n) (0x230 + (((m) & 0) << 10) + ((n) << 7)) 82 /* WR DQ phase BIT 12:8 */ 83 #define DDR_PHY_DXNWDQDLY(m, n) (0x234 + (((m) & 0) << 10) + ((n) << 7)) 84 /* [CUSTOM] rddqs gating */ 85 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) 86 /* read boundary right 8:0 left 24:16 */ 87 #define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7)) 88 /* write boundary right 4:0 left 20:16 */ 89 #define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7)) 90 /* [5:0] DRAM VREF(DQ) training result */ 91 #define DDR_PHY_DVREFT_STATUS(n) (0x270 + ((n) << 7)) 92 /* [4:0] Host PHY VREF(DQ) training result */ 93 #define DDR_PHY_HVREFT_STATUS(m, n) (0x274 + (((m) & 0) << 10) + ((n) << 7)) 94 95 /* DDRPHY AC static register */ 96 #define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */ 97 #define DDR_PHY_ACPHYCTL4 0x1064 /* AC block PHY control register */ 98 #define DDR_PHY_ACPHYCTL7 0x1070 99 /* HIDDRPHY_DX_STATIC_REG_DDR4 */ 100 /* Data block PHY miscellaneous control register. */ 101 #define DX_DXNMISCCTRL0(p) (0x1238 + ((p) << 7)) 102 /* Data block PHY debug/miscellaneous control register. dxctl_pre_margin_code [24:22] */ 103 #define DX_DXNMISCCTRL3(p) (0x1254 + ((p) << 7)) 104 105 #ifndef DDR_VREF_HOST_VAL_MAX 106 #define DDR_VREF_HOST_VAL_MAX 0x3f /* 78.75%*VDDIO */ 107 #endif 108 #define DDR_VREF_HOST_VAL_MIN 0x0 /* 40.00%*VDDIO */ 109 110 /* register mask */ 111 #define PHY_BDL_MASK 0x7f /* [6:0] */ 112 #define PHY_WDQS_PHASE_MASK 0xf /* [11:8] */ 113 #define PHY_RDQS_BDL_MASK 0x1ff /* [CUSTOM] [8:0] rdqsbdl */ 114 #define PHY_RDQSG_PHASE_MASK 0x3f /* [14:9] rdqsgphase */ 115 #define PHY_RDM_BDL_MASK 0x7f /* [6:0] */ 116 /* hardware gate training result */ 117 #define PHY_INITSTATUS_GT_MASK 0x20 118 #define PHY_SWTRLT_WL_MASK 0xf 119 #define PHY_SWTRLT_GATE_MASK 0xf 120 #define PHY_WDQ_PHASE_MASK 0x3f 121 #define PHY_PHYINITCTRL_MASK 0x1 /* [15:0] all stat */ 122 /* Read Data Eye Calibration Error */ 123 #define PHY_PHYINITSTATUS_RDET_ERR 0x100 124 #define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */ 125 #define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */ 126 #define PHY_VRFTRES_DVREF_MASK 0x3f /* [5:0] */ 127 #ifndef PHY_VRFTRES_HVREF_MASK 128 #define PHY_VRFTRES_HVREF_MASK 0x3f /* [4:0] */ 129 #endif 130 #define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */ 131 #define PHY_ADDRPH_MASK 0x1f /* [20:16] */ 132 #define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */ 133 #define PHY_CATSWAPSEL_BIT_MASK 0xff 134 #define PHY_CAT_PATTERN_MASK 0x3ff 135 #define PHY_TRAINCTRL0_MASK 0xf /* [3:0] */ 136 #define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ 137 #define PHY_OSC_START_MASK 0x1 /* [0] */ 138 #define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */ 139 #define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */ 140 #define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */ 141 #define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */ 142 #define DX_DXNMISCCTRL0_DQ_MASK 0Xff /* [15:8] dxctl_rxp_2nd_dq */ 143 #define DX_DXNMISCCTRL0_DM_MASK 0X1 /* [20] dxctl_rxp_2nd_dm */ 144 #define DX_DXNMISCCTRL3_MASK 0X7 /* [24:22] dxctl_pre_margin_code */ 145 146 /* register bit */ 147 #define PHY_MISC_UPDATE_BIT 19 /* [CUSTOM] delay config update bit */ 148 #define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */ 149 #define PHY_RDQSG_PHASE_BIT 9 /* [CUSTOM] */ 150 #define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */ 151 #define PHY_WDQS_PHASE_BIT 8 152 #define PHY_WDQS_BDL_BIT 0 153 #define PHY_WDQ_PHASE_BIT 8 154 #define PHY_WDM_BDL_BIT 0 155 /* [22:16] Write DQS Output Enable Delay Control */ 156 #define PHY_WDQSOE_BDL_BIT 16 157 #define PHY_OEN_BDL_BIT 0 158 /* Mode Register 1. Defines the MR3/MR9 of the mode register */ 159 #define PHY_MODEREG01_MR1_BIT 16 160 /* Bit delay line setting of CS1 */ 161 #define PHY_ACCMD_CS0_BIT 0 162 #define PHY_ACCMD_CS1_BIT 16 163 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ 164 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ 165 #define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */ 166 #define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */ 167 #define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */ 168 #define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */ 169 #define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ 170 #define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */ 171 #define PHY_OSC_RPT_VLD 15 /* [15] */ 172 #define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */ 173 #define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */ 174 #define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */ 175 #define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */ 176 #define DX_DXNMISCCTRL0_DQ_BIT 8 /* [15:8] dxctl_rxp_2nd_dq */ 177 #define DX_DXNMISCCTRL0_DM_BIT 20 /* [20] dxctl_rxp_2nd_dm */ 178 #define DX_DXNMISCCTRL3_BIT 22 /* [24:22] dxctl_pre_margin_code */ 179 #define PHY_CFG_RX_AGE_COMPST_EN_BIT 31 /* Enable rdqs age compensation function */ 180 /* BDL register bit */ 181 #define PHY_BDL_DQ_BIT 0 182 #define PHY_BDL_DQ0_BIT 0 183 #define PHY_BDL_DQ1_BIT 8 184 #define PHY_BDL_DQ2_BIT 16 185 #define PHY_BDL_DQ3_BIT 24 186 #define PHY_RDM_BDL_BIT 0 187 #define PHY_RDQS_BDL_BIT 0 188 189 /* value */ 190 #define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */ 191 /* hw training item defined in PHYINITCTRL */ 192 #define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */ 193 #define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */ 194 #define PHY_PHYINITCTRL_PIC_TDQSST (1 << 28) /* TDQSS training Enable. */ 195 #define PHY_PHYINITCTRL_CFG_LPBK_COMPST_EN (1 << 27) /* RDQS/CK loopback delay compensate enable. */ 196 #define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */ 197 #define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */ 198 #define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */ 199 #define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */ 200 #define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */ 201 #define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */ 202 #define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */ 203 #define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */ 204 #define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */ 205 #define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */ 206 #define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */ 207 #define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */ 208 #define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */ 209 #define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */ 210 #define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */ 211 #define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */ 212 #define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */ 213 #define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */ 214 #define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */ 215 #define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */ 216 #define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */ 217 #define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */ 218 #define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */ 219 #define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */ 220 #define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */ 221 #define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */ 222 #define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */ 223 224 #define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST) 225 #define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST) 226 #define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN) 227 #define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN) 228 #define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN) 229 #define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN) 230 #define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC) 231 #define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \ 232 | PHY_PHYINITCTRL_GT_EN \ 233 | PHY_PHYINITCTRL_GDST_EN \ 234 | PHY_PHYINITCTRL_WL2_EN \ 235 | PHY_PHYINITCTRL_RDET_EN \ 236 | PHY_PHYINITCTRL_WDET_EN \ 237 | PHY_PHYINITCTRL_DVREFT_EN \ 238 | PHY_PHYINITCTRL_HVREFT_EN \ 239 | PHY_PHYINITCTRL_PIC_TDQSST) 240 #define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST) 241 242 /* RDQS range[0, 0x7f], middle value is 0x40, but it affected by 243 temperature, so middle value change to 0x30 */ 244 #define PHY_RDQS_MIDDLE_VAL 0x30 245 /* DQ range[0, 0x7f], middle value is 0x40, but it affected by 246 temperature, so middle value change to 0x30 */ 247 #define PHY_DQ_MIDDLE_VAL 0x30303030 248 #define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */ 249 #define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ 250 #define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */ 251 /* [5] two cycle on address or command.(2T timing) */ 252 #define PHY_DRAMCFG_MA2T 0x20 253 254 #define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */ 255 #define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */ 256 #define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */ 257 #define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */ 258 #define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */ 259 #define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */ 260 #define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */ 261 #define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ 262 #define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */ 263 264 #define PHY_DMSEL_SWAPDFIBYTE 0xf8ffffff /* [24:26] No Swap */ 265 /* other */ 266 #define PHY_RDQSG_PHASE_STEP 2 /* gate training phase step. */ 267 #define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */ 268 #define PHY_DQ_BDL_LEVEL 128 /* [CUSTOM] DQ BDL range */ 269 #define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ 270 #define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */ 271 #define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */ 272 273 /* AC_DDRPHY_GATED_BYPASS */ 274 #define PHY_CK_IOCTL_DUTY_EN 0x4 /* enable ck_ioctl_DUTY_EN_v */ 275 #define PHY_CK1_IOCTL_DUTY_EN 0x8 /* enable ck1_ioctl_DUTY_EN_v */ 276 /* CK AC_IOCTL22 */ 277 #ifndef DDR_DUTY_NUM 278 #define DDR_DUTY_NUM 8 /* CK duty number */ 279 #endif 280 #ifndef DDR_CK_NUM 281 #define DDR_CK_NUM 2 /* DDR CK number */ 282 #endif 283 #ifndef DDR_DUTY_CTL_NUM 284 #define DDR_DUTY_CTL_NUM 2 /* CK duty has two control direction */ 285 #endif 286 /* CK duty step. */ 287 #ifndef PHY_AC_IOCTL21_STEP 288 #define PHY_AC_IOCTL21_STEP 1 289 #endif 290 /** 291 * DDR_BDL_PHASE_REL Calculation Method: 292 * 1. Calculation How many picosecond to one phase. 293 * PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond 294 * WAVE : 1 cycle is 2 295 * RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps 296 * PHASE : 1 wave is 12 phase 297 * phase = (((PICOSECOND * WAVE) / RATE) / PHASE) 298 * = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 12) 299 * = 104.17 ps. 300 * 2. Calculation How many bdl to one phase. 301 * one BDL is 6 ps. 302 * result = phase/bdl = 104.17 / 6 = 17.36 approximately equal to 17 ~= 16 303 * 3. 16 = 1 << 4, so the relation is 4. 304 */ 305 #ifndef DDR_BDL_PHASE_TRANSFORM 306 /* [CUSTOM] one Phase equal how much BDL. 1 phase = 16 bdl */ 307 #define DDR_BDL_PHASE_TRANSFORM 16 308 #endif 309 #ifndef DDR_BDL_PHASE_REL 310 /* [CUSTOM] relation between BDL and Phase. 1 phase = 16 bdl, 16 = 1 << 4 */ 311 #define DDR_BDL_PHASE_REL 4 312 #endif 313 314 #define DDR_VARIABLE_DECLARE(var) \ 315 unsigned int var; 316 317 #define DDR_VREF_GET_HOST_MAX(rank, val) \ 318 do { \ 319 if (0 == (rank)) \ 320 (val) = PHY_VRFTRES_HVREF_MASK; \ 321 else \ 322 (val) = PHY_VRFTRES_RXDIFFCAL_MASK; \ 323 } while (0) 324 325 /* PHY t28 all byte use a same value */ 326 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ 327 do { \ 328 unsigned int hvreft; \ 329 hvreft = ddr_read((base_phy) + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ 330 & (~PHY_VRFTRES_HVREF_MASK); \ 331 ddr_write(hvreft | (val), (base_phy) + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ 332 ddr_write(hvreft | (val), (base_phy) + DDR_PHY_HVREFT_STATUS(rank, (byte_index) + 1)); \ 333 } while (0) 334 335 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ 336 do { \ 337 val = ddr_read((base_phy) + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ 338 & PHY_VRFTRES_HVREF_MASK; \ 339 } while (0) 340 341 #define DDR_PHY_VREF_HOST_DISPLAY \ 342 {0, 0, DDR_PHY_HVREFT_STATUS(0, 0), 0, "Host Vref Byte0"}, \ 343 {0, 1, DDR_PHY_HVREFT_STATUS(0, 1), 0, "Host Vref Byte1"}, \ 344 {0, 2, DDR_PHY_HVREFT_STATUS(0, 2), 0, "Host Vref Byte2"}, \ 345 {0, 3, DDR_PHY_HVREFT_STATUS(0, 3), 0, "Host Vref Byte3"}, 346 347 #define DDR_PHY_VREF_HOST_DISPLAY_RANK1 \ 348 {1, 0, DDR_PHY_HVREFT_STATUS(1, 0), 0, "Host Vref Byte0"}, \ 349 {1, 1, DDR_PHY_HVREFT_STATUS(1, 1), 0, "Host Vref Byte1"}, \ 350 {1, 2, DDR_PHY_HVREFT_STATUS(1, 2), 0, "Host Vref Byte2"}, \ 351 {1, 3, DDR_PHY_HVREFT_STATUS(1, 3), 0, "Host Vref Byte3"}, 352 353 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ 354 do { \ 355 unsigned int _i; \ 356 for (_i = 0; _i < (byte_num); _i++) { \ 357 DDR_INFO("[%x = %x] Host Vref Byte(%x)", \ 358 (base_phy) + DDR_PHY_HVREFT_STATUS(rank, _i), \ 359 ddr_read((base_phy) \ 360 + DDR_PHY_HVREFT_STATUS(rank, _i)), _i); \ 361 } \ 362 } while (0) 363 364 /* DRAM vref operations */ 365 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ 366 do { \ 367 unsigned int dvrftctrl = \ 368 ddr_read((base_phy) + DDR_PHY_DVRFTCTRL); \ 369 unsigned int dvreft = ddr_read((base_phy) \ 370 + DDR_PHY_DVREFT_STATUS(byte_index)) \ 371 & (~PHY_VRFTRES_DVREF_MASK); \ 372 ddr_write(dvrftctrl | PHY_DVRFTCTRL_PDAEN_EN, \ 373 (base_phy) + DDR_PHY_DVRFTCTRL); \ 374 ddr_write(dvreft | (val), \ 375 (base_phy) + DDR_PHY_DVREFT_STATUS(byte_index)); \ 376 ddr_write(PHY_PHYINITCTRL_DVREFT_SYNC \ 377 | PHY_PHYINITCTRL_INIT_EN, \ 378 (base_phy) + DDR_PHY_PHYINITCTRL); \ 379 while (1) { \ 380 if (!(ddr_read((base_phy) + DDR_PHY_PHYINITCTRL) \ 381 & PHY_PHYINITCTRL_INIT_EN)) \ 382 break; \ 383 } \ 384 ddr_write(dvrftctrl & (~PHY_DVRFTCTRL_PDAEN_EN), \ 385 (base_phy) + DDR_PHY_DVRFTCTRL); \ 386 } while (0) 387 388 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ 389 { \ 390 val = ddr_read((base_phy) + DDR_PHY_DVREFT_STATUS(byte_index)) \ 391 & PHY_VRFTRES_DVREF_MASK; \ 392 } 393 394 #define DDR_PHY_VREF_DRAM_DISPLAY \ 395 {0, 0, DDR_PHY_DVREFT_STATUS(0), 0, "DRAM Vref Byte0"}, \ 396 {0, 1, DDR_PHY_DVREFT_STATUS(1), 0, "DRAM Vref Byte1"}, \ 397 {0, 2, DDR_PHY_DVREFT_STATUS(2), 0, "DRAM Vref Byte2"}, \ 398 {0, 3, DDR_PHY_DVREFT_STATUS(3), 0, "DRAM Vref Byte3"}, 399 400 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ 401 do { \ 402 unsigned int _i; \ 403 for (_i = 0; _i < (byte_num); _i++) { \ 404 DDR_INFO("[%x = %x] DRAM Vref Byte(%x)", \ 405 (base_phy) + DDR_PHY_DVREFT_STATUS(_i), \ 406 ddr_read((base_phy) \ 407 + DDR_PHY_DVREFT_STATUS(_i)), _i); \ 408 } \ 409 } while (0) 410 411 /* Dx dpmc operations */ 412 #define DDR_DX_DPMC_DISPLAY \ 413 {0, 0, DX_DXNMISCCTRL3(0), 0, "Dpmc Byte0"}, \ 414 {0, 1, DX_DXNMISCCTRL3(1), 0, "Dpmc Byte1"}, \ 415 {0, 2, DX_DXNMISCCTRL3(2), 0, "Dpmc Byte2"}, \ 416 {0, 3, DX_DXNMISCCTRL3(3), 0, "Dpmc Byte3"}, 417 418 #define DDR_DX_DPMC_DISPLAY_CMD(base_phy, byte_num) \ 419 do { \ 420 unsigned int _i; \ 421 for (_i = 0; _i < (byte_num); _i++) { \ 422 DDR_INFO("[%x = %x] Dpmc Byte(%x)", \ 423 (base_phy) + DX_DXNMISCCTRL3(_i), \ 424 ddr_read((base_phy) \ 425 + DX_DXNMISCCTRL3(_i)), _i); \ 426 } \ 427 } while (0) 428 429 /* phy t28 not support DCC training */ 430 #define DDR_PHY_DCC_DISPLAY 431 #define DDR_PHY_DCC_DISPLAY_CMD(base_phy) 432 433 /* lowpower ddr ca operations */ 434 #define DDR_PHY_ADDRPH_DISPLAY \ 435 {0, 0, DDR_PHY_ADDRPHBOUND, 0, "CA Phase"}, 436 437 #define DDR_PHY_ADDRBDL_DISPLAY \ 438 {0, 0, DDR_PHY_ACADDRBDL(0), 0, "CA BDL(0)"}, \ 439 {0, 0, DDR_PHY_ACADDRBDL(1), 0, "CA BDL(1)"}, \ 440 {0, 0, DDR_PHY_ACADDRBDL(2), 0, "CA BDL(2)"}, \ 441 {0, 0, DDR_PHY_ACADDRBDL(3), 0, "CA BDL(3)"}, \ 442 {0, 0, DDR_PHY_ACADDRBDL(4), 0, "CA BDL(4)"}, 443 444 #define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) \ 445 DDR_INFO("[%x = %x] CA Phase", \ 446 (base_phy) + DDR_PHY_ADDRPHBOUND, \ 447 ddr_read((base_phy) + DDR_PHY_ADDRPHBOUND)); 448 449 #define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) \ 450 do { \ 451 unsigned int _i; \ 452 for (_i = 0; _i < DDR_PHY_CA_REG_MAX; _i++) { \ 453 DDR_INFO("[%x = %x] ACADDRBDL(%x)", \ 454 (base_phy) + DDR_PHY_ACADDRBDL(_i), \ 455 ddr_read((base_phy) \ 456 + DDR_PHY_ACADDRBDL(_i)), _i); \ 457 } \ 458 } while (0) 459 460 /* PHY t28 DDR4 RDQS synchronize to RDM */ 461 #define DDR_PHY_RDQS_SYNC_RDM(cfg, val) \ 462 ddr_rdqs_sync(cfg, val) 463 464 /* dqs swap */ 465 #define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) \ 466 do { \ 467 (swapdfibyte_en) = \ 468 ddr_read((base_phy) + DDR_PHY_DMSEL); \ 469 ddr_write((swapdfibyte_en) & PHY_DMSEL_SWAPDFIBYTE, \ 470 (base_phy) + DDR_PHY_DMSEL); \ 471 } while (0) 472 473 #define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) \ 474 ddr_write(swapdfibyte_en, (base_phy) + DDR_PHY_DMSEL); 475 476 477 #define DDR_PHY_SWITCH_RANK(base_phy, val) \ 478 do { \ 479 ddr_write((ddr_read((base_phy) + DDR_PHY_TRAINCTRL0) & (~PHY_TRAINCTRL0_MASK)) | (val), \ 480 (base_phy) + DDR_PHY_TRAINCTRL0); \ 481 } while (0) 482 483 /* Define the union U_PHY_CATCONFIG */ 484 union U_PHY_CATCONFIG { 485 /* Define the struct bits */ 486 struct { 487 unsigned int ca_samp_num_bdl:4; /* [3:0] */ 488 unsigned int ca_samp_num_ph:4; /* [7:4] */ 489 unsigned int ca_trysamp_num:4; /* [11:8] */ 490 unsigned int cat_rb_backtap:4; /* [15:12] */ 491 unsigned int reserved:1; /* [16] */ 492 unsigned int cat_openeye_en:1; /* [17] */ 493 unsigned int cat_cat_phydq_sel:1; /* [18] */ 494 unsigned int cat_restore_en:1; /* [19] */ 495 unsigned int cat_lb_backtap:4; /* [23:20] */ 496 unsigned int sw_cat_mrw42:1; /* [24] */ 497 unsigned int sw_cat_mrw48:1; /* [25] */ 498 unsigned int sw_cat_mrw41:1; /* [26] */ 499 unsigned int sw_cat_strobe:1; /* [27] */ 500 unsigned int sw_cat_cke_high:1; /* [28] */ 501 unsigned int sw_cat_cke_low:1; /* [29] */ 502 unsigned int sw_cat_dqvalid:1; /* [30] */ 503 unsigned int sw_cat_en:1; /* [31] */ 504 } bits; 505 506 /* Define an unsigned member */ 507 unsigned int u32; 508 }; 509 510 /* Define the union U_PHY_ADDRPHBOUND */ 511 union U_PHY_ADDRPHBOUND { 512 /* Define the struct bits */ 513 struct { 514 unsigned int addrph_a_right:5; /* [4:0] */ 515 unsigned int reserved0:3; /* [7:5] */ 516 unsigned int addrph_a_left:5; /* [12:8] */ 517 unsigned int reserved1:3; /* [15:13] */ 518 unsigned int addrph_a:5; /* [20:16] */ 519 unsigned int reserved2:3; /* [23:21] */ 520 unsigned int addrph_a_ori:5; /* [28:24] */ 521 unsigned int reserved3:3; /* [31:29] */ 522 } bits; 523 524 /* Define an unsigned member */ 525 unsigned int u32; 526 }; 527 #endif /* DDR_PHY_S28_V300_H */