1 /** 2 * ddr_phy_t12_v101.h 3 * 4 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 * 19 20 * DDR PHY register offset address, mask, bit. 21 */ 22 23 /* register offset address */ 24 /* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */ 25 /* control the initialization of the PHY */ 26 #define DDR_PHY_PHYINITCTRL 0x4 27 #define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error*/ 28 #define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */ 29 #define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ 30 #define DDR_PHY_TRAINCTRL0 0x48 /* hw training control */ 31 #define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */ 32 #define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */ 33 /* update delay setting in registers to PHY */ 34 #define DDR_PHY_MISC 0x70 35 #define DDR_PHY_DMSEL 0x84 /* DM Swap Selection */ 36 #define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */ 37 /* issue one DQS pulse from PHY to DRAM */ 38 #define DDR_PHY_SWTWLDQS 0xa4 39 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ 40 /* Host vref. [5:0]range [17:12]refsel */ 41 #define DDR_PHY_IOCTL2 0xB4 42 #define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */ 43 #define DDR_PHY_HVRFTCTRL 0xc8 /* Host VREF Training Control Regiser. */ 44 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ 45 #define DDR_PHY_ACADDRBDL(n) (0x140 + ((n) << 2)) 46 #define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */ 47 #define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */ 48 #define DDR_PHY_CATSWAPINDEX 0x01B8 /* CA SWAP index register */ 49 #define DDR_PHY_CATSWAPSEL 0x01BC /* CA SWAP select register*/ 50 #define DDR_PHY_CATCONFIG 0x1C8 /* CA Training Configuration */ 51 #define DDR_PHY_PHYDQRESULT 0x1D0 /* SW CA Training DQ result from PHY */ 52 #define DDR_PHY_ADDRPHBOUND 0x1D4 /* CA Training addr phase boundary */ 53 #define DDR_PHY_SWCATPATTERN_P 0x1D8 /* pattern for positive CK edge */ 54 #define DDR_PHY_SWCATPATTERN_N 0x1DC /* pattern for negative CK edge */ 55 /* AC command bit delay line setting */ 56 #define DDR_PHY_ACCMDBDL2 0x128 57 58 #define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + ((m) << 10) + ((n) << 7)) 59 #define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + ((m) << 10) + ((n) << 7)) 60 #define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + ((m) << 10) + ((n) << 7)) 61 #define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7)) 62 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) 63 #define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7)) 64 #define DDR_PHY_DXNOEBDL(m, n) (0x228 + ((m) << 10) + ((n) << 7)) 65 #define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7)) 66 #define DDR_PHY_DXWDQSDLY(m, n) (0x230 + ((m) << 10) + ((n) << 7)) 67 #define DDR_PHY_DXNWDQDLY(m, n) (0x234 + ((m) << 10) + ((n) << 7)) 68 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) 69 #define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7)) 70 #define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7)) 71 #define DDR_PHY_DVREFT_STATUS(n) (0x270 + ((n) << 7)) 72 #define DDR_PHY_HVREFT_STATUS(m, n) (0x274 + ((m) << 10) + ((n) << 7)) 73 74 /* DDRPHY AC static register */ 75 #define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */ 76 #define DDR_PHY_ACPHYCTL4 0x1064 /* AC block PHY control register*/ 77 #define DDR_PHY_ACPHYCTL7 0x1070 78 #define DDR_PHY_ACIOCTL21 0x10F4 79 #define DDR_PHY_AC_GATED_BYPASS 0x10FC /* bypass clock gated function */ 80 81 /* register mask */ 82 #define PHY_BDL_MASK 0x7f /* [7:1] */ 83 #define PHY_WDQS_PHASE_MASK 0x1f /* [13:9] */ 84 #define PHY_RDQS_BDL_MASK 0x1ff /* [CUSTOM] [9:1] rdqsbdl*/ 85 #define PHY_RDQSG_PHASE_MASK 0x1ff /* [18:10] rdqsgphase */ 86 #define PHY_RDM_BDL_MASK 0x7f /* [7:1] */ 87 /* hardware gate training result */ 88 #define PHY_INITSTATUS_GT_MASK 0x20 89 #define PHY_SWTRLT_WL_MASK 0xf 90 #define PHY_SWTRLT_GATE_MASK 0xf 91 #define PHY_WDQ_PHASE_MASK 0x7f 92 #define PHY_PHYINITCTRL_MASK 0x1 93 /* Read Data Eye Calibration Error */ 94 #define PHY_PHYINITSTATUS_RDET_ERR 0x100 95 #define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */ 96 #define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */ 97 #define PHY_VRFTRES_DVREF_MASK 0x3f /* [5:0] */ 98 #define PHY_VRFTRES_HVREF_MASK 0x7f /* [6:0] */ 99 #define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */ 100 101 #define PHY_ADDRPH_MASK 0x1f /* [20:16] */ 102 #define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */ 103 #define PHY_CATSWAPSEL_BIT_MASK 0xff 104 #define PHY_CAT_PATTERN_MASK 0x3ff 105 #define PHY_TRAINCTRL0_MASK 0xf /* [3:0] */ 106 #define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ 107 #define PHY_ACIOCTL21_MASK 0xf /* [31:28],[15:12] */ 108 #define PHY_DXNRDBOUND_MASK 0x1ff /* [25:17],[9:1] */ 109 #define PHY_OSC_START_MASK 0x1 /* [0] */ 110 #define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */ 111 #define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */ 112 #define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */ 113 #define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */ 114 115 /* register bit */ 116 #define PHY_MISC_UPDATE_BIT 19 /* [CUSTOM] delay config update bit */ 117 #define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */ 118 #define PHY_RDQSG_PHASE_BIT 10 /* [CUSTOM] */ 119 #define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */ 120 #define PHY_WDQS_PHASE_BIT 9 121 #define PHY_WDQS_BDL_BIT 1 122 #define PHY_WDQ_PHASE_BIT 9 123 #define PHY_WDM_BDL_BIT 1 124 /* [22:16] Write DQS Output Enable Delay Control */ 125 #define PHY_WDQSOE_BDL_BIT 17 126 #define PHY_OEN_BDL_BIT 1 127 /* Mode Register 1. Defines the MR3/MR9 of the mode register */ 128 #define PHY_MODEREG01_MR1_BIT 16 129 /* Bit delay line setting of CS1 */ 130 #define PHY_ACCMD_CS0_BIT 1 131 #define PHY_ACCMD_CS1_BIT 17 132 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ 133 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ 134 #define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */ 135 #define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */ 136 #define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */ 137 #define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */ 138 #define PHY_ACADDRBDL_ADDR1_BIT 17 /* [17] ADDR1 delay line */ 139 #define PHY_VRFTRES_RXDIFFCAL_BIT 21 /* [24:21] */ 140 #define PHY_BYPASS_CK0_BIT 2 /* [2]ck_ioctl_DUTY_EN */ 141 #define PHY_BYPASS_CK1_BIT 3 /* [3]ck1_ioctl_DUTY_EN */ 142 #define PHY_ACIOCTL21_CK0_BIT 12 /* [15:12] */ 143 #define PHY_ACIOCTL21_CK1_BIT 28 /* [31:28] */ 144 #define PHY_ACIOCTL21_CTL0_BIT 10 /* [10] */ 145 #define PHY_ACIOCTL21_CTL1_BIT 26 /* [26] */ 146 #define PHY_DXNRDBOUND_RIGHT_BIT 1 /* [9:1] */ 147 #define PHY_DXNRDBOUND_LEFT_BIT 17 /* [25:17] */ 148 #define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */ 149 #define PHY_HRXDIFFCAL_EN_BIT 31 /* [31] */ 150 #define PHY_OSC_RPT_VLD 15 /* [15] */ 151 #define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */ 152 #define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */ 153 #define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */ 154 #define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */ 155 #define PHY_CFG_RX_AGE_COMPST_EN_BIT 31 /* Enable rdqs age compensation function */ 156 /* BDL register bit */ 157 #define PHY_BDL_DQ_BIT 1 158 #define PHY_BDL_DQ0_BIT 1 159 #define PHY_BDL_DQ1_BIT 9 160 #define PHY_BDL_DQ2_BIT 17 161 #define PHY_BDL_DQ3_BIT 25 162 #define PHY_RDM_BDL_BIT 1 163 #define PHY_RDQS_BDL_BIT 1 164 165 /* value */ 166 #define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */ 167 #define PHY_TRAINCTRL0_DTR_RANK0 0x0 /* Training Rank0. */ 168 #define PHY_TRAINCTRL0_DTR_RANK1 0x1 /* Training Rank1. */ 169 /* hw training item defined in PHYINITCTRL */ 170 #define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */ 171 #define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */ 172 #define PHY_PHYINITCTRL_PIC_TDQSST (1 << 29) /* TDQSS training Enable. */ 173 #define PHY_PHYINITCTRL_LP4_CHB_DIS (1 << 28) /* LPDDR4 channel-B disable. */ 174 #define PHY_PHYINITCTRL_LP4_CHA_DIS (1 << 27) /* LPDDR4 channel-A disable. */ 175 #define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */ 176 #define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */ 177 #define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */ 178 #define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */ 179 #define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */ 180 #define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */ 181 #define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */ 182 #define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */ 183 #define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */ 184 #define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */ 185 #define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */ 186 #define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */ 187 #define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */ 188 #define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */ 189 #define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */ 190 #define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */ 191 #define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */ 192 #define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */ 193 #define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */ 194 #define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */ 195 #define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */ 196 #define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */ 197 #define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */ 198 #define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */ 199 #define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */ 200 #define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */ 201 #define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */ 202 203 #define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST) 204 #define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST) 205 #define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN) 206 #define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN) 207 #define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN) 208 #define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN) 209 #define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC) 210 #define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \ 211 | PHY_PHYINITCTRL_GT_EN \ 212 | PHY_PHYINITCTRL_GDST_EN \ 213 | PHY_PHYINITCTRL_WL2_EN \ 214 | PHY_PHYINITCTRL_RDET_EN \ 215 | PHY_PHYINITCTRL_WDET_EN \ 216 | PHY_PHYINITCTRL_DVREFT_EN \ 217 | PHY_PHYINITCTRL_HVREFT_EN \ 218 | PHY_PHYINITCTRL_PIC_TDQSST) 219 #define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST) 220 221 /* RDQS range[0, 0x7f], middle value is 0x40, but it affected by 222 temperature, so middle value change to 0x30 */ 223 #define PHY_RDQS_MIDDLE_VAL 0x30 224 /* DQ range[0, 0x7f], middle value is 0x40, but it affected by 225 temperature, so middle value change to 0x30 */ 226 #define PHY_DQ_MIDDLE_VAL 0x30303030 227 #define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */ 228 #define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ 229 #define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */ 230 /* [5] two cycle on address or command.(2T timing) */ 231 #define PHY_DRAMCFG_MA2T 0x20 232 233 #define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */ 234 #define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */ 235 #define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */ 236 #define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */ 237 #define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */ 238 #define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */ 239 #define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */ 240 #define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ 241 #define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */ 242 243 #define PHY_DMSEL_SWAPDFIBYTE 0xf8ffffff /* [24:26] No Swap */ 244 245 /* AC_DDRPHY_GATED_BYPASS */ 246 #define PHY_CK_IOCTL_DUTY_EN 0x4 /* enable ck_ioctl_DUTY_EN_v */ 247 #define PHY_CK1_IOCTL_DUTY_EN 0x8 /* enable ck1_ioctl_DUTY_EN_v */ 248 /* CK AC_IOCTL22 */ 249 #ifndef DDR_DUTY_NUM 250 #define DDR_DUTY_NUM 13 /* CK duty number */ 251 #endif 252 #ifndef DDR_CK_NUM 253 #define DDR_CK_NUM 2 /* DDR CK number */ 254 #endif 255 #ifndef DDR_DUTY_CTL_NUM 256 #define DDR_DUTY_CTL_NUM 2 /* CK duty has two control direction */ 257 #endif 258 /* CK duty step. */ 259 #ifndef PHY_AC_IOCTL21_STEP 260 #define PHY_AC_IOCTL21_STEP 1 261 #endif 262 263 /* other */ 264 #define PHY_RDQSG_PHASE_STEP 2 /* gate training phase step. */ 265 #define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */ 266 #define PHY_DQ_BDL_LEVEL 128 /* [CUSTOM] DQ BDL range */ 267 #define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ 268 #define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */ 269 #define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */ 270 #define PHY_PCODE_MIN 0x14 271 #define PHY_PCODE_MAX 0x24 272 /** 273 * DDR_BDL_PHASE_REL Calculation Method: 274 * 1. Calculation How many picosecond to one phase. 275 * PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond 276 * WAVE : 1 cycle is 2 277 * RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps 278 * PHASE : 1 wave is 12 phase 279 * phase = (((PICOSECOND * WAVE) / RATE) / PHASE) 280 * = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 12) 281 * = 104.17 ps. 282 * 2. Calculation How many bdl to one phase. 283 * one BDL is 6 ps. 284 * result = phase/bdl = 104.17 / 6 = 17.36 approximately equal to 17 ~= 16 285 * 3. 16 = 1 << 4, so the relation is 4. 286 */ 287 #ifndef DDR_BDL_PHASE_TRANSFORM 288 /* [CUSTOM] one Phase equal how much BDL. 1 phase = 16 bdl */ 289 #define DDR_BDL_PHASE_TRANSFORM 16 290 #endif 291 #ifndef DDR_BDL_PHASE_REL 292 /* [CUSTOM] relation between BDL and Phase. 1 phase = 16 bdl, 16 = 1 << 4 */ 293 #define DDR_BDL_PHASE_REL 4 294 #endif 295 296 #define DDR_VARIABLE_DECLARE(var) \ 297 unsigned int var; 298 299 300 #define DDR_VREF_GET_HOST_MAX(rank, val) \ 301 do { \ 302 if (0 == rank) \ 303 val = PHY_VRFTRES_HVREF_MASK; \ 304 else \ 305 val = PHY_VRFTRES_RXDIFFCAL_MASK; \ 306 } while (0) 307 308 /* PHY t28 all byte use a same value */ 309 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ 310 do { \ 311 unsigned int hvreft; \ 312 if (0 == rank) { \ 313 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ 314 & (~PHY_VRFTRES_HVREF_MASK); \ 315 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ 316 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \ 317 } else { \ 318 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ 319 & (~(PHY_VRFTRES_RXDIFFCAL_MASK << PHY_VRFTRES_RXDIFFCAL_BIT)); \ 320 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ 321 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \ 322 } \ 323 } while (0) 324 325 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ 326 do { \ 327 if (0 == rank) { \ 328 val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ 329 & PHY_VRFTRES_HVREF_MASK; \ 330 } else { \ 331 val = (ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) >> PHY_VRFTRES_RXDIFFCAL_BIT) \ 332 & PHY_VRFTRES_RXDIFFCAL_MASK; \ 333 } \ 334 } while (0) 335 336 #define DDR_PHY_VREF_HOST_DISPLAY \ 337 {0, 0, DDR_PHY_HVREFT_STATUS(0, 0), 0, "Host Vref Byte0"}, \ 338 {0, 1, DDR_PHY_HVREFT_STATUS(0, 1), 0, "Host Vref Byte1"}, \ 339 {0, 2, DDR_PHY_HVREFT_STATUS(0, 2), 0, "Host Vref Byte2"}, \ 340 {0, 3, DDR_PHY_HVREFT_STATUS(0, 3), 0, "Host Vref Byte3"}, 341 342 #define DDR_PHY_VREF_HOST_DISPLAY_RANK1 \ 343 {1, 0, DDR_PHY_HVREFT_STATUS(1, 0), 0, "Host Vref Byte0"}, \ 344 {1, 1, DDR_PHY_HVREFT_STATUS(1, 1), 0, "Host Vref Byte1"}, \ 345 {1, 2, DDR_PHY_HVREFT_STATUS(1, 2), 0, "Host Vref Byte2"}, \ 346 {1, 3, DDR_PHY_HVREFT_STATUS(1, 3), 0, "Host Vref Byte3"}, 347 348 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ 349 do { \ 350 unsigned int _i; \ 351 for (_i = 0; _i < byte_num; _i++) { \ 352 DDR_INFO("[%x = %x] Host Vref Byte(%x)", \ 353 base_phy + DDR_PHY_HVREFT_STATUS(rank, _i), \ 354 ddr_read(base_phy \ 355 + DDR_PHY_HVREFT_STATUS(rank, _i)), _i); \ 356 } \ 357 } while (0) 358 359 /* DRAM vref operations */ 360 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ 361 do { \ 362 unsigned int dvrftctrl = \ 363 ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \ 364 unsigned int dvreft = ddr_read(base_phy \ 365 + DDR_PHY_DVREFT_STATUS(byte_index)) \ 366 & (~PHY_VRFTRES_DVREF_MASK); \ 367 ddr_write(dvrftctrl | PHY_DVRFTCTRL_PDAEN_EN, \ 368 base_phy + DDR_PHY_DVRFTCTRL); \ 369 ddr_write(dvreft | val, \ 370 base_phy + DDR_PHY_DVREFT_STATUS(byte_index)); \ 371 ddr_write(PHY_PHYINITCTRL_DVREFT_SYNC \ 372 | PHY_PHYINITCTRL_INIT_EN, \ 373 base_phy + DDR_PHY_PHYINITCTRL); \ 374 while (1) { \ 375 if (!(ddr_read(base_phy + DDR_PHY_PHYINITCTRL) \ 376 & PHY_PHYINITCTRL_INIT_EN)) \ 377 break; \ 378 } \ 379 ddr_write(dvrftctrl & (~PHY_DVRFTCTRL_PDAEN_EN), \ 380 base_phy + DDR_PHY_DVRFTCTRL); \ 381 } while (0) 382 383 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ 384 { \ 385 val = ddr_read(base_phy + DDR_PHY_DVREFT_STATUS(byte_index)) \ 386 & PHY_VRFTRES_DVREF_MASK; \ 387 } 388 389 #define DDR_PHY_VREF_DRAM_DISPLAY \ 390 {0, 0, DDR_PHY_DVREFT_STATUS(0), 0, "DRAM Vref Byte0"}, \ 391 {0, 1, DDR_PHY_DVREFT_STATUS(1), 0, "DRAM Vref Byte1"}, \ 392 {0, 2, DDR_PHY_DVREFT_STATUS(2), 0, "DRAM Vref Byte2"}, \ 393 {0, 3, DDR_PHY_DVREFT_STATUS(3), 0, "DRAM Vref Byte3"}, 394 395 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ 396 do { \ 397 unsigned int _i; \ 398 for (_i = 0; _i < byte_num; _i++) { \ 399 DDR_INFO("[%x = %x] DRAM Vref Byte(%x)", \ 400 base_phy + DDR_PHY_DVREFT_STATUS(_i), \ 401 ddr_read(base_phy \ 402 + DDR_PHY_DVREFT_STATUS(_i)), _i); \ 403 } \ 404 } while (0) 405 406 #define DDR_PHY_DCC_DISPLAY \ 407 {0, 0, DDR_PHY_ACIOCTL21, 0, "CK DUTY"}, 408 409 #define DDR_PHY_DCC_DISPLAY_CMD(base_phy) \ 410 do { \ 411 unsigned int val; \ 412 val = ddr_read(base_phy + DDR_PHY_ACIOCTL21); \ 413 val = ddr_read(base_phy + DDR_PHY_ACIOCTL21); \ 414 DDR_INFO("[%x = %x] DCC duty", \ 415 base_phy + DDR_PHY_ACIOCTL21, val); \ 416 } while (0) 417 418 #define DDR_PHY_ADDRPH_DISPLAY \ 419 {0, 0, DDR_PHY_ADDRPHBOUND, 0, "CA Phase"}, 420 421 #define DDR_PHY_ADDRBDL_DISPLAY \ 422 {0, 0, DDR_PHY_ACADDRBDL(0), 0, "CA BDL(0)"}, \ 423 {0, 0, DDR_PHY_ACADDRBDL(1), 0, "CA BDL(1)"}, \ 424 {0, 0, DDR_PHY_ACADDRBDL(2), 0, "CA BDL(2)"}, \ 425 {0, 0, DDR_PHY_ACADDRBDL(3), 0, "CA BDL(3)"}, \ 426 {0, 0, DDR_PHY_ACADDRBDL(4), 0, "CA BDL(4)"}, 427 428 #define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) \ 429 DDR_INFO("[%x = %x] CA Phase", \ 430 base_phy + DDR_PHY_ADDRPHBOUND, \ 431 ddr_read(base_phy + DDR_PHY_ADDRPHBOUND)); 432 433 #define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) \ 434 do { \ 435 unsigned int _i; \ 436 for (_i = 0; _i < DDR_PHY_CA_REG_MAX; _i++) { \ 437 DDR_INFO("[%x = %x] ACADDRBDL(%x)", \ 438 base_phy + DDR_PHY_ACADDRBDL(_i), \ 439 ddr_read(base_phy \ 440 + DDR_PHY_ACADDRBDL(_i)), _i); \ 441 } \ 442 } while (0) 443 444 /* PHY t28 DDR4 RDQS synchronize to RDM */ 445 #define DDR_PHY_RDQS_SYNC_RDM(cfg, val) \ 446 ddr_rdqs_sync(cfg, val) 447 448 /* dqs swap */ 449 #define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) \ 450 do { \ 451 swapdfibyte_en = \ 452 ddr_read(base_phy + DDR_PHY_DMSEL); \ 453 ddr_write(swapdfibyte_en & PHY_DMSEL_SWAPDFIBYTE, \ 454 base_phy + DDR_PHY_DMSEL); \ 455 } while (0) 456 457 #define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) \ 458 ddr_write(swapdfibyte_en, base_phy + DDR_PHY_DMSEL); 459 460 #define DDR_PHY_SWITCH_RANK(base_phy, val) \ 461 do { \ 462 ddr_write((ddr_read(base_phy + DDR_PHY_TRAINCTRL0) & (~PHY_TRAINCTRL0_MASK)) | val, base_phy + DDR_PHY_TRAINCTRL0); \ 463 ddr_write((ddr_read(base_phy + DDR_PHY_HVRFTCTRL) & (~(0x1 << PHY_HRXDIFFCAL_EN_BIT))) | (val << PHY_HRXDIFFCAL_EN_BIT), base_phy + DDR_PHY_HVRFTCTRL); \ 464 } while (0) 465 466 /* Define the union U_PHY_CATCONFIG */ 467 union U_PHY_CATCONFIG { 468 /* Define the struct bits */ 469 struct { 470 unsigned int ca_samp_num_bdl:4; /* [3:0] */ 471 unsigned int ca_samp_num_ph:4; /* [7:4] */ 472 unsigned int ca_trysamp_num:4; /* [11:8] */ 473 unsigned int cat_rb_backtap:4; /* [15:12] */ 474 unsigned int reserved:1; /* [16] */ 475 unsigned int cat_openeye_en:1; /* [17] */ 476 unsigned int cat_cat_phydq_sel:1; /* [18] */ 477 unsigned int cat_restore_en:1; /* [19] */ 478 unsigned int cat_lb_backtap:4; /* [23:20] */ 479 unsigned int sw_cat_mrw42:1; /* [24] */ 480 unsigned int sw_cat_mrw48:1; /* [25] */ 481 unsigned int sw_cat_mrw41:1; /* [26] */ 482 unsigned int sw_cat_strobe:1; /* [27] */ 483 unsigned int sw_cat_cke_high:1; /* [28] */ 484 unsigned int sw_cat_cke_low:1; /* [29] */ 485 unsigned int sw_cat_dqvalid:1; /* [30] */ 486 unsigned int sw_cat_en:1; /* [31] */ 487 } bits; 488 489 /* Define an unsigned member */ 490 unsigned int u32; 491 }; 492 493 /* Define the union U_PHY_ADDRPHBOUND */ 494 union U_PHY_ADDRPHBOUND { 495 /* Define the struct bits */ 496 struct { 497 unsigned int addrph_a_right:5; /* [4:0] */ 498 unsigned int reserved0:3; /* [7:5] */ 499 unsigned int addrph_a_left:5; /* [12:8] */ 500 unsigned int reserved1:3; /* [15:13] */ 501 unsigned int addrph_a:5; /* [20:16] */ 502 unsigned int reserved2:3; /* [23:21] */ 503 unsigned int addrph_a_ori:5; /* [28:24] */ 504 unsigned int reserved3:3; /* [31:29] */ 505 } bits; 506 507 /* Define an unsigned member */ 508 unsigned int u32; 509 }; 510