1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 18 */ 19 20 /* register offset address */ 21 /* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */ 22 /* control the initialization of the PHY */ 23 #define DDR_PHY_PHYINITCTRL 0x4 24 #define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error*/ 25 #define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */ 26 #define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */ 27 #define DDR_PHY_TRAINCTRL0 0x48 /* hw training control */ 28 #define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */ 29 #define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */ 30 /* update delay setting in registers to PHY */ 31 #define DDR_PHY_MISC 0x70 32 #define DDR_PHY_DMSEL 0x84 /* DM Swap Selection */ 33 #define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */ 34 /* issue one DQS pulse from PHY to DRAM */ 35 #define DDR_PHY_SWTWLDQS 0xa4 36 #define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/ 37 /* Host vref. [5:0]range [17:12]refsel */ 38 #define DDR_PHY_PHYRSCTRL 0xB0 /* PHY Register Slice Contrl */ 39 #define DDR_PHY_IOCTL2 0xB4 40 #define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */ 41 #define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */ 42 #define DDR_PHY_ACADDRBDL(n) (0x140 + ((n) << 2)) 43 #define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */ 44 #define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */ 45 #define DDR_PHY_CATSWAPINDEX 0x01B8 /* CA SWAP index register */ 46 #define DDR_PHY_CATSWAPSEL 0x01BC /* CA SWAP select register*/ 47 #define DDR_PHY_CATCONFIG 0x1C8 /* CA Training Configuration */ 48 #define DDR_PHY_PHYDQRESULT 0x1D0 /* SW CA Training DQ result from PHY */ 49 #define DDR_PHY_ADDRPHBOUND 0x1D4 /* CA Training addr phase boundary */ 50 #define DDR_PHY_SWCATPATTERN_P 0x1D8 /* pattern for positive CK edge */ 51 #define DDR_PHY_SWCATPATTERN_N 0x1DC /* pattern for negative CK edge */ 52 /* AC command bit delay line setting */ 53 #define DDR_PHY_ACCMDBDL2 0x128 54 55 /* WR DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line 56 on write path */ 57 #define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + ((m) << 10) + ((n) << 7)) 58 /* WR DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] */ 59 #define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + ((m) << 10) + ((n) << 7)) 60 /* WR DM [6:0] the delay value of the bit delay line on DQM */ 61 #define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + ((m) << 10) + ((n) << 7)) 62 /* RD DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line 63 on read path */ 64 #define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7)) 65 /* RD DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line 66 on read path */ 67 #define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7)) 68 /* [6:0]RD DM*/ 69 #define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7)) 70 71 72 /* [CUSTOM] */ 73 #define DDR_PHY_DXNOEBDL(m, n) (0x228 + ((m) << 10) + ((n) << 7)) 74 /* [8:0] rdqs_bdl [24:16]rdqs_cyc. 75 phase shift of the Read DQS to create 90 degree delays*/ 76 #define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7)) 77 /* [6:0] the delay value of delay applied on WDQS for write leveling */ 78 #define DDR_PHY_DXWDQSDLY(m, n) (0x230 + ((m) << 10) + ((n) << 7)) 79 /* WR DQ phase BIT 12:8 */ 80 #define DDR_PHY_DXNWDQDLY(m, n) (0x234 + ((m) << 10) + ((n) << 7)) 81 /* [CUSTOM] rddqs gating*/ 82 #define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7)) 83 /* read boundary right 8:0 left 24:16 */ 84 #define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7)) 85 /* write boundary right 4:0 left 20:16 */ 86 #define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7)) 87 /* [5:0] DRAM VREF(DQ) training result */ 88 #define DDR_PHY_DVREFT_STATUS(n) (0x270 + ((n) << 7)) 89 /* [4:0] Host PHY VREF(DQ) training result */ 90 #define DDR_PHY_HVREFT_STATUS(m, n) (0x274 + ((m) << 10) + ((n) << 7)) 91 92 /* DDRPHY AC static register */ 93 #define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */ 94 #define DDR_PHY_ACPHYCTL4 0x1064 /* AC block PHY control register*/ 95 #define DDR_PHY_ACPHYCTL7 0x1070 96 97 #define DDR_VREF_HOST_VAL_MAX (0x1f) /* 78.75%*VDDIO */ 98 #define DDR_VREF_HOST_VAL_MIN (0x0) /* 40.00%*VDDIO */ 99 100 /* register mask */ 101 #define PHY_BDL_MASK 0x7f /* [6:0] */ 102 #define PHY_WDQS_PHASE_MASK 0xf /* [11:8] */ 103 #define PHY_RDQS_BDL_MASK 0x1ff /* [CUSTOM] [8:0] rdqsbdl*/ 104 #define PHY_RDQSG_PHASE_MASK 0x3f /* [14:9] rdqsgphase */ 105 #define PHY_RDM_BDL_MASK 0x7f /* [6:0] */ 106 /* hardware gate training result */ 107 #define PHY_INITSTATUS_GT_MASK 0x20 108 #define PHY_SWTRLT_WL_MASK 0xf 109 #define PHY_SWTRLT_GATE_MASK 0xf 110 #define PHY_WDQ_PHASE_MASK 0x1f 111 #define PHY_PHYINITCTRL_MASK 0x1 /* [15:0] all stat */ 112 /* Read Data Eye Calibration Error */ 113 #define PHY_PHYINITSTATUS_RDET_ERR 0x100 114 #define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */ 115 #define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */ 116 #define PHY_VRFTRES_DVREF_MASK 0x3f /* [5:0] */ 117 #define PHY_VRFTRES_HVREF_MASK 0x1f /* [4:0] */ 118 #define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */ 119 #define PHY_ADDRPH_MASK 0x1f /* [20:16] */ 120 #define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */ 121 #define PHY_CATSWAPSEL_BIT_MASK 0xff 122 #define PHY_CAT_PATTERN_MASK 0x3ff 123 #define PHY_TRAINCTRL0_MASK 0xf /* [3:0] */ 124 #define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */ 125 #define PHY_OSC_START_MASK 0x1 /* [0] */ 126 #define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */ 127 #define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */ 128 #define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */ 129 #define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */ 130 131 /* register bit */ 132 #define PHY_MISC_UPDATE_BIT 19 /* [CUSTOM] delay config update bit */ 133 #define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */ 134 #define PHY_RDQSG_PHASE_BIT 9 /* [CUSTOM] */ 135 #define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */ 136 #define PHY_WDQS_PHASE_BIT 8 137 #define PHY_WDQS_BDL_BIT 0 138 #define PHY_WDQ_PHASE_BIT 8 139 #define PHY_WDM_BDL_BIT 0 140 /* [22:16] Write DQS Output Enable Delay Control */ 141 #define PHY_WDQSOE_BDL_BIT 16 142 #define PHY_OEN_BDL_BIT 0 143 /* Mode Register 1. Defines the MR3/MR9 of the mode register */ 144 #define PHY_MODEREG01_MR1_BIT 16 145 /* Bit delay line setting of CS1 */ 146 #define PHY_ACCMD_CS0_BIT 0 147 #define PHY_ACCMD_CS1_BIT 16 148 #define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */ 149 #define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */ 150 #define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */ 151 #define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */ 152 #define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */ 153 #define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */ 154 #define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */ 155 #define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */ 156 #define PHY_OSC_RPT_VLD 15 /* [15] */ 157 #define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */ 158 #define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */ 159 #define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */ 160 #define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */ 161 #define PHY_CFG_RX_AGE_COMPST_EN_BIT 31 /* Enable rdqs age compensation function */ 162 /* BDL register bit */ 163 #define PHY_BDL_DQ_BIT 0 164 #define PHY_BDL_DQ0_BIT 0 165 #define PHY_BDL_DQ1_BIT 8 166 #define PHY_BDL_DQ2_BIT 16 167 #define PHY_BDL_DQ3_BIT 24 168 #define PHY_RDM_BDL_BIT 0 169 #define PHY_RDQS_BDL_BIT 0 170 171 /* value */ 172 #define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */ 173 /* hw training item defined in PHYINITCTRL */ 174 #define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */ 175 #define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */ 176 #define PHY_PHYINITCTRL_PIC_TDQSST (1 << 28) /* TDQSS training Enable. */ 177 #define PHY_PHYINITCTRL_CFG_LPBK_COMPST_EN (1 << 27) /* RDQS/CK loopback delay compensate enable. */ 178 #define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */ 179 #define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */ 180 #define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */ 181 #define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */ 182 #define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */ 183 #define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */ 184 #define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */ 185 #define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */ 186 #define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */ 187 #define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */ 188 #define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */ 189 #define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */ 190 #define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */ 191 #define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */ 192 #define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */ 193 #define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */ 194 #define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */ 195 #define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */ 196 #define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */ 197 #define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */ 198 #define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */ 199 #define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */ 200 #define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */ 201 #define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */ 202 #define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */ 203 #define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */ 204 #define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */ 205 206 #define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST) 207 #define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST) 208 #define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN) 209 #define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN) 210 #define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN) 211 #define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN) 212 #define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC) 213 #define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \ 214 | PHY_PHYINITCTRL_GT_EN \ 215 | PHY_PHYINITCTRL_GDST_EN \ 216 | PHY_PHYINITCTRL_WL2_EN \ 217 | PHY_PHYINITCTRL_RDET_EN \ 218 | PHY_PHYINITCTRL_WDET_EN \ 219 | PHY_PHYINITCTRL_DVREFT_EN \ 220 | PHY_PHYINITCTRL_HVREFT_EN \ 221 | PHY_PHYINITCTRL_PIC_TDQSST) 222 #define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST) 223 224 /* RDQS range[0, 0x7f], middle value is 0x40, but it affected by 225 temperature, so middle value change to 0x30 */ 226 #define PHY_RDQS_MIDDLE_VAL 0x30 227 /* DQ range[0, 0x7f], middle value is 0x40, but it affected by 228 temperature, so middle value change to 0x30 */ 229 #define PHY_DQ_MIDDLE_VAL 0x30303030 230 #define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */ 231 #define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */ 232 #define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */ 233 /* [5] two cycle on address or command.(2T timing) */ 234 #define PHY_DRAMCFG_MA2T 0x20 235 236 #define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */ 237 #define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */ 238 #define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */ 239 #define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */ 240 #define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */ 241 #define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */ 242 #define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */ 243 #define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */ 244 #define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */ 245 246 #define PHY_DMSEL_SWAPDFIBYTE 0xf8ffffff /* [24:26] No Swap */ 247 /* other */ 248 #define PHY_RDQSG_PHASE_STEP 2 /* gate training phase step. */ 249 #define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */ 250 #define PHY_DQ_BDL_LEVEL 128 /* [CUSTOM] DQ BDL range */ 251 #define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */ 252 #define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */ 253 #define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */ 254 #define PHY_PCODE_MIN 0x14 255 #define PHY_PCODE_MAX 0x24 256 /** 257 * DDR_BDL_PHASE_REL Calculation Method: 258 * 1. Calculation How many picosecond to one phase. 259 * PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond 260 * WAVE : 1 cycle is 2 261 * RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps 262 * PHASE : 1 wave is 12 phase 263 * phase = (((PICOSECOND * WAVE) / RATE) / PHASE) 264 * = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 12) 265 * = 104.17 ps. 266 * 2. Calculation How many bdl to one phase. 267 * one BDL is 6 ps. 268 * result = phase/bdl = 104.17 / 6 = 17.36 approximately equal to 17 ~= 16 269 * 3. 16 = 1 << 4, so the relation is 4. 270 */ 271 #ifndef DDR_BDL_PHASE_TRANSFORM 272 /* [CUSTOM] one Phase equal how much BDL. 1 phase = 16 bdl */ 273 #define DDR_BDL_PHASE_TRANSFORM 16 274 #endif 275 #ifndef DDR_BDL_PHASE_REL 276 /* [CUSTOM] relation between BDL and Phase. 1 phase = 16 bdl, 16 = 1 << 4 */ 277 #define DDR_BDL_PHASE_REL 4 278 #endif 279 280 #define DDR_VARIABLE_DECLARE(var) \ 281 unsigned int var; 282 283 #define DDR_VREF_GET_HOST_MAX(rank, val) \ 284 do { \ 285 if (0 == rank) \ 286 val = PHY_VRFTRES_HVREF_MASK; \ 287 else \ 288 val = PHY_VRFTRES_RXDIFFCAL_MASK; \ 289 } while (0) 290 291 /* PHY t28 all byte use a same value */ 292 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \ 293 do { \ 294 unsigned int hvreft; \ 295 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ 296 & (~PHY_VRFTRES_HVREF_MASK); \ 297 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \ 298 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \ 299 } while (0) 300 301 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \ 302 do { \ 303 val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \ 304 & PHY_VRFTRES_HVREF_MASK; \ 305 } while (0) 306 307 #define DDR_PHY_VREF_HOST_DISPLAY \ 308 {0, 0, DDR_PHY_HVREFT_STATUS(0, 0), 0, "Host Vref Byte0"}, \ 309 {0, 1, DDR_PHY_HVREFT_STATUS(0, 1), 0, "Host Vref Byte1"}, \ 310 {0, 2, DDR_PHY_HVREFT_STATUS(0, 2), 0, "Host Vref Byte2"}, \ 311 {0, 3, DDR_PHY_HVREFT_STATUS(0, 3), 0, "Host Vref Byte3"}, 312 313 #define DDR_PHY_VREF_HOST_DISPLAY_RANK1 \ 314 {1, 0, DDR_PHY_HVREFT_STATUS(1, 0), 0, "Host Vref Byte0"}, \ 315 {1, 1, DDR_PHY_HVREFT_STATUS(1, 1), 0, "Host Vref Byte1"}, \ 316 {1, 2, DDR_PHY_HVREFT_STATUS(1, 2), 0, "Host Vref Byte2"}, \ 317 {1, 3, DDR_PHY_HVREFT_STATUS(1, 3), 0, "Host Vref Byte3"}, 318 319 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \ 320 do { \ 321 unsigned int _i; \ 322 for (_i = 0; _i < byte_num; _i++) { \ 323 DDR_INFO("[%x = %x] Host Vref Byte(%x)", \ 324 base_phy + DDR_PHY_HVREFT_STATUS(rank, _i), \ 325 ddr_read(base_phy \ 326 + DDR_PHY_HVREFT_STATUS(rank, _i)), _i); \ 327 } \ 328 } while (0) 329 330 /* DRAM vref operations */ 331 #define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \ 332 do { \ 333 unsigned int dvrftctrl = \ 334 ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \ 335 unsigned int dvreft = ddr_read(base_phy \ 336 + DDR_PHY_DVREFT_STATUS(byte_index)) \ 337 & (~PHY_VRFTRES_DVREF_MASK); \ 338 ddr_write(dvrftctrl | PHY_DVRFTCTRL_PDAEN_EN, \ 339 base_phy + DDR_PHY_DVRFTCTRL); \ 340 ddr_write(dvreft | val, \ 341 base_phy + DDR_PHY_DVREFT_STATUS(byte_index)); \ 342 ddr_write(PHY_PHYINITCTRL_DVREFT_SYNC \ 343 | PHY_PHYINITCTRL_INIT_EN, \ 344 base_phy + DDR_PHY_PHYINITCTRL); \ 345 while (1) { \ 346 if (!(ddr_read(base_phy + DDR_PHY_PHYINITCTRL) \ 347 & PHY_PHYINITCTRL_INIT_EN)) \ 348 break; \ 349 } \ 350 ddr_write(dvrftctrl & (~PHY_DVRFTCTRL_PDAEN_EN), \ 351 base_phy + DDR_PHY_DVRFTCTRL); \ 352 } while (0) 353 354 #define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \ 355 { \ 356 val = ddr_read(base_phy + DDR_PHY_DVREFT_STATUS(byte_index)) \ 357 & PHY_VRFTRES_DVREF_MASK; \ 358 } 359 360 #define DDR_PHY_VREF_DRAM_DISPLAY \ 361 {0, 0, DDR_PHY_DVREFT_STATUS(0), 0, "DRAM Vref Byte0"}, \ 362 {0, 1, DDR_PHY_DVREFT_STATUS(1), 0, "DRAM Vref Byte1"}, \ 363 {0, 2, DDR_PHY_DVREFT_STATUS(2), 0, "DRAM Vref Byte2"}, \ 364 {0, 3, DDR_PHY_DVREFT_STATUS(3), 0, "DRAM Vref Byte3"}, 365 366 #define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \ 367 do { \ 368 unsigned int _i; \ 369 for (_i = 0; _i < byte_num; _i++) { \ 370 DDR_INFO("[%x = %x] DRAM Vref Byte(%x)", \ 371 base_phy + DDR_PHY_DVREFT_STATUS(_i), \ 372 ddr_read(base_phy \ 373 + DDR_PHY_DVREFT_STATUS(_i)), _i); \ 374 } \ 375 } while (0) 376 377 /* phy t28 not support DCC training */ 378 #define DDR_PHY_DCC_DISPLAY 379 #define DDR_PHY_DCC_DISPLAY_CMD(base_phy) 380 381 /* lowpower ddr ca operations */ 382 #define DDR_PHY_ADDRPH_DISPLAY \ 383 {0, 0, DDR_PHY_ADDRPHBOUND, 0, "CA Phase"}, 384 385 #define DDR_PHY_ADDRBDL_DISPLAY \ 386 {0, 0, DDR_PHY_ACADDRBDL(0), 0, "CA BDL(0)"}, \ 387 {0, 0, DDR_PHY_ACADDRBDL(1), 0, "CA BDL(1)"}, \ 388 {0, 0, DDR_PHY_ACADDRBDL(2), 0, "CA BDL(2)"}, \ 389 {0, 0, DDR_PHY_ACADDRBDL(3), 0, "CA BDL(3)"}, \ 390 {0, 0, DDR_PHY_ACADDRBDL(4), 0, "CA BDL(4)"}, 391 392 #define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) \ 393 DDR_INFO("[%x = %x] CA Phase", \ 394 base_phy + DDR_PHY_ADDRPHBOUND, \ 395 ddr_read(base_phy + DDR_PHY_ADDRPHBOUND)); 396 397 #define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) \ 398 do { \ 399 unsigned int _i; \ 400 for (_i = 0; _i < DDR_PHY_CA_REG_MAX; _i++) { \ 401 DDR_INFO("[%x = %x] ACADDRBDL(%x)", \ 402 base_phy + DDR_PHY_ACADDRBDL(_i), \ 403 ddr_read(base_phy \ 404 + DDR_PHY_ACADDRBDL(_i)), _i); \ 405 } \ 406 } while (0) 407 408 /* PHY t28 DDR4 RDQS synchronize to RDM */ 409 #define DDR_PHY_RDQS_SYNC_RDM(cfg, val) \ 410 ddr_rdqs_sync(cfg, val) 411 412 /* dqs swap */ 413 #define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) \ 414 do { \ 415 swapdfibyte_en = \ 416 ddr_read(base_phy + DDR_PHY_DMSEL); \ 417 ddr_write(swapdfibyte_en & PHY_DMSEL_SWAPDFIBYTE, \ 418 base_phy + DDR_PHY_DMSEL); \ 419 } while (0) 420 421 #define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) \ 422 ddr_write(swapdfibyte_en, base_phy + DDR_PHY_DMSEL); 423 424 425 #define DDR_PHY_SWITCH_RANK(base_phy, val) \ 426 do { \ 427 ddr_write((ddr_read(base_phy + DDR_PHY_TRAINCTRL0) & (~PHY_TRAINCTRL0_MASK)) | val, base_phy + DDR_PHY_TRAINCTRL0); \ 428 } while (0) 429 430 /* Define the union U_PHY_CATCONFIG */ 431 union U_PHY_CATCONFIG { 432 /* Define the struct bits */ 433 struct { 434 unsigned int ca_samp_num_bdl:4; /* [3:0] */ 435 unsigned int ca_samp_num_ph:4; /* [7:4] */ 436 unsigned int ca_trysamp_num:4; /* [11:8] */ 437 unsigned int cat_rb_backtap:4; /* [15:12] */ 438 unsigned int reserved:1; /* [16] */ 439 unsigned int cat_openeye_en:1; /* [17] */ 440 unsigned int cat_cat_phydq_sel:1; /* [18] */ 441 unsigned int cat_restore_en:1; /* [19] */ 442 unsigned int cat_lb_backtap:4; /* [23:20] */ 443 unsigned int sw_cat_mrw42:1; /* [24] */ 444 unsigned int sw_cat_mrw48:1; /* [25] */ 445 unsigned int sw_cat_mrw41:1; /* [26] */ 446 unsigned int sw_cat_strobe:1; /* [27] */ 447 unsigned int sw_cat_cke_high:1; /* [28] */ 448 unsigned int sw_cat_cke_low:1; /* [29] */ 449 unsigned int sw_cat_dqvalid:1; /* [30] */ 450 unsigned int sw_cat_en:1; /* [31] */ 451 } bits; 452 453 /* Define an unsigned member */ 454 unsigned int u32; 455 }; 456 457 /* Define the union U_PHY_ADDRPHBOUND */ 458 union U_PHY_ADDRPHBOUND { 459 /* Define the struct bits */ 460 struct { 461 unsigned int addrph_a_right:5; /* [4:0] */ 462 unsigned int reserved0:3; /* [7:5] */ 463 unsigned int addrph_a_left:5; /* [12:8] */ 464 unsigned int reserved1:3; /* [15:13] */ 465 unsigned int addrph_a:5; /* [20:16] */ 466 unsigned int reserved2:3; /* [23:21] */ 467 unsigned int addrph_a_ori:5; /* [28:24] */ 468 unsigned int reserved3:3; /* [31:29] */ 469 } bits; 470 471 /* Define an unsigned member */ 472 unsigned int u32; 473 }; 474