1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #ifndef DDR_TRAINING_CUSTOM_H 20 #define DDR_TRAINING_CUSTOM_H 21 22 /* config DDRC, PHY, DDRT typte */ 23 #define DDR_DDRC_V520_CONFIG 24 #define DDR_PHY_T12_V101_CONFIG 25 #define DDR_DDRT_T12_V100_CONFIG 26 27 /* config special item */ 28 /* s40/t28/t16 not support dcc training */ 29 #define DDR_VREF_TRAINING_CONFIG 30 #define DDR_VREF_WITHOUT_BDL_CONFIG 31 #define DDR_DCC_TRAINING_CONFIG 32 33 #define DDR_WL_TRAINING_DISABLE 34 #define DDR_GATE_TRAINING_DISABLE 35 #define DDR_TRAINING_UART_DISABLE 36 37 /* Disable write dm 38 #define DDR_WRITE_DM_DISABLE */ 39 #define DDR_PHY_NUM 1 /* phy number */ 40 41 #define DDR_DMC_PER_PHY_MAX 2 /* dmc number per phy max */ 42 43 #define DDR_AXI_SWITCH_NUM 4 /* ddr training axi switch number */ 44 45 /* config DDRC, PHY, DDRT base address */ 46 /* [CUSTOM] DDR PHY0 base register */ 47 #define DDR_REG_BASE_PHY0 0x0460c000 48 /* [CUSTOM] DDR PHY1 base register 49 #define DDR_REG_BASE_PHY1 0x0460e000 */ 50 /* [CUSTOM] DDR DMC0 base register */ 51 #define DDR_REG_BASE_DMC0 0x04608000 52 /* [CUSTOM] DDR DMC1 base register */ 53 #define DDR_REG_BASE_DMC1 0x04609000 54 55 #ifdef DDR_REG_BASE_PHY1 56 /* [CUSTOM] DDR DMC2 base register */ 57 #define DDR_REG_BASE_DMC2 0x0460a000 58 /* [CUSTOM] DDR DMC3 base register */ 59 #define DDR_REG_BASE_DMC3 0x0460b000 60 #endif 61 62 /* [CUSTOM] DDR DDRT base register */ 63 #define DDR_REG_BASE_DDRT 0x04620000 64 /* [CUSTOM] DDR training item system control */ 65 #define DDR_REG_BASE_SYSCTRL 0x04520000 66 #define DDR_REG_BASE_AXI 0x04600000 67 /* Serial Configuration */ 68 #define DDR_REG_BASE_UART0 0x04540000 69 70 /* config offset address */ 71 /* Assume sysctrl offset address for DDR training as follows, 72 if not please define. */ 73 /* [CUSTOM] ddrt reversed data */ 74 #define SYSCTRL_DDRT_PATTERN 0xa8 75 /* [CUSTOM] PHY2 ddrt reversed data 76 #define SYSCTRL_DDRT_PATTERN_SEC 0xac */ 77 /* [CUSTOM] ddr training item */ 78 #define SYSCTRL_DDR_TRAINING_CFG 0xa0 79 #define SYSCTRL_DDR_TRAINING_CFG_SEC 0xa4 80 /* [CUSTOM] ddr training version flag */ 81 #define SYSCTRL_DDR_TRAINING_VERSION_FLAG 0xac 82 /* [CUSTOM] ddr training stat */ 83 #define SYSCTRL_DDR_TRAINING_STAT 0x9c 84 85 /* [CUSTOM] ddr hw training item */ 86 #define SYSCTRL_DDR_HW_PHY0_RANK0 0x90 87 #define SYSCTRL_DDR_HW_PHY0_RANK1 0x94 88 #if 0 89 /* PHY1 hw training item */ 90 #define SYSCTRL_DDR_HW_PHY1_RANK0 0x98 91 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c 92 #endif 93 94 /* config other special */ 95 /* [CUSTOM] DDR training start address. MEM_BASE_DDR */ 96 #define DDRT_CFG_BASE_ADDR 0x20000000 97 /* [CUSTOM] SRAM start address. 98 NOTE: Makefile will parse it, plase define it as Hex. eg: 0xFFFF0C00 */ 99 #define DDR_TRAINING_RUN_STACK 0x04200c00 100 #define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask) \ 101 ddr_training_save_reg_custom(relate_reg, mask) 102 103 #define DDR_TRAINING_RESTORE_REG_FUNC(relate_reg) \ 104 ddr_training_restore_reg_custom(relate_reg) 105 106 void ddr_training_save_reg_custom(void *relate_reg, unsigned int mask); 107 void ddr_training_restore_reg_custom(void *relate_reg); 108 #endif /* DDR_TRAINING_CUSTOM_H */ 109