1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #ifndef DDR_TRAINING_CUSTOM_H 20 #define DDR_TRAINING_CUSTOM_H 21 22 /* config DDRC, PHY, DDRT typte */ 23 #define DDR_DDRC_V520_CONFIG 24 #define DDR_PHY_S28_V300_CONFIG 25 #define DDR_DDRT_V2_0_SHF0_CONFIG 26 27 /* config special item */ 28 /* s40/t28/t16 not support dcc training */ 29 #define DDR_VREF_TRAINING_CONFIG 30 #define DDR_VREF_WITHOUT_BDL_CONFIG 31 32 #define DDR_WL_TRAINING_DISABLE 33 #define DDR_GATE_TRAINING_DISABLE 34 #define DDR_TRAINING_UART_DISABLE 35 36 #define DDR_PHY_NUM 2 /* phy number */ 37 38 #define DDR_DMC_PER_PHY_MAX 2 /* dmc number per phy max */ 39 40 /* config DDRC, PHY, DDRT base address */ 41 /* [CUSTOM] DDR DMC0 base register */ 42 #define DDR_REG_BASE_DMC0 0x11138000 43 /* [CUSTOM] DDR DMC1 base register */ 44 #define DDR_REG_BASE_DMC1 0x11139000 45 /* [CUSTOM] DDR DMC2 base register */ 46 #define DDR_REG_BASE_DMC2 0x1113a000 47 /* [CUSTOM] DDR DMC3 base register */ 48 #define DDR_REG_BASE_DMC3 0x1113b000 49 /* [CUSTOM] DDR PHY0 base register */ 50 #define DDR_REG_BASE_PHY0 0x1113c000 51 /* [CUSTOM] DDR PHY1 base register */ 52 #define DDR_REG_BASE_PHY1 0x1113e000 53 /* [CUSTOM] DDR DDRT base register, ddrt1:0x1ff30000 */ 54 #define DDR_REG_BASE_DDRT 0x11140000 55 /* [CUSTOM] DDR training item system control */ 56 #define DDR_REG_BASE_SYSCTRL 0x11020000 57 #define DDR_REG_BASE_AXI 0x11130000 58 59 /* Serial Configuration*/ 60 #define DDR_REG_BASE_UART0 0x11040000 61 62 /* config offset address */ 63 /* Assume sysctrl offset address for DDR training as follows, 64 if not please define. */ 65 /* [CUSTOM] PHY0 ddrt reversed data */ 66 #define SYSCTRL_DDRT_PATTERN 0xa8 67 /* [CUSTOM] PHY2 ddrt reversed data */ 68 #define SYSCTRL_DDRT_PATTERN_SEC 0xac 69 /* [CUSTOM] rank0 ddr sw training item */ 70 #define SYSCTRL_DDR_TRAINING_CFG 0xa0 71 /* [CUSTOM] rank1 ddr sw training item */ 72 #define SYSCTRL_DDR_TRAINING_CFG_SEC 0xa4 73 /* [CUSTOM] ddr training version flag */ 74 #define SYSCTRL_DDR_TRAINING_VERSION_FLAG 0xb4 75 /* [CUSTOM] ddr training stat */ 76 #define SYSCTRL_DDR_TRAINING_STAT 0xb0 77 78 /* [CUSTOM] ddr hw training item */ 79 #define SYSCTRL_DDR_HW_PHY0_RANK0 0x90 80 #define SYSCTRL_DDR_HW_PHY0_RANK1 0x94 81 #define SYSCTRL_DDR_HW_PHY1_RANK0 0x98 82 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c 83 84 /* config other special */ 85 /* [CUSTOM] DDR training start address. MEM_BASE_DDR*/ 86 #define DDRT_CFG_BASE_ADDR 0x40000000 87 /* [CUSTOM] SRAM start address. 88 NOTE: Makefile will parse it, plase define it as Hex. eg: 0xFFFF0C00 */ 89 #define DDR_TRAINING_RUN_STACK 0x04010c00 90 91 #define DDR_RELATE_REG_DECLARE 92 #define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask) \ 93 ddr_training_save_reg_custom(relate_reg, mask) 94 95 #define DDR_TRAINING_RESTORE_REG_FUNC(relate_reg) \ 96 ddr_training_restore_reg_custom(relate_reg) 97 98 #define ddr_boot_cmd_save_func(relate_reg) \ 99 ddr_boot_cmd_save(relate_reg) 100 101 #define ddr_boot_cmd_restore_func(relate_reg) \ 102 ddr_boot_cmd_restore(relate_reg) 103 104 struct tr_custom_reg { 105 unsigned int ddrt_clk_reg; 106 unsigned int phy0_age_compst_en; 107 unsigned int phy1_age_compst_en; 108 unsigned int ddr_ctrl; 109 }; 110 111 void ddr_training_save_reg_custom(void *relate_reg, unsigned int mask); 112 void ddr_training_restore_reg_custom(void *relate_reg); 113 void ddr_boot_cmd_save(void *relate_reg); 114 void ddr_boot_cmd_restore(void *relate_reg); 115 int ddr_get_cksel(void); 116 #endif /* DDR_TRAINING_CUSTOM_H */ 117