1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * Keith Outwater, keith_outwater@mvis.com
6 *
7 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
8 */
9
10 /*
11 * Configuration support for Xilinx Virtex2 devices. Based
12 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
13 */
14
15 #include <common.h>
16 #include <console.h>
17 #include <virtex2.h>
18
19 #if 0
20 #define FPGA_DEBUG
21 #endif
22
23 #ifdef FPGA_DEBUG
24 #define PRINTF(fmt, args...) printf(fmt, ##args)
25 #else
26 #define PRINTF(fmt, args...)
27 #endif
28
29 /*
30 * If the SelectMap interface can be overrun by the processor, define
31 * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
32 * configuration file and add board-specific support for checking BUSY status.
33 * By default, assume that the SelectMap interface cannot be overrun.
34 */
35 #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
36 #undef CONFIG_SYS_FPGA_CHECK_BUSY
37 #endif
38
39 #ifndef CONFIG_FPGA_DELAY
40 #define CONFIG_FPGA_DELAY()
41 #endif
42
43 #ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
44 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
45 #endif
46
47 /*
48 * Don't allow config cycle to be interrupted
49 */
50 #ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
51 #undef CONFIG_SYS_FPGA_CHECK_CTRLC
52 #endif
53
54 /*
55 * Check for errors during configuration by default
56 */
57 #ifndef CONFIG_SYS_FPGA_CHECK_ERROR
58 #define CONFIG_SYS_FPGA_CHECK_ERROR
59 #endif
60
61 /*
62 * The default timeout in mS for INIT_B to deassert after PROG_B has
63 * been deasserted. Per the latest Virtex II Handbook (page 347), the
64 * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
65 * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
66 * which yields 11.44 mS. So let's make it bigger in order to handle
67 * an XC2V1000, if anyone can ever get ahold of one.
68 */
69 #ifndef CONFIG_SYS_FPGA_WAIT_INIT
70 #define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
71 #endif
72
73 /*
74 * The default timeout for waiting for BUSY to deassert during configuration.
75 * This is normally not necessary since for most reasonable configuration
76 * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
77 */
78 #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
79 #define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
80 #endif
81
82 /* Default timeout for waiting for FPGA to enter operational mode after
83 * configuration data has been written.
84 */
85 #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
86 #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
87 #endif
88
89 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
90 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
91
92 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
93 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
94
virtex2_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype)95 static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
96 bitstream_type bstype)
97 {
98 int ret_val = FPGA_FAIL;
99
100 switch (desc->iface) {
101 case slave_serial:
102 PRINTF("%s: Launching Slave Serial Load\n", __func__);
103 ret_val = virtex2_ss_load(desc, buf, bsize);
104 break;
105
106 case slave_selectmap:
107 PRINTF("%s: Launching Slave Parallel Load\n", __func__);
108 ret_val = virtex2_ssm_load(desc, buf, bsize);
109 break;
110
111 default:
112 printf("%s: Unsupported interface type, %d\n",
113 __func__, desc->iface);
114 }
115 return ret_val;
116 }
117
virtex2_dump(xilinx_desc * desc,const void * buf,size_t bsize)118 static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
119 {
120 int ret_val = FPGA_FAIL;
121
122 switch (desc->iface) {
123 case slave_serial:
124 PRINTF("%s: Launching Slave Serial Dump\n", __func__);
125 ret_val = virtex2_ss_dump(desc, buf, bsize);
126 break;
127
128 case slave_parallel:
129 PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
130 ret_val = virtex2_ssm_dump(desc, buf, bsize);
131 break;
132
133 default:
134 printf("%s: Unsupported interface type, %d\n",
135 __func__, desc->iface);
136 }
137 return ret_val;
138 }
139
virtex2_info(xilinx_desc * desc)140 static int virtex2_info(xilinx_desc *desc)
141 {
142 return FPGA_SUCCESS;
143 }
144
145 /*
146 * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
147 * is as follows:
148 * 1. Set the FPGA's PROG_B line low.
149 * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
150 * 3. Write data to the SelectMap port. If INIT_B goes low at any time
151 * this process, a configuration error (most likely CRC failure) has
152 * ocurred. At this point a status word may be read from the
153 * SelectMap interface to determine the source of the problem (You
154 * could, for instance, put this in your 'abort' function handler).
155 * 4. After all data has been written, test the state of the FPGA
156 * INIT_B and DONE lines. If both are high, configuration has
157 * succeeded. Congratulations!
158 */
virtex2_slave_pre(xilinx_virtex2_slave_fns * fn,int cookie)159 static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
160 {
161 unsigned long ts;
162
163 PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
164 __func__, __LINE__, fn);
165
166 if (!fn) {
167 printf("%s:%d: NULL Interface function table!\n",
168 __func__, __LINE__);
169 return FPGA_FAIL;
170 }
171
172 /* Gotta split this one up (so the stack won't blow??) */
173 PRINTF("%s:%d: Function Table:\n"
174 " base 0x%p\n"
175 " struct 0x%p\n"
176 " pre 0x%p\n"
177 " prog 0x%p\n"
178 " init 0x%p\n"
179 " error 0x%p\n",
180 __func__, __LINE__,
181 &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
182 PRINTF(" clock 0x%p\n"
183 " cs 0x%p\n"
184 " write 0x%p\n"
185 " rdata 0x%p\n"
186 " wdata 0x%p\n"
187 " busy 0x%p\n"
188 " abort 0x%p\n"
189 " post 0x%p\n\n",
190 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
191 fn->busy, fn->abort, fn->post);
192
193 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
194 printf("Initializing FPGA Device %d...\n", cookie);
195 #endif
196 /*
197 * Run the pre configuration function if there is one.
198 */
199 if (*fn->pre)
200 (*fn->pre)(cookie);
201
202 /*
203 * Assert the program line. The minimum pulse width for
204 * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
205 * There is no maximum value for the pulse width. Check to make
206 * sure that INIT_B goes low after assertion of PROG_B
207 */
208 (*fn->pgm)(true, true, cookie);
209 udelay(10);
210 ts = get_timer(0);
211 do {
212 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
213 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
214 __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
215 (*fn->abort)(cookie);
216 return FPGA_FAIL;
217 }
218 } while (!(*fn->init)(cookie));
219
220 (*fn->pgm)(false, true, cookie);
221 CONFIG_FPGA_DELAY();
222 if (fn->clk)
223 (*fn->clk)(true, true, cookie);
224
225 /*
226 * Start a timer and wait for INIT_B to go high
227 */
228 ts = get_timer(0);
229 do {
230 CONFIG_FPGA_DELAY();
231 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
232 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
233 __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
234 (*fn->abort)(cookie);
235 return FPGA_FAIL;
236 }
237 } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
238
239 if (fn->wr)
240 (*fn->wr)(true, true, cookie);
241 if (fn->cs)
242 (*fn->cs)(true, true, cookie);
243
244 mdelay(10);
245 return FPGA_SUCCESS;
246 }
247
virtex2_slave_post(xilinx_virtex2_slave_fns * fn,int cookie)248 static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
249 int cookie)
250 {
251 int ret_val = FPGA_SUCCESS;
252 int num_done = 0;
253 unsigned long ts;
254
255 /*
256 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
257 */
258 CONFIG_FPGA_DELAY();
259 if (fn->cs)
260 (*fn->cs)(false, true, cookie);
261 if (fn->wr)
262 (*fn->wr)(false, true, cookie);
263
264 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
265 putc('\n');
266 #endif
267
268 /*
269 * Check for successful configuration. FPGA INIT_B and DONE
270 * should both be high upon successful configuration. Continue pulsing
271 * clock with data set to all ones until DONE is asserted and for 8
272 * clock cycles afterwards.
273 */
274 ts = get_timer(0);
275 while (true) {
276 if ((*fn->done)(cookie) == FPGA_SUCCESS &&
277 !((*fn->init)(cookie))) {
278 if (num_done++ >= 8)
279 break;
280 }
281
282 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
283 printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
284 __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
285 (*fn->abort)(cookie);
286 ret_val = FPGA_FAIL;
287 break;
288 }
289 if (fn->wbulkdata) {
290 unsigned char dummy = 0xff;
291 (*fn->wbulkdata)(&dummy, 1, true, cookie);
292 } else {
293 (*fn->wdata)(0xff, true, cookie);
294 CONFIG_FPGA_DELAY();
295 (*fn->clk)(false, true, cookie);
296 CONFIG_FPGA_DELAY();
297 (*fn->clk)(true, true, cookie);
298 }
299 }
300
301 if (ret_val == FPGA_SUCCESS) {
302 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
303 printf("Initialization of FPGA device %d complete\n", cookie);
304 #endif
305 /*
306 * Run the post configuration function if there is one.
307 */
308 if (*fn->post)
309 (*fn->post)(cookie);
310 } else {
311 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
312 printf("** Initialization of FPGA device %d FAILED\n",
313 cookie);
314 #endif
315 }
316 return ret_val;
317 }
318
virtex2_ssm_load(xilinx_desc * desc,const void * buf,size_t bsize)319 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
320 {
321 int ret_val = FPGA_FAIL;
322 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
323 size_t bytecount = 0;
324 unsigned char *data = (unsigned char *)buf;
325 int cookie = desc->cookie;
326
327 ret_val = virtex2_slave_pre(fn, cookie);
328 if (ret_val != FPGA_SUCCESS)
329 return ret_val;
330
331 /*
332 * Load the data byte by byte
333 */
334 while (bytecount < bsize) {
335 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
336 if (ctrlc()) {
337 (*fn->abort)(cookie);
338 return FPGA_FAIL;
339 }
340 #endif
341
342 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
343 PRINTF("%s:%d:done went active early, bytecount = %d\n",
344 __func__, __LINE__, bytecount);
345 break;
346 }
347
348 #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
349 if ((*fn->init)(cookie)) {
350 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
351 __func__, __LINE__);
352 printf("%zu = buffer offset, %zu = buffer size\n",
353 bytecount, bsize);
354 (*fn->abort)(cookie);
355 return FPGA_FAIL;
356 }
357 #endif
358
359 (*fn->wdata)(data[bytecount++], true, cookie);
360 CONFIG_FPGA_DELAY();
361
362 /*
363 * Cycle the clock pin
364 */
365 (*fn->clk)(false, true, cookie);
366 CONFIG_FPGA_DELAY();
367 (*fn->clk)(true, true, cookie);
368
369 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
370 ts = get_timer(0);
371 while ((*fn->busy)(cookie)) {
372 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
373 printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
374 __func__, __LINE__,
375 CONFIG_SYS_FPGA_WAIT_BUSY);
376 (*fn->abort)(cookie);
377 return FPGA_FAIL;
378 }
379 }
380 #endif
381
382 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
383 if (bytecount % (bsize / 40) == 0)
384 putc('.');
385 #endif
386 }
387
388 return virtex2_slave_post(fn, cookie);
389 }
390
391 /*
392 * Read the FPGA configuration data
393 */
virtex2_ssm_dump(xilinx_desc * desc,const void * buf,size_t bsize)394 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
395 {
396 int ret_val = FPGA_FAIL;
397 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
398
399 if (fn) {
400 unsigned char *data = (unsigned char *)buf;
401 size_t bytecount = 0;
402 int cookie = desc->cookie;
403
404 printf("Starting Dump of FPGA Device %d...\n", cookie);
405
406 (*fn->cs)(true, true, cookie);
407 (*fn->clk)(true, true, cookie);
408
409 while (bytecount < bsize) {
410 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
411 if (ctrlc()) {
412 (*fn->abort)(cookie);
413 return FPGA_FAIL;
414 }
415 #endif
416 /*
417 * Cycle the clock and read the data
418 */
419 (*fn->clk)(false, true, cookie);
420 (*fn->clk)(true, true, cookie);
421 (*fn->rdata)(&data[bytecount++], cookie);
422 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
423 if (bytecount % (bsize / 40) == 0)
424 putc('.');
425 #endif
426 }
427
428 /*
429 * Deassert CS_B and cycle the clock to deselect the device.
430 */
431 (*fn->cs)(false, false, cookie);
432 (*fn->clk)(false, true, cookie);
433 (*fn->clk)(true, true, cookie);
434
435 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
436 putc('\n');
437 #endif
438 puts("Done.\n");
439 } else {
440 printf("%s:%d: NULL Interface function table!\n",
441 __func__, __LINE__);
442 }
443 return ret_val;
444 }
445
virtex2_ss_load(xilinx_desc * desc,const void * buf,size_t bsize)446 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
447 {
448 int ret_val = FPGA_FAIL;
449 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
450 unsigned char *data = (unsigned char *)buf;
451 int cookie = desc->cookie;
452
453 ret_val = virtex2_slave_pre(fn, cookie);
454 if (ret_val != FPGA_SUCCESS)
455 return ret_val;
456
457 if (fn->wbulkdata) {
458 /* Load the data in a single chunk */
459 (*fn->wbulkdata)(data, bsize, true, cookie);
460 } else {
461 size_t bytecount = 0;
462
463 /*
464 * Load the data bit by bit
465 */
466 while (bytecount < bsize) {
467 unsigned char curr_data = data[bytecount++];
468 int bit;
469
470 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
471 if (ctrlc()) {
472 (*fn->abort) (cookie);
473 return FPGA_FAIL;
474 }
475 #endif
476
477 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
478 PRINTF("%s:%d:done went active early, bytecount = %d\n",
479 __func__, __LINE__, bytecount);
480 break;
481 }
482
483 #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
484 if ((*fn->init)(cookie)) {
485 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
486 __func__, __LINE__);
487 printf("%zu = buffer offset, %zu = buffer size\n",
488 bytecount, bsize);
489 (*fn->abort)(cookie);
490 return FPGA_FAIL;
491 }
492 #endif
493
494 for (bit = 7; bit >= 0; --bit) {
495 unsigned char curr_bit = (curr_data >> bit) & 1;
496 (*fn->wdata)(curr_bit, true, cookie);
497 CONFIG_FPGA_DELAY();
498 (*fn->clk)(false, true, cookie);
499 CONFIG_FPGA_DELAY();
500 (*fn->clk)(true, true, cookie);
501 }
502
503 /* Slave serial never uses a busy pin */
504
505 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
506 if (bytecount % (bsize / 40) == 0)
507 putc('.');
508 #endif
509 }
510 }
511
512 return virtex2_slave_post(fn, cookie);
513 }
514
virtex2_ss_dump(xilinx_desc * desc,const void * buf,size_t bsize)515 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
516 {
517 printf("%s: Slave Serial Dumping is unsupported\n", __func__);
518 return FPGA_FAIL;
519 }
520
521 /* vim: set ts=4 tw=78: */
522
523 struct xilinx_fpga_op virtex2_op = {
524 .load = virtex2_load,
525 .dump = virtex2_dump,
526 .info = virtex2_info,
527 };
528