1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * i2c driver for Freescale i.MX series
4 *
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 *
8 * Based on i2c-imx.c from linux kernel:
9 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
10 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
11 * Copyright (C) 2007 RightHand Technologies, Inc.
12 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
13 *
14 */
15
16 #include <common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
19 #include <linux/errno.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/io.h>
22 #include <i2c.h>
23 #include <watchdog.h>
24 #include <dm.h>
25 #include <dm/pinctrl.h>
26 #include <fdtdec.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 #define I2C_QUIRK_FLAG (1 << 0)
31
32 #define IMX_I2C_REGSHIFT 2
33 #define VF610_I2C_REGSHIFT 0
34
35 #define I2C_EARLY_INIT_INDEX 0
36 #ifdef CONFIG_SYS_I2C_IFDR_DIV
37 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
38 #else
39 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
40 #endif
41
42 /* Register index */
43 #define IADR 0
44 #define IFDR 1
45 #define I2CR 2
46 #define I2SR 3
47 #define I2DR 4
48
49 #define I2CR_IIEN (1 << 6)
50 #define I2CR_MSTA (1 << 5)
51 #define I2CR_MTX (1 << 4)
52 #define I2CR_TX_NO_AK (1 << 3)
53 #define I2CR_RSTA (1 << 2)
54
55 #define I2SR_ICF (1 << 7)
56 #define I2SR_IBB (1 << 5)
57 #define I2SR_IAL (1 << 4)
58 #define I2SR_IIF (1 << 1)
59 #define I2SR_RX_NO_AK (1 << 0)
60
61 #ifdef I2C_QUIRK_REG
62 #define I2CR_IEN (0 << 7)
63 #define I2CR_IDIS (1 << 7)
64 #define I2SR_IIF_CLEAR (1 << 1)
65 #else
66 #define I2CR_IEN (1 << 7)
67 #define I2CR_IDIS (0 << 7)
68 #define I2SR_IIF_CLEAR (0 << 1)
69 #endif
70
71 #ifdef I2C_QUIRK_REG
72 static u16 i2c_clk_div[60][2] = {
73 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
74 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
75 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
76 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
77 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
78 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
79 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
80 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
81 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
82 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
83 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
84 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
85 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
86 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
87 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
88 };
89 #else
90 static u16 i2c_clk_div[50][2] = {
91 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
92 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
93 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
94 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
95 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
96 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
97 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
98 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
99 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
100 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
101 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
102 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
103 { 3072, 0x1E }, { 3840, 0x1F }
104 };
105 #endif
106
107 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
108 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
109 #endif
110 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
111 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
112 #endif
113 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
114 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
115 #endif
116 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
117 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
118 #endif
119
120 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
121 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
122 #endif
123 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
124 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
125 #endif
126 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
127 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
128 #endif
129 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
130 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
131 #endif
132
133 /*
134 * Calculate and set proper clock divider
135 */
i2c_imx_get_clk(struct mxc_i2c_bus * i2c_bus,unsigned int rate)136 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
137 {
138 unsigned int i2c_clk_rate;
139 unsigned int div;
140 u8 clk_div;
141
142 #if defined(CONFIG_MX31)
143 struct clock_control_regs *sc_regs =
144 (struct clock_control_regs *)CCM_BASE;
145
146 /* start the required I2C clock */
147 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
148 &sc_regs->cgr0);
149 #endif
150
151 /* Divider value calculation */
152 #if CONFIG_IS_ENABLED(CLK)
153 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
154 #else
155 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
156 #endif
157
158 div = (i2c_clk_rate + rate - 1) / rate;
159 if (div < i2c_clk_div[0][0])
160 clk_div = 0;
161 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
162 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
163 else
164 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
165 ;
166
167 /* Store divider value */
168 return clk_div;
169 }
170
171 /*
172 * Set I2C Bus speed
173 */
bus_i2c_set_bus_speed(struct mxc_i2c_bus * i2c_bus,int speed)174 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
175 {
176 ulong base = i2c_bus->base;
177 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
178 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
179 u8 idx = i2c_clk_div[clk_idx][1];
180 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
181
182 if (!base)
183 return -EINVAL;
184
185 /* Store divider value */
186 writeb(idx, base + (IFDR << reg_shift));
187
188 /* Reset module */
189 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
190 writeb(0, base + (I2SR << reg_shift));
191 return 0;
192 }
193
194 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
195 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
196 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
197
wait_for_sr_state(struct mxc_i2c_bus * i2c_bus,unsigned state)198 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
199 {
200 unsigned sr;
201 ulong elapsed;
202 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
203 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
204 ulong base = i2c_bus->base;
205 ulong start_time = get_timer(0);
206 for (;;) {
207 sr = readb(base + (I2SR << reg_shift));
208 if (sr & I2SR_IAL) {
209 if (quirk)
210 writeb(sr | I2SR_IAL, base +
211 (I2SR << reg_shift));
212 else
213 writeb(sr & ~I2SR_IAL, base +
214 (I2SR << reg_shift));
215 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
216 __func__, sr, readb(base + (I2CR << reg_shift)),
217 state);
218 return -ERESTART;
219 }
220 if ((sr & (state >> 8)) == (unsigned char)state)
221 return sr;
222 WATCHDOG_RESET();
223 elapsed = get_timer(start_time);
224 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
225 break;
226 }
227 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
228 sr, readb(base + (I2CR << reg_shift)), state);
229 return -ETIMEDOUT;
230 }
231
tx_byte(struct mxc_i2c_bus * i2c_bus,u8 byte)232 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
233 {
234 int ret;
235 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
236 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
237 ulong base = i2c_bus->base;
238
239 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
240 writeb(byte, base + (I2DR << reg_shift));
241
242 ret = wait_for_sr_state(i2c_bus, ST_IIF);
243 if (ret < 0)
244 return ret;
245 if (ret & I2SR_RX_NO_AK)
246 return -EREMOTEIO;
247 return 0;
248 }
249
250 /*
251 * Stub implementations for outer i2c slave operations.
252 */
__i2c_force_reset_slave(void)253 void __i2c_force_reset_slave(void)
254 {
255 }
256 void i2c_force_reset_slave(void)
257 __attribute__((weak, alias("__i2c_force_reset_slave")));
258
259 /*
260 * Stop I2C transaction
261 */
i2c_imx_stop(struct mxc_i2c_bus * i2c_bus)262 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
263 {
264 int ret;
265 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
266 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
267 ulong base = i2c_bus->base;
268 unsigned int temp = readb(base + (I2CR << reg_shift));
269
270 temp &= ~(I2CR_MSTA | I2CR_MTX);
271 writeb(temp, base + (I2CR << reg_shift));
272 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
273 if (ret < 0)
274 printf("%s:trigger stop failed\n", __func__);
275 }
276
277 /*
278 * Send start signal, chip address and
279 * write register address
280 */
i2c_init_transfer_(struct mxc_i2c_bus * i2c_bus,u8 chip,u32 addr,int alen)281 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
282 u32 addr, int alen)
283 {
284 unsigned int temp;
285 int ret;
286 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
287 ulong base = i2c_bus->base;
288 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
289
290 /* Reset i2c slave */
291 i2c_force_reset_slave();
292
293 /* Enable I2C controller */
294 if (quirk)
295 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
296 else
297 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
298
299 if (ret) {
300 writeb(I2CR_IEN, base + (I2CR << reg_shift));
301 /* Wait for controller to be stable */
302 udelay(50);
303 }
304
305 if (readb(base + (IADR << reg_shift)) == (chip << 1))
306 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
307 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
308 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
309 if (ret < 0)
310 return ret;
311
312 /* Start I2C transaction */
313 temp = readb(base + (I2CR << reg_shift));
314 temp |= I2CR_MSTA;
315 writeb(temp, base + (I2CR << reg_shift));
316
317 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
318 if (ret < 0)
319 return ret;
320
321 temp |= I2CR_MTX | I2CR_TX_NO_AK;
322 writeb(temp, base + (I2CR << reg_shift));
323
324 if (alen >= 0) {
325 /* write slave address */
326 ret = tx_byte(i2c_bus, chip << 1);
327 if (ret < 0)
328 return ret;
329
330 while (alen--) {
331 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
332 if (ret < 0)
333 return ret;
334 }
335 }
336
337 return 0;
338 }
339
340 #ifndef CONFIG_DM_I2C
i2c_idle_bus(struct mxc_i2c_bus * i2c_bus)341 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
342 {
343 if (i2c_bus && i2c_bus->idle_bus_fn)
344 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
345 return 0;
346 }
347 #else
348 /*
349 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
350 * "
351 * scl-gpios: specify the gpio related to SCL pin
352 * sda-gpios: specify the gpio related to SDA pin
353 * add pinctrl to configure i2c pins to gpio function for i2c
354 * bus recovery, call it "gpio" state
355 * "
356 *
357 * The i2c_idle_bus is an implementation following Linux Kernel.
358 */
i2c_idle_bus(struct mxc_i2c_bus * i2c_bus)359 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
360 {
361 struct udevice *bus = i2c_bus->bus;
362 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
363 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
364 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
365 int sda, scl, idle_sclks;
366 int i, ret = 0;
367 ulong elapsed, start_time;
368
369 if (pinctrl_select_state(bus, "gpio")) {
370 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
371 /*
372 * GPIO pinctrl for i2c force idle is not a must,
373 * but it is strongly recommended to be used.
374 * Because it can help you to recover from bad
375 * i2c bus state. Do not return failure, because
376 * it is not a must.
377 */
378 return 0;
379 }
380
381 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
382 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
383 scl = dm_gpio_get_value(scl_gpio);
384 sda = dm_gpio_get_value(sda_gpio);
385
386 if ((sda & scl) == 1)
387 goto exit; /* Bus is idle already */
388
389 /*
390 * In most cases it is just enough to generate 8 + 1 SCLK
391 * clocks to recover I2C slave device from 'stuck' state
392 * (when for example SW reset was performed, in the middle of
393 * I2C transmission).
394 *
395 * However, there are devices which send data in packets of
396 * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
397 * clocks.
398 */
399 idle_sclks = 8 + 1;
400
401 if (i2c->max_transaction_bytes > 0)
402 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
403 /* Send high and low on the SCL line */
404 for (i = 0; i < idle_sclks; i++) {
405 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
406 dm_gpio_set_value(scl_gpio, 0);
407 udelay(50);
408 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
409 udelay(50);
410 }
411 start_time = get_timer(0);
412 for (;;) {
413 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
414 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
415 scl = dm_gpio_get_value(scl_gpio);
416 sda = dm_gpio_get_value(sda_gpio);
417 if ((sda & scl) == 1)
418 break;
419 WATCHDOG_RESET();
420 elapsed = get_timer(start_time);
421 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
422 ret = -EBUSY;
423 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
424 break;
425 }
426 }
427
428 exit:
429 pinctrl_select_state(bus, "default");
430 return ret;
431 }
432 #endif
433
i2c_init_transfer(struct mxc_i2c_bus * i2c_bus,u8 chip,u32 addr,int alen)434 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
435 u32 addr, int alen)
436 {
437 int retry;
438 int ret;
439 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
440 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
441
442 if (!i2c_bus->base)
443 return -EINVAL;
444
445 for (retry = 0; retry < 3; retry++) {
446 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
447 if (ret >= 0)
448 return 0;
449 i2c_imx_stop(i2c_bus);
450 if (ret == -EREMOTEIO)
451 return ret;
452
453 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
454 retry);
455 if (ret != -ERESTART)
456 /* Disable controller */
457 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
458 udelay(100);
459 if (i2c_idle_bus(i2c_bus) < 0)
460 break;
461 }
462 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
463 return ret;
464 }
465
466
i2c_write_data(struct mxc_i2c_bus * i2c_bus,u8 chip,const u8 * buf,int len)467 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
468 int len)
469 {
470 int i, ret = 0;
471
472 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
473 debug("write_data: ");
474 /* use rc for counter */
475 for (i = 0; i < len; ++i)
476 debug(" 0x%02x", buf[i]);
477 debug("\n");
478
479 for (i = 0; i < len; i++) {
480 ret = tx_byte(i2c_bus, buf[i]);
481 if (ret < 0) {
482 debug("i2c_write_data(): rc=%d\n", ret);
483 break;
484 }
485 }
486
487 return ret;
488 }
489
490 /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
491 * final message of a transaction. If not, it switches the bus back to TX mode
492 * and does not send a STOP, leaving the bus in a state where a repeated start
493 * and address can be sent for another message.
494 */
i2c_read_data(struct mxc_i2c_bus * i2c_bus,uchar chip,uchar * buf,int len,bool last)495 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
496 int len, bool last)
497 {
498 int ret;
499 unsigned int temp;
500 int i;
501 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
502 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
503 ulong base = i2c_bus->base;
504
505 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
506
507 /* setup bus to read data */
508 temp = readb(base + (I2CR << reg_shift));
509 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
510 if (len == 1)
511 temp |= I2CR_TX_NO_AK;
512 writeb(temp, base + (I2CR << reg_shift));
513 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
514 /* dummy read to clear ICF */
515 readb(base + (I2DR << reg_shift));
516
517 /* read data */
518 for (i = 0; i < len; i++) {
519 ret = wait_for_sr_state(i2c_bus, ST_IIF);
520 if (ret < 0) {
521 debug("i2c_read_data(): ret=%d\n", ret);
522 i2c_imx_stop(i2c_bus);
523 return ret;
524 }
525
526 if (i == (len - 1)) {
527 /* Final byte has already been received by master! When
528 * we read it from I2DR, the master will start another
529 * cycle. We must program it first to send a STOP or
530 * switch to TX to avoid this.
531 */
532 if (last) {
533 i2c_imx_stop(i2c_bus);
534 } else {
535 /* Final read, no stop, switch back to tx */
536 temp = readb(base + (I2CR << reg_shift));
537 temp |= I2CR_MTX | I2CR_TX_NO_AK;
538 writeb(temp, base + (I2CR << reg_shift));
539 }
540 } else if (i == (len - 2)) {
541 /* Master has already recevied penultimate byte. When
542 * we read it from I2DR, master will start RX of final
543 * byte. We must set TX_NO_AK now so it does not ACK
544 * that final byte.
545 */
546 temp = readb(base + (I2CR << reg_shift));
547 temp |= I2CR_TX_NO_AK;
548 writeb(temp, base + (I2CR << reg_shift));
549 }
550
551 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
552 buf[i] = readb(base + (I2DR << reg_shift));
553 }
554
555 /* reuse ret for counter*/
556 for (ret = 0; ret < len; ++ret)
557 debug(" 0x%02x", buf[ret]);
558 debug("\n");
559
560 /* It is not clear to me that this is necessary */
561 if (last)
562 i2c_imx_stop(i2c_bus);
563 return 0;
564 }
565
__enable_i2c_clk(unsigned char enable,unsigned int i2c_num)566 int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
567 {
568 return 1;
569 }
570
571 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
572 __attribute__((weak, alias("__enable_i2c_clk")));
573
574 #ifndef CONFIG_DM_I2C
575 /*
576 * Read data from I2C device
577 *
578 * The transactions use the syntax defined in the Linux kernel I2C docs.
579 *
580 * If alen is > 0, then this function will send a transaction of the form:
581 * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
582 * This is a normal I2C register read: writing the register address, then doing
583 * a repeated start and reading the data.
584 *
585 * If alen == 0, then we get this transaction:
586 * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
587 * This is somewhat unusual, though valid, transaction. It addresses the chip
588 * in write mode, but doesn't actually write any register address or data, then
589 * does a repeated start and reads data.
590 *
591 * If alen < 0, then we get this transaction:
592 * S Chip Rd [A] [data] A ... NA P
593 * The chip is addressed in read mode and then data is read. No register
594 * address is written first. This is perfectly valid on most devices and
595 * required on some (usually those that don't act like an array of registers).
596 */
bus_i2c_read(struct mxc_i2c_bus * i2c_bus,u8 chip,u32 addr,int alen,u8 * buf,int len)597 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
598 int alen, u8 *buf, int len)
599 {
600 int ret = 0;
601 u32 temp;
602 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
603 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
604 ulong base = i2c_bus->base;
605
606 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
607 if (ret < 0)
608 return ret;
609
610 if (alen >= 0) {
611 temp = readb(base + (I2CR << reg_shift));
612 temp |= I2CR_RSTA;
613 writeb(temp, base + (I2CR << reg_shift));
614 }
615
616 ret = tx_byte(i2c_bus, (chip << 1) | 1);
617 if (ret < 0) {
618 i2c_imx_stop(i2c_bus);
619 return ret;
620 }
621
622 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
623
624 i2c_imx_stop(i2c_bus);
625 return ret;
626 }
627
628 /*
629 * Write data to I2C device
630 *
631 * If alen > 0, we get this transaction:
632 * S Chip Wr [A] addr [A] data [A] ... [A] P
633 * An ordinary write register command.
634 *
635 * If alen == 0, then we get this:
636 * S Chip Wr [A] data [A] ... [A] P
637 * This is a simple I2C write.
638 *
639 * If alen < 0, then we get this:
640 * S data [A] ... [A] P
641 * This is most likely NOT something that should be used. It doesn't send the
642 * chip address first, so in effect, the first byte of data will be used as the
643 * address.
644 */
bus_i2c_write(struct mxc_i2c_bus * i2c_bus,u8 chip,u32 addr,int alen,const u8 * buf,int len)645 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
646 int alen, const u8 *buf, int len)
647 {
648 int ret = 0;
649
650 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
651 if (ret < 0)
652 return ret;
653
654 ret = i2c_write_data(i2c_bus, chip, buf, len);
655
656 i2c_imx_stop(i2c_bus);
657
658 return ret;
659 }
660
661 #if !defined(I2C2_BASE_ADDR)
662 #define I2C2_BASE_ADDR 0
663 #endif
664
665 #if !defined(I2C3_BASE_ADDR)
666 #define I2C3_BASE_ADDR 0
667 #endif
668
669 #if !defined(I2C4_BASE_ADDR)
670 #define I2C4_BASE_ADDR 0
671 #endif
672
673 #if !defined(I2C5_BASE_ADDR)
674 #define I2C5_BASE_ADDR 0
675 #endif
676
677 #if !defined(I2C6_BASE_ADDR)
678 #define I2C6_BASE_ADDR 0
679 #endif
680
681 #if !defined(I2C7_BASE_ADDR)
682 #define I2C7_BASE_ADDR 0
683 #endif
684
685 #if !defined(I2C8_BASE_ADDR)
686 #define I2C8_BASE_ADDR 0
687 #endif
688
689 static struct mxc_i2c_bus mxc_i2c_buses[] = {
690 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
691 defined(CONFIG_FSL_LAYERSCAPE)
692 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
693 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
694 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
695 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
696 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
697 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
698 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
699 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
700 #else
701 { 0, I2C1_BASE_ADDR, 0 },
702 { 1, I2C2_BASE_ADDR, 0 },
703 { 2, I2C3_BASE_ADDR, 0 },
704 { 3, I2C4_BASE_ADDR, 0 },
705 { 4, I2C5_BASE_ADDR, 0 },
706 { 5, I2C6_BASE_ADDR, 0 },
707 { 6, I2C7_BASE_ADDR, 0 },
708 { 7, I2C8_BASE_ADDR, 0 },
709 #endif
710 };
711
i2c_get_base(struct i2c_adapter * adap)712 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
713 {
714 return &mxc_i2c_buses[adap->hwadapnr];
715 }
716
mxc_i2c_read(struct i2c_adapter * adap,uint8_t chip,uint addr,int alen,uint8_t * buffer,int len)717 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
718 uint addr, int alen, uint8_t *buffer,
719 int len)
720 {
721 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
722 }
723
mxc_i2c_write(struct i2c_adapter * adap,uint8_t chip,uint addr,int alen,uint8_t * buffer,int len)724 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
725 uint addr, int alen, uint8_t *buffer,
726 int len)
727 {
728 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
729 }
730
731 /*
732 * Test if a chip at a given address responds (probe the chip)
733 */
mxc_i2c_probe(struct i2c_adapter * adap,uint8_t chip)734 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
735 {
736 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
737 }
738
bus_i2c_init(int index,int speed,int unused,int (* idle_bus_fn)(void * p),void * idle_bus_data)739 void bus_i2c_init(int index, int speed, int unused,
740 int (*idle_bus_fn)(void *p), void *idle_bus_data)
741 {
742 int ret;
743
744 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
745 debug("Error i2c index\n");
746 return;
747 }
748
749 /*
750 * Warning: Be careful to allow the assignment to a static
751 * variable here. This function could be called while U-Boot is
752 * still running in flash memory. So such assignment is equal
753 * to write data to flash without erasing.
754 */
755 if (idle_bus_fn)
756 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
757 if (idle_bus_data)
758 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
759
760 ret = enable_i2c_clk(1, index);
761 if (ret < 0) {
762 debug("I2C-%d clk fail to enable.\n", index);
763 return;
764 }
765
766 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
767 }
768
769 /*
770 * Early init I2C for prepare read the clk through I2C.
771 */
i2c_early_init_f(void)772 void i2c_early_init_f(void)
773 {
774 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
775 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
776 & I2C_QUIRK_FLAG ? true : false;
777 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
778
779 /* Set I2C divider value */
780 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
781 /* Reset module */
782 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
783 writeb(0, base + (I2SR << reg_shift));
784 /* Enable I2C */
785 writeb(I2CR_IEN, base + (I2CR << reg_shift));
786 }
787
788 /*
789 * Init I2C Bus
790 */
mxc_i2c_init(struct i2c_adapter * adap,int speed,int slaveaddr)791 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
792 {
793 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
794 }
795
796 /*
797 * Set I2C Speed
798 */
mxc_i2c_set_bus_speed(struct i2c_adapter * adap,uint speed)799 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
800 {
801 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
802 }
803
804 /*
805 * Register mxc i2c adapters
806 */
807 #ifdef CONFIG_SYS_I2C_MXC_I2C1
808 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
809 mxc_i2c_read, mxc_i2c_write,
810 mxc_i2c_set_bus_speed,
811 CONFIG_SYS_MXC_I2C1_SPEED,
812 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
813 #endif
814
815 #ifdef CONFIG_SYS_I2C_MXC_I2C2
816 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
817 mxc_i2c_read, mxc_i2c_write,
818 mxc_i2c_set_bus_speed,
819 CONFIG_SYS_MXC_I2C2_SPEED,
820 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
821 #endif
822
823 #ifdef CONFIG_SYS_I2C_MXC_I2C3
824 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
825 mxc_i2c_read, mxc_i2c_write,
826 mxc_i2c_set_bus_speed,
827 CONFIG_SYS_MXC_I2C3_SPEED,
828 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
829 #endif
830
831 #ifdef CONFIG_SYS_I2C_MXC_I2C4
832 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
833 mxc_i2c_read, mxc_i2c_write,
834 mxc_i2c_set_bus_speed,
835 CONFIG_SYS_MXC_I2C4_SPEED,
836 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
837 #endif
838
839 #ifdef CONFIG_SYS_I2C_MXC_I2C5
840 U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
841 mxc_i2c_read, mxc_i2c_write,
842 mxc_i2c_set_bus_speed,
843 CONFIG_SYS_MXC_I2C5_SPEED,
844 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
845 #endif
846
847 #ifdef CONFIG_SYS_I2C_MXC_I2C6
848 U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
849 mxc_i2c_read, mxc_i2c_write,
850 mxc_i2c_set_bus_speed,
851 CONFIG_SYS_MXC_I2C6_SPEED,
852 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
853 #endif
854
855 #ifdef CONFIG_SYS_I2C_MXC_I2C7
856 U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
857 mxc_i2c_read, mxc_i2c_write,
858 mxc_i2c_set_bus_speed,
859 CONFIG_SYS_MXC_I2C7_SPEED,
860 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
861 #endif
862
863 #ifdef CONFIG_SYS_I2C_MXC_I2C8
864 U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
865 mxc_i2c_read, mxc_i2c_write,
866 mxc_i2c_set_bus_speed,
867 CONFIG_SYS_MXC_I2C8_SPEED,
868 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
869 #endif
870
871 #else
872
873 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
874 {
875 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
876
877 return bus_i2c_set_bus_speed(i2c_bus, speed);
878 }
879
880 static int mxc_i2c_probe(struct udevice *bus)
881 {
882 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
883 const void *fdt = gd->fdt_blob;
884 int node = dev_of_offset(bus);
885 fdt_addr_t addr;
886 int ret, ret2;
887
888 i2c_bus->driver_data = dev_get_driver_data(bus);
889
890 addr = devfdt_get_addr(bus);
891 if (addr == FDT_ADDR_T_NONE)
892 return -EINVAL;
893
894 i2c_bus->base = addr;
895 i2c_bus->index = bus->seq;
896 i2c_bus->bus = bus;
897
898 /* Enable clk */
899 #if CONFIG_IS_ENABLED(CLK)
900 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
901 if (ret) {
902 printf("Failed to get i2c clk\n");
903 return ret;
904 }
905 ret = clk_enable(&i2c_bus->per_clk);
906 if (ret) {
907 printf("Failed to enable i2c clk\n");
908 return ret;
909 }
910 #else
911 ret = enable_i2c_clk(1, bus->seq);
912 if (ret < 0)
913 return ret;
914 #endif
915
916 /*
917 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
918 * Use gpio to force bus idle when necessary.
919 */
920 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
921 if (ret < 0) {
922 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
923 } else {
924 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
925 "scl-gpios", 0, &i2c_bus->scl_gpio,
926 GPIOD_IS_OUT);
927 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
928 "sda-gpios", 0, &i2c_bus->sda_gpio,
929 GPIOD_IS_OUT);
930 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
931 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
932 ret || ret2) {
933 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
934 return -EINVAL;
935 }
936 }
937
938 /*
939 * Pinmux settings are in board file now, until pinmux is supported,
940 * we can set pinmux here in probe function.
941 */
942
943 debug("i2c : controller bus %d at %lu , speed %d: ",
944 bus->seq, i2c_bus->base,
945 i2c_bus->speed);
946
947 return 0;
948 }
949
950 /* Sends: S Addr Wr [A|NA] P */
951 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
952 u32 chip_flags)
953 {
954 int ret;
955 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
956
957 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
958 if (ret < 0) {
959 debug("%s failed, ret = %d\n", __func__, ret);
960 return ret;
961 }
962
963 i2c_imx_stop(i2c_bus);
964
965 return 0;
966 }
967
968 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
969 {
970 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
971 int ret = 0;
972 ulong base = i2c_bus->base;
973 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
974 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
975 int read_mode;
976
977 /* Here address len is set to -1 to not send any address at first.
978 * Otherwise i2c_init_transfer will send the chip address with write
979 * mode set. This is wrong if the 1st message is read.
980 */
981 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
982 if (ret < 0) {
983 debug("i2c_init_transfer error: %d\n", ret);
984 return ret;
985 }
986
987 read_mode = -1; /* So it's always different on the first message */
988 for (; nmsgs > 0; nmsgs--, msg++) {
989 const int msg_is_read = !!(msg->flags & I2C_M_RD);
990
991 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
992 msg->len, msg_is_read ? 'R' : 'W');
993
994 if (msg_is_read != read_mode) {
995 /* Send repeated start if not 1st message */
996 if (read_mode != -1) {
997 debug("i2c_xfer: [RSTART]\n");
998 ret = readb(base + (I2CR << reg_shift));
999 ret |= I2CR_RSTA;
1000 writeb(ret, base + (I2CR << reg_shift));
1001 }
1002 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1003 msg_is_read ? 'R' : 'W');
1004 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1005 if (ret < 0) {
1006 debug("i2c_xfer: [STOP]\n");
1007 i2c_imx_stop(i2c_bus);
1008 break;
1009 }
1010 read_mode = msg_is_read;
1011 }
1012
1013 if (msg->flags & I2C_M_RD)
1014 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1015 msg->len, nmsgs == 1 ||
1016 (msg->flags & I2C_M_STOP));
1017 else
1018 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1019 msg->len);
1020
1021 if (ret < 0)
1022 break;
1023 }
1024
1025 if (ret)
1026 debug("i2c_write: error sending\n");
1027
1028 i2c_imx_stop(i2c_bus);
1029
1030 return ret;
1031 }
1032
1033 static const struct dm_i2c_ops mxc_i2c_ops = {
1034 .xfer = mxc_i2c_xfer,
1035 .probe_chip = mxc_i2c_probe_chip,
1036 .set_bus_speed = mxc_i2c_set_bus_speed,
1037 };
1038
1039 static const struct udevice_id mxc_i2c_ids[] = {
1040 { .compatible = "fsl,imx21-i2c", },
1041 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1042 {}
1043 };
1044
1045 U_BOOT_DRIVER(i2c_mxc) = {
1046 .name = "i2c_mxc",
1047 .id = UCLASS_I2C,
1048 .of_match = mxc_i2c_ids,
1049 .probe = mxc_i2c_probe,
1050 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
1051 .ops = &mxc_i2c_ops,
1052 };
1053 #endif
1054