1 /*
2 * This code was extracted from:
3 * git://github.com/gonzoua/u-boot-pi.git master
4 * and hence presumably (C) 2012 Oleksandr Tymoshenko
5 *
6 * Tweaks for U-Boot upstreaming
7 * (C) 2012 Stephen Warren
8 *
9 * Portions (e.g. read/write macros, concepts for back-to-back register write
10 * timing workarounds) obviously extracted from the Linux kernel at:
11 * https://github.com/raspberrypi/linux.git rpi-3.6.y
12 *
13 * The Linux kernel code has the following (c) and license, which is hence
14 * propagated to Oleksandr's tree and here:
15 *
16 * Support for SDHCI device on 2835
17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33 /* Supports:
34 * SDHCI platform device - Arasan SD controller in BCM2708
35 *
36 * Inspired by sdhci-pci.c, by Pierre Ossman
37 */
38
39 #include <common.h>
40 #include <dm.h>
41 #include <malloc.h>
42 #include <memalign.h>
43 #include <sdhci.h>
44 #include <time.h>
45 #include <asm/arch/msg.h>
46 #include <asm/arch/mbox.h>
47 #include <mach/sdhci.h>
48 #include <mach/timer.h>
49
50 /* 400KHz is max freq for card ID etc. Use that as min */
51 #define MIN_FREQ 400000
52 #define SDHCI_BUFFER 0x20
53
54 struct bcm2835_sdhci_plat {
55 struct mmc_config cfg;
56 struct mmc mmc;
57 };
58
59 struct bcm2835_sdhci_host {
60 struct sdhci_host host;
61 uint twoticks_delay;
62 ulong last_write;
63 };
64
to_bcm(struct sdhci_host * host)65 static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host)
66 {
67 return (struct bcm2835_sdhci_host *)host;
68 }
69
bcm2835_sdhci_raw_writel(struct sdhci_host * host,u32 val,int reg)70 static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val,
71 int reg)
72 {
73 struct bcm2835_sdhci_host *bcm_host = to_bcm(host);
74
75 /*
76 * The Arasan has a bugette whereby it may lose the content of
77 * successive writes to registers that are within two SD-card clock
78 * cycles of each other (a clock domain crossing problem).
79 * It seems, however, that the data register does not have this problem.
80 * (Which is just as well - otherwise we'd have to nobble the DMA engine
81 * too)
82 */
83 if (reg != SDHCI_BUFFER) {
84 while (timer_get_us() - bcm_host->last_write <
85 bcm_host->twoticks_delay)
86 ;
87 }
88
89 writel(val, host->ioaddr + reg);
90 bcm_host->last_write = timer_get_us();
91 }
92
bcm2835_sdhci_raw_readl(struct sdhci_host * host,int reg)93 static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
94 {
95 return readl(host->ioaddr + reg);
96 }
97
bcm2835_sdhci_writel(struct sdhci_host * host,u32 val,int reg)98 static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
99 {
100 bcm2835_sdhci_raw_writel(host, val, reg);
101 }
102
bcm2835_sdhci_writew(struct sdhci_host * host,u16 val,int reg)103 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
104 {
105 static u32 shadow;
106 u32 oldval = (reg == SDHCI_COMMAND) ? shadow :
107 bcm2835_sdhci_raw_readl(host, reg & ~3);
108 u32 word_num = (reg >> 1) & 1;
109 u32 word_shift = word_num * 16;
110 u32 mask = 0xffff << word_shift;
111 u32 newval = (oldval & ~mask) | (val << word_shift);
112
113 if (reg == SDHCI_TRANSFER_MODE)
114 shadow = newval;
115 else
116 bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
117 }
118
bcm2835_sdhci_writeb(struct sdhci_host * host,u8 val,int reg)119 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
120 {
121 u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3);
122 u32 byte_num = reg & 3;
123 u32 byte_shift = byte_num * 8;
124 u32 mask = 0xff << byte_shift;
125 u32 newval = (oldval & ~mask) | (val << byte_shift);
126
127 bcm2835_sdhci_raw_writel(host, newval, reg & ~3);
128 }
129
bcm2835_sdhci_readl(struct sdhci_host * host,int reg)130 static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
131 {
132 u32 val = bcm2835_sdhci_raw_readl(host, reg);
133
134 return val;
135 }
136
bcm2835_sdhci_readw(struct sdhci_host * host,int reg)137 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
138 {
139 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
140 u32 word_num = (reg >> 1) & 1;
141 u32 word_shift = word_num * 16;
142 u32 word = (val >> word_shift) & 0xffff;
143
144 return word;
145 }
146
bcm2835_sdhci_readb(struct sdhci_host * host,int reg)147 static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
148 {
149 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3));
150 u32 byte_num = reg & 3;
151 u32 byte_shift = byte_num * 8;
152 u32 byte = (val >> byte_shift) & 0xff;
153
154 return byte;
155 }
156
157 static const struct sdhci_ops bcm2835_ops = {
158 .write_l = bcm2835_sdhci_writel,
159 .write_w = bcm2835_sdhci_writew,
160 .write_b = bcm2835_sdhci_writeb,
161 .read_l = bcm2835_sdhci_readl,
162 .read_w = bcm2835_sdhci_readw,
163 .read_b = bcm2835_sdhci_readb,
164 };
165
bcm2835_sdhci_bind(struct udevice * dev)166 static int bcm2835_sdhci_bind(struct udevice *dev)
167 {
168 struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
169
170 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
171 }
172
bcm2835_sdhci_probe(struct udevice * dev)173 static int bcm2835_sdhci_probe(struct udevice *dev)
174 {
175 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
176 struct bcm2835_sdhci_plat *plat = dev_get_platdata(dev);
177 struct bcm2835_sdhci_host *priv = dev_get_priv(dev);
178 struct sdhci_host *host = &priv->host;
179 fdt_addr_t base;
180 int emmc_freq;
181 int ret;
182 int clock_id = (int)dev_get_driver_data(dev);
183
184 base = devfdt_get_addr(dev);
185 if (base == FDT_ADDR_T_NONE)
186 return -EINVAL;
187
188 ret = bcm2835_get_mmc_clock(clock_id);
189 if (ret < 0) {
190 debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret);
191 return ret;
192 }
193 emmc_freq = ret;
194
195 /*
196 * See the comments in bcm2835_sdhci_raw_writel().
197 *
198 * This should probably be dynamically calculated based on the actual
199 * frequency. However, this is the longest we'll have to wait, and
200 * doesn't seem to slow access down too much, so the added complexity
201 * doesn't seem worth it for now.
202 *
203 * 1/MIN_FREQ is (max) time per tick of eMMC clock.
204 * 2/MIN_FREQ is time for two ticks.
205 * Multiply by 1000000 to get uS per two ticks.
206 * +1 for hack rounding.
207 */
208 priv->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1;
209 priv->last_write = 0;
210
211 host->name = dev->name;
212 host->ioaddr = (void *)base;
213 host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
214 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
215 host->max_clk = emmc_freq;
216 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
217 host->ops = &bcm2835_ops;
218
219 host->mmc = &plat->mmc;
220 host->mmc->dev = dev;
221
222 ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ);
223 if (ret) {
224 debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret);
225 return ret;
226 }
227
228 upriv->mmc = &plat->mmc;
229 host->mmc->priv = host;
230
231 return sdhci_probe(dev);
232 }
233
234 static const struct udevice_id bcm2835_sdhci_match[] = {
235 {
236 .compatible = "brcm,bcm2835-sdhci",
237 .data = BCM2835_MBOX_CLOCK_ID_EMMC
238 },
239 {
240 .compatible = "brcm,bcm2711-emmc2",
241 .data = BCM2835_MBOX_CLOCK_ID_EMMC2
242 },
243 { /* sentinel */ }
244 };
245
246 U_BOOT_DRIVER(sdhci_cdns) = {
247 .name = "sdhci-bcm2835",
248 .id = UCLASS_MMC,
249 .of_match = bcm2835_sdhci_match,
250 .bind = bcm2835_sdhci_bind,
251 .probe = bcm2835_sdhci_probe,
252 .priv_auto_alloc_size = sizeof(struct bcm2835_sdhci_host),
253 .platdata_auto_alloc_size = sizeof(struct bcm2835_sdhci_plat),
254 .ops = &sdhci_ops,
255 };
256