1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 */
18
19 /* CRG register */
20 #define PERI_CRG_MMC_CLK (CRG_REG_BASE + 0x34c0)
21 #define CRG_CLK_SEL_SHIFT 24
22 #define CRG_CLK_SEL_MASK (0x7 << CRG_CLK_SEL_SHIFT)
23 #define CRG_DLL_SRST_REQ (1 << 16)
24 #define CRG_CLK_EN (1 << 0)
25 #define CRG_AHB_CLK_EN (2 << 0)
26
27 #define PERI_CRG_MMC_P4_DLL (CRG_REG_BASE + 0x34c4)
28 #define CRG_P4_DLL_SRST_REQ (1 << 1)
29
30 #define PERI_CRG_MMC_DRV_DLL (CRG_REG_BASE + 0x34c8)
31 #define CRG_DRV_PHASE_SEL_SHIFT 15
32 #define CRG_DRV_PHASE_SEL_MASK (0x1F << 15)
33
34 #define PERI_CRG_MMC_STAT (CRG_REG_BASE + 0x34d8)
35 #define CRG_SAM_DLL_READY (1 << 12)
36 #define CRG_DS_DLL_READY (1 << 10)
37 #define CRG_P4_DLL_LOCKED (1 << 9)
38
39 #define REG_EMMC_SAMPL_DLL_STATUS PERI_CRG_MMC_STAT
40 #define REG_SDIO0_SAMPL_DLL_STATUS PERI_CRG_MMC_STAT
41 #define SDIO_SAMPL_DLL_SLAVE_READY CRG_SAM_DLL_READY
42
43 #define REG_EMMC_DRV_DLL_CTRL PERI_CRG_MMC_DRV_DLL
44 #define REG_SDIO0_DRV_DLL_CTRL PERI_CRG_MMC_DRV_DLL
45 #define SDIO_DRV_PHASE_SEL_MASK CRG_DRV_PHASE_SEL_MASK
46 #define sdio_drv_sel(phase) ((phase) << CRG_DRV_PHASE_SEL_SHIFT)
47
48 #define REG_EMMC_SAMPLB_DLL_CTRL 0x34d4
49 #define SDIO_SAMPLB_DLL_CLK_MASK 0xf
50 #define sdio_samplb_sel(phase) (((phase) & 0xf) << 0)
51
52 /* eMMC io reg */
53 #define REG_IO_CFG_BASE 0x10FF0000
54 #define REG_MMC_D0_IO 0xd0
55 #define REG_MMC_D1_IO 0xd4
56 #define REG_MMC_D2_IO 0xd8
57 #define REG_MMC_D3_IO 0xdc
58 #define REG_MMC_CLK_IO 0xc8
59 #define REG_MMC_CMD_IO 0xcc
60 #define REG_MMC_RST_IO 0xc4
61 #define REG_MMC_D4_IO 0xec
62 #define REG_MMC_D6_IO 0xf0
63 #define REG_MMC_D5_IO 0xe0
64 #define REG_MMC_D7_IO 0xe4
65 #define REG_MMC_DQS_IO 0xf4
66
67 /* IO CFG */
68 #define IO_CFG_DRV_STR_MASK (0xf << 4)
69 #define io_cfg_drv_str_sel(str) ((str) << 4)
70 #define IO_CFG_PULL_UP (0x1 << 8)
71 #define IO_CFG_PULL_DOWN (0x1 << 9)
72 #define IO_CFG_SR (0x1 << 10)
73 #define IO_CFG_SDIO_MASK (IO_CFG_DRV_STR_MASK | IO_CFG_PULL_UP |\
74 IO_CFG_PULL_DOWN | IO_CFG_SR)
75 #define MMC_IO_MUX 0x1
76 #define SD_IO_MUX 0x2
77 #define IO_MUX_MASK 0x3
78 #define MMC_BUS_WIDTH_4_BIT 4
79 #define MMC_BUS_WIDTH_8_BIT 8
80 #define BOOT_FROM_NAND_FLAG (0x1 << 2)
81 #define BOOT_FLAG_MASK (0x3 << 2)
82 #define EMMC_BOOT_8BIT (0x1 << 11)
83
84 #define IO_CLK 0
85 #define IO_CMD 1
86 #define IO_DATA 2
87 #define IO_RST 3
88 #define IO_DS 4
89 #define EMMC_IO_TYPE_NUM 5
90
91 static unsigned int reg_data_io[] = {
92 REG_MMC_D0_IO, REG_MMC_D1_IO,
93 REG_MMC_D2_IO, REG_MMC_D3_IO,
94 REG_MMC_D4_IO, REG_MMC_D5_IO,
95 REG_MMC_D6_IO, REG_MMC_D7_IO
96 };
97
98 static u32 hisi_mmc_io_cfg[][EMMC_IO_TYPE_NUM] = {
99 [MMC_LEGACY] = {
100 io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
101 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
102 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
103 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
104 },
105 [MMC_HS] = {
106 io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
107 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
108 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
109 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
110 },
111 [SD_HS] = {
112 io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
113 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
114 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP
115 },
116 [MMC_HS_52] = {
117 io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
118 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
119 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
120 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
121 },
122 [MMC_HS_200] = {
123 io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
124 io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
125 io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
126 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
127 },
128 [MMC_HS_400] = {
129 io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
130 io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP,
131 io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP,
132 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP,
133 io_cfg_drv_str_sel(0x3)
134 },
135 [MMC_HS_400_ES] = {
136 io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
137 io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP,
138 io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_UP,
139 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP,
140 io_cfg_drv_str_sel(0x3)
141 }
142 };
143
144 /* avaliable frequency */
145 #define CLK_400K 400000
146 #define CLK_24P75M 24750000
147 #define CLK_49P5M 49500000
148 #define CLK_99M 99000000
149 #define CLK_148P5M 148500000
150
151 /* sample drive phase */
152 #define DRIVE 0
153 #define SAMPLE 1
154 #define PHASE_TYPE_NUM 2
155
156 static u32 hisi_phase_cfg[][PHASE_TYPE_NUM] = {
157 [MMC_LEGACY] = { 16, 0 },
158 [MMC_HS] = { 16, 4 },
159 [MMC_HS_52] = { 16, 4 },
160 [SD_HS] = { 16, 4 },
161 [MMC_HS_200] = { 22, 0 },
162 #ifdef CONFIG_TARGET_HI3521DV200
163 [MMC_HS_400] = { 9, 0 },
164 [MMC_HS_400_ES] = { 9, 0 }
165 #else /* CONFIG_TARGET_HI3520DV500 */
166 [MMC_HS_400] = { 11, 0 },
167 [MMC_HS_400_ES] = { 11, 0 }
168 #endif
169 };
170
get_ocr_from_bootrom(void)171 unsigned int get_ocr_from_bootrom(void)
172 {
173 return readl(REG_SAVE_HCS);
174 }
175
hisi_wait_drv_dll_lock(struct sdhci_host * host)176 void hisi_wait_drv_dll_lock(struct sdhci_host *host)
177 {
178 /* doing nothing */
179 }
180
hisi_enable_sampl_dll_slave(struct sdhci_host * host)181 void hisi_enable_sampl_dll_slave(struct sdhci_host *host)
182 {
183 /* doing nothing */
184 }
185
hisi_dll_reset_assert(void)186 static void hisi_dll_reset_assert(void)
187 {
188 const uintptr_t crg_addr = PERI_CRG_MMC_P4_DLL;
189 unsigned int reg;
190
191 reg = readl(crg_addr);
192 reg |= CRG_P4_DLL_SRST_REQ;
193 writel(reg, crg_addr);
194 }
195
hisi_dll_reset_deassert(void)196 static void hisi_dll_reset_deassert(void)
197 {
198 const uintptr_t crg_addr = PERI_CRG_MMC_P4_DLL;
199 unsigned int reg;
200
201 reg = readl(crg_addr);
202 reg &= ~CRG_P4_DLL_SRST_REQ;
203 writel(reg, crg_addr);
204 }
205
hisi_wait_p4_dll_lock(void)206 static void hisi_wait_p4_dll_lock(void)
207 {
208 const uintptr_t reg_addr = PERI_CRG_MMC_STAT;
209 unsigned int timeout = 20;
210 unsigned int reg;
211
212 do {
213 reg = readl(reg_addr);
214 if (reg & CRG_P4_DLL_LOCKED)
215 return;
216
217 udelay(1000); /* delay 1000 us */
218 timeout--;
219 } while (timeout > 0);
220
221 printf("sdhci-hisi: P4 DLL master not locked.\n");
222 }
223
hisi_wait_ds_dll_ready(void)224 static void hisi_wait_ds_dll_ready(void)
225 {
226 const uintptr_t reg_addr = PERI_CRG_MMC_STAT;
227 unsigned int timeout = 20;
228 unsigned int reg;
229
230 do {
231 reg = readl(reg_addr);
232 if (reg & CRG_DS_DLL_READY)
233 return;
234
235 udelay(1000); /* delay 1000 us */
236 timeout--;
237 } while (timeout > 0);
238
239 printf("sdhci-hisi: DS DLL slave not ready.\n");
240 }
241
hisi_mmc_priv_init(struct sdhci_host * host)242 static void hisi_mmc_priv_init(struct sdhci_host *host)
243 {
244 unsigned int reg;
245
246 reg = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
247 reg &= ~SDHCI_UNDEFL_INCR_EN;
248 sdhci_writel(host, reg, SDHCI_AXI_MBIIU_CTRL);
249
250 reg = sdhci_readl(host, SDHCI_EMMC_CTRL);
251 reg |= SDHCI_CARD_IS_EMMC;
252 sdhci_writel(host, reg, SDHCI_EMMC_CTRL);
253 }
254
get_mmc_bus_width(void)255 static unsigned int get_mmc_bus_width(void)
256 {
257 unsigned int sys_stat;
258 unsigned int bus_width;
259
260 sys_stat = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT);
261
262 if ((sys_stat & BOOT_FLAG_MASK) == BOOT_FROM_NAND_FLAG) {
263 /* up to 4 bit mode support when spi nand start up */
264 bus_width = MMC_BUS_WIDTH_4_BIT;
265 } else {
266 bus_width = (sys_stat & EMMC_BOOT_8BIT) ?
267 MMC_BUS_WIDTH_8_BIT : MMC_BUS_WIDTH_4_BIT;
268 }
269
270 return bus_width;
271 }
272
hisi_set_drv_str(unsigned int offset,unsigned int drv_str)273 static void hisi_set_drv_str(unsigned int offset, unsigned int drv_str)
274 {
275 unsigned int reg;
276 const uintptr_t io_addr = REG_IO_CFG_BASE + offset;
277
278 reg = readl(io_addr);
279 reg &= ~IO_CFG_SDIO_MASK;
280 reg |= drv_str;
281 writel(reg, io_addr);
282 }
283
hisi_mmc_set_ioconfig(struct sdhci_host * host)284 static void hisi_mmc_set_ioconfig(struct sdhci_host *host)
285 {
286 unsigned int selected_mode = host->mmc->selected_mode;
287 unsigned int bus_width;
288 unsigned int i;
289
290 bus_width = get_mmc_bus_width();
291
292 hisi_set_drv_str(REG_MMC_CLK_IO, hisi_mmc_io_cfg[selected_mode][IO_CLK]);
293 hisi_set_drv_str(REG_MMC_CMD_IO, hisi_mmc_io_cfg[selected_mode][IO_CMD]);
294 for (i = 0; i < bus_width; i++)
295 hisi_set_drv_str(reg_data_io[i],
296 hisi_mmc_io_cfg[selected_mode][IO_DATA]);
297 hisi_set_drv_str(REG_MMC_RST_IO, hisi_mmc_io_cfg[selected_mode][IO_RST]);
298
299 if (selected_mode == MMC_HS_400 ||
300 selected_mode == MMC_HS_400_ES)
301 hisi_set_drv_str(REG_MMC_DQS_IO,
302 hisi_mmc_io_cfg[selected_mode][IO_DS]);
303
304 sdhci_set_uhs_timing(host);
305 }
306
hisi_set_phase(struct sdhci_host * host)307 static void hisi_set_phase(struct sdhci_host *host)
308 {
309 unsigned int drv_phase, sample_phase;
310 unsigned int selected_mode = host->mmc->selected_mode;
311
312 if (selected_mode == MMC_HS_400 ||
313 selected_mode == MMC_HS_200)
314 sample_phase = host->tuning_phase;
315 else
316 sample_phase = hisi_phase_cfg[selected_mode][SAMPLE];
317
318 drv_phase = hisi_phase_cfg[selected_mode][DRIVE];
319
320 hisi_set_drv_phase(host, drv_phase);
321 hisi_enable_sample(host);
322 hisi_set_sampl_phase(host, sample_phase);
323
324 udelay(25); /* delay 25us */
325 }
326
hisi_set_crg(struct sdhci_host * host,unsigned int clk)327 static void hisi_set_crg(struct sdhci_host *host, unsigned int clk)
328 {
329 const uintptr_t crg_addr = PERI_CRG_MMC_CLK;
330 unsigned int sel, reg;
331 unsigned int clk_mux[] = {
332 CLK_400K, CLK_24P75M, CLK_49P5M,
333 CLK_99M, CLK_148P5M
334 };
335
336 for (sel = 0x4; sel > 0; sel--) {
337 if (clk >= clk_mux[sel])
338 break;
339 }
340
341 reg = readl(crg_addr);
342 reg &= ~CRG_CLK_SEL_MASK;
343 reg |= mmc_clk_sel(sel);
344 writel(reg, crg_addr);
345 }
346
hisi_mmc_set_clk(struct sdhci_host * host,unsigned int clk)347 static int hisi_mmc_set_clk(struct sdhci_host *host, unsigned int clk)
348 {
349 hisi_disable_card_clk(host);
350 udelay(25); /* delay 25 us */
351 hisi_disable_internal_clk(host);
352
353 if (clk == 0)
354 return 0;
355
356 hisi_set_crg(host, clk);
357 hisi_set_phase(host);
358
359 udelay(5); /* delay 5 us */
360
361 hisi_enable_internal_clk(host);
362
363 if ((host->mmc->selected_mode == MMC_HS_400) ||
364 (host->mmc->selected_mode == MMC_HS_400_ES) ||
365 (host->mmc->selected_mode == MMC_HS_200)) {
366 hisi_dll_reset_assert();
367 hisi_dll_reset_deassert();
368 hisi_wait_p4_dll_lock();
369 hisi_wait_sampl_dll_slave_ready(host);
370 }
371
372 if ((host->mmc->selected_mode == MMC_HS_400) ||
373 (host->mmc->selected_mode == MMC_HS_400_ES))
374 hisi_wait_ds_dll_ready();
375
376 hisi_enable_card_clk(host);
377 udelay(75); /* delay 75 us */
378
379 return 0;
380 }
381
hisi_set_pin_mux(unsigned int offset,unsigned int pin_mux)382 static void hisi_set_pin_mux(unsigned int offset, unsigned int pin_mux)
383 {
384 unsigned int reg;
385 const uintptr_t io_addr = REG_IO_CFG_BASE + offset;
386
387 reg = readl(io_addr);
388 reg &= ~IO_MUX_MASK;
389 reg |= pin_mux;
390 writel(reg, io_addr);
391 }
392
mmc_pin_mux_config(int is_emmc)393 static void mmc_pin_mux_config(int is_emmc)
394 {
395 unsigned int bus_width, pin_mux, i;
396
397 if (is_emmc) {
398 bus_width = get_mmc_bus_width();
399 pin_mux = MMC_IO_MUX;
400 } else {
401 bus_width = MMC_BUS_WIDTH_4_BIT;
402 pin_mux = SD_IO_MUX;
403 }
404
405 hisi_set_pin_mux(REG_MMC_CLK_IO, pin_mux);
406 hisi_set_pin_mux(REG_MMC_CMD_IO, pin_mux);
407 for (i = 0; i < bus_width; i++)
408 hisi_set_pin_mux(reg_data_io[i], pin_mux);
409 /* REG_MMC_RST_IO & SDIO_CARD_POWER_EN_N is the same pin */
410 hisi_set_pin_mux(REG_MMC_RST_IO, pin_mux);
411
412 if (bus_width == MMC_BUS_WIDTH_8_BIT)
413 hisi_set_pin_mux(REG_MMC_DQS_IO, MMC_IO_MUX);
414 }
415
hisi_mmc_crg_init(void)416 static void hisi_mmc_crg_init(void)
417 {
418 unsigned int reg;
419
420 /* eMMC clk enable */
421 reg = readl(PERI_CRG_MMC_CLK);
422 reg |= CRG_CLK_EN | CRG_AHB_CLK_EN;
423 writel(reg, PERI_CRG_MMC_CLK);
424
425 /* eMMC reset assert */
426 reg = readl(PERI_CRG_MMC_CLK);
427 reg |= CRG_DLL_SRST_REQ;
428 writel(reg, PERI_CRG_MMC_CLK);
429 udelay(25); /* delay 25us */
430
431 /* eMMC reset deassert */
432 reg = readl(PERI_CRG_MMC_CLK);
433 reg &= ~CRG_DLL_SRST_REQ;
434 writel(reg, PERI_CRG_MMC_CLK);
435 udelay(1); /* delay 1us */
436 }
437
438 #define DEVICE_TYPE_EMMC 1
439 #define DEVICE_TYPE_SD 0
440
emmc_hardware_init(void)441 static int emmc_hardware_init(void)
442 {
443 mmc_pin_mux_config(DEVICE_TYPE_EMMC);
444 if (!get_ocr_from_bootrom())
445 hisi_mmc_crg_init();
446 return 0;
447 }
448
sd_hardware_init(void)449 static int sd_hardware_init(void)
450 {
451 mmc_pin_mux_config(DEVICE_TYPE_SD);
452 hisi_mmc_crg_init();
453 return 0;
454 }
455
456