1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 */
18
19 /* CRG register */
20 #define PERI_CRG_MMC_CLK (CRG_REG_BASE + 0x34c0)
21 #define CRG_CLK_SEL_SHIFT 24
22 #define CRG_CLK_SEL_MASK (0x7 << CRG_CLK_SEL_SHIFT)
23 #define CRG_DLL_SRST_REQ (1 << 16)
24 #define CRG_CLK_EN (1 << 0)
25 #define CRG_AHB_CLK_EN (2 << 0)
26
27 #define PERI_CRG_MMC_P4_DLL (CRG_REG_BASE + 0x34c4)
28 #define CRG_P4_DLL_SRST_REQ (1 << 1)
29
30 #define PERI_CRG_MMC_DRV_DLL (CRG_REG_BASE + 0x34c8)
31 #define CRG_DRV_PHASE_SEL_SHIFT 15
32 #define CRG_DRV_PHASE_SEL_MASK (0x1F << 15)
33
34 #define PERI_CRG_MMC_STAT (CRG_REG_BASE + 0x34d8)
35 #define CRG_SAM_DLL_READY (1 << 12)
36 #define CRG_DS_DLL_READY (1 << 10)
37 #define CRG_P4_DLL_LOCKED (1 << 9)
38
39 #define REG_EMMC_SAMPL_DLL_STATUS PERI_CRG_MMC_STAT
40 #define REG_SDIO0_SAMPL_DLL_STATUS PERI_CRG_MMC_STAT
41 #define SDIO_SAMPL_DLL_SLAVE_READY CRG_SAM_DLL_READY
42
43 #define REG_EMMC_DRV_DLL_CTRL PERI_CRG_MMC_DRV_DLL
44 #define REG_SDIO0_DRV_DLL_CTRL PERI_CRG_MMC_DRV_DLL
45 #define SDIO_DRV_PHASE_SEL_MASK CRG_DRV_PHASE_SEL_MASK
46 #define sdio_drv_sel(phase) ((phase) << CRG_DRV_PHASE_SEL_SHIFT)
47
48 #define REG_EMMC_SAMPLB_DLL_CTRL 0x34d4
49 #define SDIO_SAMPLB_DLL_CLK_MASK 0xf
50 #define sdio_samplb_sel(phase) (((phase) & 0xf) << 0)
51
52 /* eMMC io reg */
53 #define REG_IO_CFG_BASE 0x10FF0000
54 #define REG_MMC_CLK_IO 0x10
55 #define REG_MMC_CMD_IO 0x14
56 #define REG_MMC_D0_IO 0x00
57 #define REG_MMC_D1_IO 0x04
58 #define REG_MMC_D2_IO 0x08
59 #define REG_MMC_D3_IO 0x0c
60 #define REG_MMC_D4_IO 0x1c
61 #define REG_MMC_D6_IO 0x20
62 #define REG_MMC_D5_IO 0x28
63 #define REG_MMC_D7_IO 0x2C
64 #define REG_MMC_DQS_IO 0x30
65 #define REG_MMC_RST_IO 0x18
66
67 /* IO CFG */
68 #define IO_CFG_DRV_STR_MASK (0xf << 4)
69 #define io_cfg_drv_str_sel(str) ((str) << 4)
70 #define IO_CFG_PULL_UP (0x1 << 8)
71 #define IO_CFG_PULL_DOWN (0x1 << 9)
72 #define IO_CFG_SR (0x1 << 10)
73 #define IO_CFG_SDIO_MASK (IO_CFG_DRV_STR_MASK | IO_CFG_PULL_UP |\
74 IO_CFG_PULL_DOWN | IO_CFG_SR)
75 #define MMC_IO_MUX 0x2
76 #define IO_MUX_MASK 0x3
77 #define MMC_BUS_WIDTH_4_BIT 4
78 #define MMC_BUS_WIDTH_8_BIT 8
79 #define BOOT_FROM_NAND_FLAG (0x1 << 2)
80 #define BOOT_FLAG_MASK (0x3 << 2)
81 #define EMMC_BOOT_8BIT (0x1 << 11)
82
83 #define IO_CLK 0
84 #define IO_CMD 1
85 #define IO_DATA 2
86 #define IO_RST 3
87 #define IO_DS 4
88 #define EMMC_IO_TYPE_NUM 5
89
90 static unsigned int reg_data_io[] = {
91 REG_MMC_D0_IO, REG_MMC_D1_IO,
92 REG_MMC_D2_IO, REG_MMC_D3_IO,
93 REG_MMC_D4_IO, REG_MMC_D5_IO,
94 REG_MMC_D6_IO, REG_MMC_D7_IO
95 };
96
97 static u32 hisi_mmc_io_cfg[][EMMC_IO_TYPE_NUM] = {
98 [MMC_LEGACY] = {
99 io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
100 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
101 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
102 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
103 },
104 [MMC_HS] = {
105 io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
106 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
107 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
108 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
109 },
110 [MMC_HS_52] = {
111 io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN,
112 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
113 io_cfg_drv_str_sel(0xe) | IO_CFG_PULL_UP,
114 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
115 },
116 [MMC_HS_200] = {
117 io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
118 io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
119 io_cfg_drv_str_sel(0xc) | IO_CFG_PULL_UP,
120 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP
121 },
122 [MMC_HS_400] = {
123 io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
124 io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_UP,
125 io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_UP,
126 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP,
127 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_DOWN
128 },
129 [MMC_HS_400_ES] = {
130 io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN,
131 io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_UP,
132 io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_UP,
133 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP,
134 io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_DOWN
135 }
136 };
137
138 /* avaliable frequency */
139 #define CLK_400K 400000
140 #define CLK_24P75M 24750000
141 #define CLK_49P5M 49500000
142 #define CLK_99M 99000000
143 #define CLK_148P5M 148500000
144 #define CLK_175M 175000000
145 #define CLK_196P5M 196500000
146
147 /* sample drive phase */
148 #define DRIVE 0
149 #define SAMPLE 1
150 #define PHASE_TYPE_NUM 2
151
152 static u32 hisi_phase_cfg[][PHASE_TYPE_NUM] = {
153 [MMC_LEGACY] = { 16, 0 },
154 [MMC_HS] = { 16, 4 },
155 [MMC_HS_52] = { 16, 4 },
156 [MMC_HS_200] = { 22, 0 },
157 [MMC_HS_400] = { 9, 0 },
158 [MMC_HS_400_ES] = { 9, 0 }
159 };
160
get_ocr_from_bootrom(void)161 unsigned int get_ocr_from_bootrom(void)
162 {
163 return readl(REG_SAVE_HCS);
164 }
165
hisi_wait_drv_dll_lock(struct sdhci_host * host)166 void hisi_wait_drv_dll_lock(struct sdhci_host *host)
167 {
168 /* doing nothing */
169 }
170
hisi_enable_sampl_dll_slave(struct sdhci_host * host)171 void hisi_enable_sampl_dll_slave(struct sdhci_host *host)
172 {
173 /* doing nothing */
174 }
175
hisi_dll_reset_assert(void)176 static void hisi_dll_reset_assert(void)
177 {
178 const uintptr_t crg_addr = PERI_CRG_MMC_P4_DLL;
179 unsigned int reg;
180
181 reg = readl(crg_addr);
182 reg |= CRG_P4_DLL_SRST_REQ;
183 writel(reg, crg_addr);
184 }
185
hisi_dll_reset_deassert(void)186 static void hisi_dll_reset_deassert(void)
187 {
188 const uintptr_t crg_addr = PERI_CRG_MMC_P4_DLL;
189 unsigned int reg;
190
191 reg = readl(crg_addr);
192 reg &= ~CRG_P4_DLL_SRST_REQ;
193 writel(reg, crg_addr);
194 }
195
hisi_wait_p4_dll_lock(void)196 static void hisi_wait_p4_dll_lock(void)
197 {
198 const uintptr_t reg_addr = PERI_CRG_MMC_STAT;
199 unsigned int timeout = 20;
200 unsigned int reg;
201
202 do {
203 reg = readl(reg_addr);
204 if (reg & CRG_P4_DLL_LOCKED)
205 return;
206
207 udelay(1000); /* delay 1000 us */
208 timeout--;
209 } while (timeout > 0);
210
211 printf("sdhci-hisi: P4 DLL master not locked.\n");
212 }
213
hisi_wait_ds_dll_ready(void)214 static void hisi_wait_ds_dll_ready(void)
215 {
216 const uintptr_t reg_addr = PERI_CRG_MMC_STAT;
217 unsigned int timeout = 20;
218 unsigned int reg;
219
220 do {
221 reg = readl(reg_addr);
222 if (reg & CRG_DS_DLL_READY)
223 return;
224
225 udelay(1000); /* delay 1000 us */
226 timeout--;
227 } while (timeout > 0);
228
229 printf("sdhci-hisi: DS DLL slave not ready.\n");
230 }
231
hisi_mmc_priv_init(struct sdhci_host * host)232 static void hisi_mmc_priv_init(struct sdhci_host *host)
233 {
234 unsigned int reg;
235
236 reg = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
237 reg &= ~SDHCI_UNDEFL_INCR_EN;
238 sdhci_writel(host, reg, SDHCI_AXI_MBIIU_CTRL);
239
240 reg = sdhci_readl(host, SDHCI_EMMC_CTRL);
241 reg |= SDHCI_CARD_IS_EMMC;
242 sdhci_writel(host, reg, SDHCI_EMMC_CTRL);
243 }
244
get_mmc_bus_width(void)245 static unsigned int get_mmc_bus_width(void)
246 {
247 unsigned int sys_stat;
248 unsigned int bus_width;
249
250 sys_stat = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT);
251
252 if ((sys_stat & BOOT_FLAG_MASK) == BOOT_FROM_NAND_FLAG) {
253 /* up to 4 bit mode support when spi nand start up */
254 bus_width = MMC_BUS_WIDTH_4_BIT;
255 } else {
256 bus_width = (sys_stat & EMMC_BOOT_8BIT) ?
257 MMC_BUS_WIDTH_8_BIT : MMC_BUS_WIDTH_4_BIT;
258 }
259
260 return bus_width;
261 }
262
hisi_set_drv_str(unsigned int offset,unsigned int drv_str)263 static void hisi_set_drv_str(unsigned int offset, unsigned int drv_str)
264 {
265 unsigned int reg;
266 const uintptr_t io_addr = REG_IO_CFG_BASE + offset;
267
268 reg = readl(io_addr);
269 reg &= ~IO_CFG_SDIO_MASK;
270 reg |= drv_str;
271 writel(reg, io_addr);
272 }
273
hisi_mmc_set_ioconfig(struct sdhci_host * host)274 static void hisi_mmc_set_ioconfig(struct sdhci_host *host)
275 {
276 unsigned int selected_mode = host->mmc->selected_mode;
277 unsigned int bus_width;
278 unsigned int i;
279
280 bus_width = get_mmc_bus_width();
281
282 hisi_set_drv_str(REG_MMC_CLK_IO, hisi_mmc_io_cfg[selected_mode][IO_CLK]);
283 hisi_set_drv_str(REG_MMC_CMD_IO, hisi_mmc_io_cfg[selected_mode][IO_CMD]);
284 for (i = 0; i < bus_width; i++)
285 hisi_set_drv_str(reg_data_io[i],
286 hisi_mmc_io_cfg[selected_mode][IO_DATA]);
287 hisi_set_drv_str(REG_MMC_RST_IO, hisi_mmc_io_cfg[selected_mode][IO_RST]);
288
289 if (selected_mode == MMC_HS_400 ||
290 selected_mode == MMC_HS_400_ES)
291 hisi_set_drv_str(REG_MMC_DQS_IO,
292 hisi_mmc_io_cfg[selected_mode][IO_DS]);
293
294 sdhci_set_uhs_timing(host);
295 }
296
hisi_set_phase(struct sdhci_host * host)297 static void hisi_set_phase(struct sdhci_host *host)
298 {
299 unsigned int drv_phase, sample_phase;
300 unsigned int selected_mode = host->mmc->selected_mode;
301
302 if (selected_mode == MMC_HS_400 ||
303 selected_mode == MMC_HS_200)
304 sample_phase = host->tuning_phase;
305 else
306 sample_phase = hisi_phase_cfg[selected_mode][SAMPLE];
307
308 drv_phase = hisi_phase_cfg[selected_mode][DRIVE];
309
310 hisi_set_drv_phase(host, drv_phase);
311 hisi_enable_sample(host);
312 hisi_set_sampl_phase(host, sample_phase);
313
314 udelay(25); /* delay 25us */
315 }
316
hisi_set_crg(struct sdhci_host * host,unsigned int clk)317 static void hisi_set_crg(struct sdhci_host *host, unsigned int clk)
318 {
319 const uintptr_t crg_addr = PERI_CRG_MMC_CLK;
320 unsigned int sel, reg;
321 unsigned int clk_mux[] = {
322 CLK_400K, CLK_24P75M, CLK_49P5M,
323 CLK_99M, CLK_148P5M, CLK_175M, CLK_196P5M
324 };
325
326 for (sel = 0x6; sel > 0; sel--) {
327 if (clk >= clk_mux[sel])
328 break;
329 }
330
331 reg = readl(crg_addr);
332 reg &= ~CRG_CLK_SEL_MASK;
333 reg |= mmc_clk_sel(sel);
334 writel(reg, crg_addr);
335 }
336
hisi_mmc_set_clk(struct sdhci_host * host,unsigned int clk)337 static int hisi_mmc_set_clk(struct sdhci_host *host, unsigned int clk)
338 {
339 hisi_disable_card_clk(host);
340 udelay(25); /* delay 25 us */
341 hisi_disable_internal_clk(host);
342
343 if (clk == 0)
344 return 0;
345
346 hisi_set_crg(host, clk);
347 hisi_set_phase(host);
348
349 udelay(5); /* delay 5 us */
350
351 hisi_enable_internal_clk(host);
352
353 if ((host->mmc->selected_mode == MMC_HS_400) ||
354 (host->mmc->selected_mode == MMC_HS_400_ES) ||
355 (host->mmc->selected_mode == MMC_HS_200)) {
356 hisi_dll_reset_assert();
357 hisi_dll_reset_deassert();
358 hisi_wait_p4_dll_lock();
359 hisi_wait_sampl_dll_slave_ready(host);
360 }
361
362 if ((host->mmc->selected_mode == MMC_HS_400) ||
363 (host->mmc->selected_mode == MMC_HS_400_ES))
364 hisi_wait_ds_dll_ready();
365
366 hisi_enable_card_clk(host);
367 udelay(75); /* delay 75 us */
368
369 return 0;
370 }
371
hisi_set_pin_mux(unsigned int offset,unsigned int pin_mux)372 static void hisi_set_pin_mux(unsigned int offset, unsigned int pin_mux)
373 {
374 unsigned int reg;
375 const uintptr_t io_addr = REG_IO_CFG_BASE + offset;
376
377 reg = readl(io_addr);
378 reg &= ~IO_MUX_MASK;
379 reg |= pin_mux;
380 writel(reg, io_addr);
381 }
382
emmc_pin_mux_config(void)383 static void emmc_pin_mux_config(void)
384 {
385 unsigned int bus_width, i;
386
387 bus_width = get_mmc_bus_width();
388
389 hisi_set_pin_mux(REG_MMC_CLK_IO, MMC_IO_MUX);
390 hisi_set_pin_mux(REG_MMC_CMD_IO, MMC_IO_MUX);
391 for (i = 0; i < bus_width; i++)
392 hisi_set_pin_mux(reg_data_io[i], MMC_IO_MUX);
393 hisi_set_pin_mux(REG_MMC_RST_IO, MMC_IO_MUX);
394
395 if (bus_width == MMC_BUS_WIDTH_8_BIT)
396 hisi_set_pin_mux(REG_MMC_DQS_IO, MMC_IO_MUX);
397 }
398
hisi_mmc_crg_init(void)399 static void hisi_mmc_crg_init(void)
400 {
401 unsigned int reg;
402
403 /* eMMC clk enable */
404 reg = readl(PERI_CRG_MMC_CLK);
405 reg |= CRG_CLK_EN | CRG_AHB_CLK_EN;
406 writel(reg, PERI_CRG_MMC_CLK);
407
408 /* eMMC reset assert */
409 reg = readl(PERI_CRG_MMC_CLK);
410 reg |= CRG_DLL_SRST_REQ;
411 writel(reg, PERI_CRG_MMC_CLK);
412 udelay(25); /* delay 25us */
413
414 /* eMMC reset deassert */
415 reg = readl(PERI_CRG_MMC_CLK);
416 reg &= ~CRG_DLL_SRST_REQ;
417 writel(reg, PERI_CRG_MMC_CLK);
418 udelay(1); /* delay 1us */
419 }
420
emmc_hardware_init(void)421 static int emmc_hardware_init(void)
422 {
423 emmc_pin_mux_config();
424 if (!get_ocr_from_bootrom())
425 hisi_mmc_crg_init();
426 return 0;
427 }
428
sd_hardware_init(void)429 static int sd_hardware_init(void)
430 {
431 printf("sdhci-hisi: sd card not support, should not be here !\n");
432 return 0;
433 }
434