1 /*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25 #include <config.h>
26 #include <common.h>
27 #include <cpu_func.h>
28 #include <malloc.h>
29 #include <memalign.h>
30 #include <mmc.h>
31 #include <part.h>
32 #include <i2c.h>
33 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
34 #include <palmas.h>
35 #endif
36 #include <asm/io.h>
37 #include <asm/arch/mmc_host_def.h>
38 #ifdef CONFIG_OMAP54XX
39 #include <asm/arch/mux_dra7xx.h>
40 #include <asm/arch/dra7xx_iodelay.h>
41 #endif
42 #if !defined(CONFIG_SOC_KEYSTONE)
43 #include <asm/gpio.h>
44 #include <asm/arch/sys_proto.h>
45 #endif
46 #ifdef CONFIG_MMC_OMAP36XX_PINS
47 #include <asm/arch/mux.h>
48 #endif
49 #include <dm.h>
50 #include <power/regulator.h>
51 #include <thermal.h>
52
53 DECLARE_GLOBAL_DATA_PTR;
54
55 /* simplify defines to OMAP_HSMMC_USE_GPIO */
56 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
57 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
58 #define OMAP_HSMMC_USE_GPIO
59 #else
60 #undef OMAP_HSMMC_USE_GPIO
61 #endif
62
63 /* common definitions for all OMAPs */
64 #define SYSCTL_SRC (1 << 25)
65 #define SYSCTL_SRD (1 << 26)
66
67 #ifdef CONFIG_IODELAY_RECALIBRATION
68 struct omap_hsmmc_pinctrl_state {
69 struct pad_conf_entry *padconf;
70 int npads;
71 struct iodelay_cfg_entry *iodelay;
72 int niodelays;
73 };
74 #endif
75
76 struct omap_hsmmc_data {
77 struct hsmmc *base_addr;
78 #if !CONFIG_IS_ENABLED(DM_MMC)
79 struct mmc_config cfg;
80 #endif
81 uint bus_width;
82 uint clock;
83 ushort last_cmd;
84 #ifdef OMAP_HSMMC_USE_GPIO
85 #if CONFIG_IS_ENABLED(DM_MMC)
86 struct gpio_desc cd_gpio; /* Change Detect GPIO */
87 struct gpio_desc wp_gpio; /* Write Protect GPIO */
88 #else
89 int cd_gpio;
90 int wp_gpio;
91 #endif
92 #endif
93 #if CONFIG_IS_ENABLED(DM_MMC)
94 enum bus_mode mode;
95 #endif
96 u8 controller_flags;
97 #ifdef CONFIG_MMC_OMAP_HS_ADMA
98 struct omap_hsmmc_adma_desc *adma_desc_table;
99 uint desc_slot;
100 #endif
101 const char *hw_rev;
102 struct udevice *pbias_supply;
103 uint signal_voltage;
104 #ifdef CONFIG_IODELAY_RECALIBRATION
105 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
106 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
107 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
108 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
109 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
110 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
111 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
112 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
113 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
114 #endif
115 };
116
117 struct omap_mmc_of_data {
118 u8 controller_flags;
119 };
120
121 #ifdef CONFIG_MMC_OMAP_HS_ADMA
122 struct omap_hsmmc_adma_desc {
123 u8 attr;
124 u8 reserved;
125 u16 len;
126 u32 addr;
127 };
128
129 #define ADMA_MAX_LEN 63488
130
131 /* Decriptor table defines */
132 #define ADMA_DESC_ATTR_VALID BIT(0)
133 #define ADMA_DESC_ATTR_END BIT(1)
134 #define ADMA_DESC_ATTR_INT BIT(2)
135 #define ADMA_DESC_ATTR_ACT1 BIT(4)
136 #define ADMA_DESC_ATTR_ACT2 BIT(5)
137
138 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
139 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
140 #endif
141
142 /* If we fail after 1 second wait, something is really bad */
143 #define MAX_RETRY_MS 1000
144 #define MMC_TIMEOUT_MS 20
145
146 /* DMA transfers can take a long time if a lot a data is transferred.
147 * The timeout must take in account the amount of data. Let's assume
148 * that the time will never exceed 333 ms per MB (in other word we assume
149 * that the bandwidth is always above 3MB/s).
150 */
151 #define DMA_TIMEOUT_PER_MB 333
152 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
153 #define OMAP_HSMMC_NO_1_8_V BIT(1)
154 #define OMAP_HSMMC_USE_ADMA BIT(2)
155 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
156
157 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
158 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
159 unsigned int siz);
160 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
161 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
162 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
163
omap_hsmmc_get_data(struct mmc * mmc)164 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
165 {
166 #if CONFIG_IS_ENABLED(DM_MMC)
167 return dev_get_priv(mmc->dev);
168 #else
169 return (struct omap_hsmmc_data *)mmc->priv;
170 #endif
171 }
omap_hsmmc_get_cfg(struct mmc * mmc)172 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
173 {
174 #if CONFIG_IS_ENABLED(DM_MMC)
175 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
176 return &plat->cfg;
177 #else
178 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
179 #endif
180 }
181
182 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
omap_mmc_setup_gpio_in(int gpio,const char * label)183 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
184 {
185 int ret;
186
187 #ifndef CONFIG_DM_GPIO
188 if (!gpio_is_valid(gpio))
189 return -1;
190 #endif
191 ret = gpio_request(gpio, label);
192 if (ret)
193 return ret;
194
195 ret = gpio_direction_input(gpio);
196 if (ret)
197 return ret;
198
199 return gpio;
200 }
201 #endif
202
mmc_board_init(struct mmc * mmc)203 static unsigned char mmc_board_init(struct mmc *mmc)
204 {
205 #if defined(CONFIG_OMAP34XX)
206 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
207 t2_t *t2_base = (t2_t *)T2_BASE;
208 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
209 u32 pbias_lite;
210 #ifdef CONFIG_MMC_OMAP36XX_PINS
211 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
212 #endif
213
214 pbias_lite = readl(&t2_base->pbias_lite);
215 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
216 #ifdef CONFIG_TARGET_OMAP3_CAIRO
217 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
218 pbias_lite &= ~PBIASLITEVMODE0;
219 #endif
220 #ifdef CONFIG_TARGET_OMAP3_LOGIC
221 /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
222 pbias_lite &= ~PBIASLITEVMODE1;
223 #endif
224 #ifdef CONFIG_MMC_OMAP36XX_PINS
225 if (get_cpu_family() == CPU_OMAP36XX) {
226 /* Disable extended drain IO before changing PBIAS */
227 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
228 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
229 }
230 #endif
231 writel(pbias_lite, &t2_base->pbias_lite);
232
233 writel(pbias_lite | PBIASLITEPWRDNZ1 |
234 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
235 &t2_base->pbias_lite);
236
237 #ifdef CONFIG_MMC_OMAP36XX_PINS
238 if (get_cpu_family() == CPU_OMAP36XX)
239 /* Enable extended drain IO after changing PBIAS */
240 writel(wkup_ctrl |
241 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
242 OMAP34XX_CTRL_WKUP_CTRL);
243 #endif
244 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
245 &t2_base->devconf0);
246
247 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
248 &t2_base->devconf1);
249
250 /* Change from default of 52MHz to 26MHz if necessary */
251 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
252 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
253 &t2_base->ctl_prog_io1);
254
255 writel(readl(&prcm_base->fclken1_core) |
256 EN_MMC1 | EN_MMC2 | EN_MMC3,
257 &prcm_base->fclken1_core);
258
259 writel(readl(&prcm_base->iclken1_core) |
260 EN_MMC1 | EN_MMC2 | EN_MMC3,
261 &prcm_base->iclken1_core);
262 #endif
263
264 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
265 !CONFIG_IS_ENABLED(DM_REGULATOR)
266 /* PBIAS config needed for MMC1 only */
267 if (mmc_get_blk_desc(mmc)->devnum == 0)
268 vmmc_pbias_config(LDO_VOLT_3V3);
269 #endif
270
271 return 0;
272 }
273
mmc_init_stream(struct hsmmc * mmc_base)274 void mmc_init_stream(struct hsmmc *mmc_base)
275 {
276 ulong start;
277
278 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
279
280 writel(MMC_CMD0, &mmc_base->cmd);
281 start = get_timer(0);
282 while (!(readl(&mmc_base->stat) & CC_MASK)) {
283 if (get_timer(0) - start > MAX_RETRY_MS) {
284 printf("%s: timedout waiting for cc!\n", __func__);
285 return;
286 }
287 }
288 writel(CC_MASK, &mmc_base->stat)
289 ;
290 writel(MMC_CMD0, &mmc_base->cmd)
291 ;
292 start = get_timer(0);
293 while (!(readl(&mmc_base->stat) & CC_MASK)) {
294 if (get_timer(0) - start > MAX_RETRY_MS) {
295 printf("%s: timedout waiting for cc2!\n", __func__);
296 return;
297 }
298 }
299 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
300 }
301
302 #if CONFIG_IS_ENABLED(DM_MMC)
303 #ifdef CONFIG_IODELAY_RECALIBRATION
omap_hsmmc_io_recalibrate(struct mmc * mmc)304 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
305 {
306 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
307 struct omap_hsmmc_pinctrl_state *pinctrl_state;
308
309 switch (priv->mode) {
310 case MMC_HS_200:
311 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
312 break;
313 case UHS_SDR104:
314 pinctrl_state = priv->sdr104_pinctrl_state;
315 break;
316 case UHS_SDR50:
317 pinctrl_state = priv->sdr50_pinctrl_state;
318 break;
319 case UHS_DDR50:
320 pinctrl_state = priv->ddr50_pinctrl_state;
321 break;
322 case UHS_SDR25:
323 pinctrl_state = priv->sdr25_pinctrl_state;
324 break;
325 case UHS_SDR12:
326 pinctrl_state = priv->sdr12_pinctrl_state;
327 break;
328 case SD_HS:
329 case MMC_HS:
330 case MMC_HS_52:
331 pinctrl_state = priv->hs_pinctrl_state;
332 break;
333 case MMC_DDR_52:
334 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
335 default:
336 pinctrl_state = priv->default_pinctrl_state;
337 break;
338 }
339
340 if (!pinctrl_state)
341 pinctrl_state = priv->default_pinctrl_state;
342
343 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
344 if (pinctrl_state->iodelay)
345 late_recalibrate_iodelay(pinctrl_state->padconf,
346 pinctrl_state->npads,
347 pinctrl_state->iodelay,
348 pinctrl_state->niodelays);
349 else
350 do_set_mux32((*ctrl)->control_padconf_core_base,
351 pinctrl_state->padconf,
352 pinctrl_state->npads);
353 }
354 }
355 #endif
omap_hsmmc_set_timing(struct mmc * mmc)356 static void omap_hsmmc_set_timing(struct mmc *mmc)
357 {
358 u32 val;
359 struct hsmmc *mmc_base;
360 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
361
362 mmc_base = priv->base_addr;
363
364 omap_hsmmc_stop_clock(mmc_base);
365 val = readl(&mmc_base->ac12);
366 val &= ~AC12_UHSMC_MASK;
367 priv->mode = mmc->selected_mode;
368
369 if (mmc_is_mode_ddr(priv->mode))
370 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
371 else
372 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
373
374 switch (priv->mode) {
375 case MMC_HS_200:
376 case UHS_SDR104:
377 val |= AC12_UHSMC_SDR104;
378 break;
379 case UHS_SDR50:
380 val |= AC12_UHSMC_SDR50;
381 break;
382 case MMC_DDR_52:
383 case UHS_DDR50:
384 val |= AC12_UHSMC_DDR50;
385 break;
386 case SD_HS:
387 case MMC_HS_52:
388 case UHS_SDR25:
389 val |= AC12_UHSMC_SDR25;
390 break;
391 case MMC_LEGACY:
392 case MMC_HS:
393 case SD_LEGACY:
394 case UHS_SDR12:
395 val |= AC12_UHSMC_SDR12;
396 break;
397 default:
398 val |= AC12_UHSMC_RES;
399 break;
400 }
401 writel(val, &mmc_base->ac12);
402
403 #ifdef CONFIG_IODELAY_RECALIBRATION
404 omap_hsmmc_io_recalibrate(mmc);
405 #endif
406 omap_hsmmc_start_clock(mmc_base);
407 }
408
omap_hsmmc_conf_bus_power(struct mmc * mmc,uint signal_voltage)409 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
410 {
411 struct hsmmc *mmc_base;
412 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
413 u32 hctl, ac12;
414
415 mmc_base = priv->base_addr;
416
417 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
418 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
419
420 switch (signal_voltage) {
421 case MMC_SIGNAL_VOLTAGE_330:
422 hctl |= SDVS_3V3;
423 break;
424 case MMC_SIGNAL_VOLTAGE_180:
425 hctl |= SDVS_1V8;
426 ac12 |= AC12_V1V8_SIGEN;
427 break;
428 }
429
430 writel(hctl, &mmc_base->hctl);
431 writel(ac12, &mmc_base->ac12);
432 }
433
omap_hsmmc_wait_dat0(struct udevice * dev,int state,int timeout_us)434 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
435 {
436 int ret = -ETIMEDOUT;
437 u32 con;
438 bool dat0_high;
439 bool target_dat0_high = !!state;
440 struct omap_hsmmc_data *priv = dev_get_priv(dev);
441 struct hsmmc *mmc_base = priv->base_addr;
442
443 con = readl(&mmc_base->con);
444 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
445
446 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
447 while (timeout_us--) {
448 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
449 if (dat0_high == target_dat0_high) {
450 ret = 0;
451 break;
452 }
453 udelay(10);
454 }
455 writel(con, &mmc_base->con);
456
457 return ret;
458 }
459
460 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
461 #if CONFIG_IS_ENABLED(DM_REGULATOR)
omap_hsmmc_set_io_regulator(struct mmc * mmc,int mV)462 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
463 {
464 int ret = 0;
465 int uV = mV * 1000;
466
467 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
468
469 if (!mmc->vqmmc_supply)
470 return 0;
471
472 /* Disable PBIAS */
473 ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
474 if (ret)
475 return ret;
476
477 /* Turn off IO voltage */
478 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
479 if (ret)
480 return ret;
481 /* Program a new IO voltage value */
482 ret = regulator_set_value(mmc->vqmmc_supply, uV);
483 if (ret)
484 return ret;
485 /* Turn on IO voltage */
486 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
487 if (ret)
488 return ret;
489
490 /* Program PBIAS voltage*/
491 ret = regulator_set_value(priv->pbias_supply, uV);
492 if (ret && ret != -ENOSYS)
493 return ret;
494 /* Enable PBIAS */
495 ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
496 if (ret)
497 return ret;
498
499 return 0;
500 }
501 #endif
502
omap_hsmmc_set_signal_voltage(struct mmc * mmc)503 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
504 {
505 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
506 struct hsmmc *mmc_base = priv->base_addr;
507 int mv = mmc_voltage_to_mv(mmc->signal_voltage);
508 u32 capa_mask;
509 __maybe_unused u8 palmas_ldo_volt;
510 u32 val;
511
512 if (mv < 0)
513 return -EINVAL;
514
515 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
516 mv = 3300;
517 capa_mask = VS33_3V3SUP;
518 palmas_ldo_volt = LDO_VOLT_3V3;
519 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
520 capa_mask = VS18_1V8SUP;
521 palmas_ldo_volt = LDO_VOLT_1V8;
522 } else {
523 return -EOPNOTSUPP;
524 }
525
526 val = readl(&mmc_base->capa);
527 if (!(val & capa_mask))
528 return -EOPNOTSUPP;
529
530 priv->signal_voltage = mmc->signal_voltage;
531
532 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
533
534 #if CONFIG_IS_ENABLED(DM_REGULATOR)
535 return omap_hsmmc_set_io_regulator(mmc, mv);
536 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
537 defined(CONFIG_PALMAS_POWER)
538 if (mmc_get_blk_desc(mmc)->devnum == 0)
539 vmmc_pbias_config(palmas_ldo_volt);
540 return 0;
541 #else
542 return 0;
543 #endif
544 }
545 #endif
546
omap_hsmmc_set_capabilities(struct mmc * mmc)547 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
548 {
549 struct hsmmc *mmc_base;
550 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
551 u32 val;
552
553 mmc_base = priv->base_addr;
554 val = readl(&mmc_base->capa);
555
556 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
557 val |= (VS33_3V3SUP | VS18_1V8SUP);
558 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
559 val |= VS33_3V3SUP;
560 val &= ~VS18_1V8SUP;
561 } else {
562 val |= VS18_1V8SUP;
563 val &= ~VS33_3V3SUP;
564 }
565
566 writel(val, &mmc_base->capa);
567
568 return val;
569 }
570
571 #ifdef MMC_SUPPORTS_TUNING
omap_hsmmc_disable_tuning(struct mmc * mmc)572 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
573 {
574 struct hsmmc *mmc_base;
575 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
576 u32 val;
577
578 mmc_base = priv->base_addr;
579 val = readl(&mmc_base->ac12);
580 val &= ~(AC12_SCLK_SEL);
581 writel(val, &mmc_base->ac12);
582
583 val = readl(&mmc_base->dll);
584 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
585 writel(val, &mmc_base->dll);
586 }
587
omap_hsmmc_set_dll(struct mmc * mmc,int count)588 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
589 {
590 int i;
591 struct hsmmc *mmc_base;
592 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
593 u32 val;
594
595 mmc_base = priv->base_addr;
596 val = readl(&mmc_base->dll);
597 val |= DLL_FORCE_VALUE;
598 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
599 val |= (count << DLL_FORCE_SR_C_SHIFT);
600 writel(val, &mmc_base->dll);
601
602 val |= DLL_CALIB;
603 writel(val, &mmc_base->dll);
604 for (i = 0; i < 1000; i++) {
605 if (readl(&mmc_base->dll) & DLL_CALIB)
606 break;
607 }
608 val &= ~DLL_CALIB;
609 writel(val, &mmc_base->dll);
610 }
611
omap_hsmmc_execute_tuning(struct udevice * dev,uint opcode)612 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
613 {
614 struct omap_hsmmc_data *priv = dev_get_priv(dev);
615 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
616 struct mmc *mmc = upriv->mmc;
617 struct hsmmc *mmc_base;
618 u32 val;
619 u8 cur_match, prev_match = 0;
620 int ret;
621 u32 phase_delay = 0;
622 u32 start_window = 0, max_window = 0;
623 u32 length = 0, max_len = 0;
624 bool single_point_failure = false;
625 struct udevice *thermal_dev;
626 int temperature;
627 int i;
628
629 mmc_base = priv->base_addr;
630 val = readl(&mmc_base->capa2);
631
632 /* clock tuning is not needed for upto 52MHz */
633 if (!((mmc->selected_mode == MMC_HS_200) ||
634 (mmc->selected_mode == UHS_SDR104) ||
635 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
636 return 0;
637
638 ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
639 if (ret) {
640 printf("Couldn't get thermal device for tuning\n");
641 return ret;
642 }
643 ret = thermal_get_temp(thermal_dev, &temperature);
644 if (ret) {
645 printf("Couldn't get temperature for tuning\n");
646 return ret;
647 }
648 val = readl(&mmc_base->dll);
649 val |= DLL_SWT;
650 writel(val, &mmc_base->dll);
651
652 /*
653 * Stage 1: Search for a maximum pass window ignoring any
654 * any single point failures. If the tuning value ends up
655 * near it, move away from it in stage 2 below
656 */
657 while (phase_delay <= MAX_PHASE_DELAY) {
658 omap_hsmmc_set_dll(mmc, phase_delay);
659
660 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
661
662 if (cur_match) {
663 if (prev_match) {
664 length++;
665 } else if (single_point_failure) {
666 /* ignore single point failure */
667 length++;
668 single_point_failure = false;
669 } else {
670 start_window = phase_delay;
671 length = 1;
672 }
673 } else {
674 single_point_failure = prev_match;
675 }
676
677 if (length > max_len) {
678 max_window = start_window;
679 max_len = length;
680 }
681
682 prev_match = cur_match;
683 phase_delay += 4;
684 }
685
686 if (!max_len) {
687 ret = -EIO;
688 goto tuning_error;
689 }
690
691 val = readl(&mmc_base->ac12);
692 if (!(val & AC12_SCLK_SEL)) {
693 ret = -EIO;
694 goto tuning_error;
695 }
696 /*
697 * Assign tuning value as a ratio of maximum pass window based
698 * on temperature
699 */
700 if (temperature < -20000)
701 phase_delay = min(max_window + 4 * max_len - 24,
702 max_window +
703 DIV_ROUND_UP(13 * max_len, 16) * 4);
704 else if (temperature < 20000)
705 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
706 else if (temperature < 40000)
707 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
708 else if (temperature < 70000)
709 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
710 else if (temperature < 90000)
711 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
712 else if (temperature < 120000)
713 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
714 else
715 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
716
717 /*
718 * Stage 2: Search for a single point failure near the chosen tuning
719 * value in two steps. First in the +3 to +10 range and then in the
720 * +2 to -10 range. If found, move away from it in the appropriate
721 * direction by the appropriate amount depending on the temperature.
722 */
723 for (i = 3; i <= 10; i++) {
724 omap_hsmmc_set_dll(mmc, phase_delay + i);
725 if (mmc_send_tuning(mmc, opcode, NULL)) {
726 if (temperature < 10000)
727 phase_delay += i + 6;
728 else if (temperature < 20000)
729 phase_delay += i - 12;
730 else if (temperature < 70000)
731 phase_delay += i - 8;
732 else if (temperature < 90000)
733 phase_delay += i - 6;
734 else
735 phase_delay += i - 6;
736
737 goto single_failure_found;
738 }
739 }
740
741 for (i = 2; i >= -10; i--) {
742 omap_hsmmc_set_dll(mmc, phase_delay + i);
743 if (mmc_send_tuning(mmc, opcode, NULL)) {
744 if (temperature < 10000)
745 phase_delay += i + 12;
746 else if (temperature < 20000)
747 phase_delay += i + 8;
748 else if (temperature < 70000)
749 phase_delay += i + 8;
750 else if (temperature < 90000)
751 phase_delay += i + 10;
752 else
753 phase_delay += i + 12;
754
755 goto single_failure_found;
756 }
757 }
758
759 single_failure_found:
760
761 omap_hsmmc_set_dll(mmc, phase_delay);
762
763 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
764 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
765
766 return 0;
767
768 tuning_error:
769
770 omap_hsmmc_disable_tuning(mmc);
771 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
772 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
773
774 return ret;
775 }
776 #endif
777 #endif
778
mmc_enable_irq(struct mmc * mmc,struct mmc_cmd * cmd)779 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
780 {
781 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
782 struct hsmmc *mmc_base = priv->base_addr;
783 u32 irq_mask = INT_EN_MASK;
784
785 /*
786 * TODO: Errata i802 indicates only DCRC interrupts can occur during
787 * tuning procedure and DCRC should be disabled. But see occurences
788 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
789 * interrupts occur along with BRR, so the data is actually in the
790 * buffer. It has to be debugged why these interrutps occur
791 */
792 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
793 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
794
795 writel(irq_mask, &mmc_base->ie);
796 }
797
omap_hsmmc_init_setup(struct mmc * mmc)798 static int omap_hsmmc_init_setup(struct mmc *mmc)
799 {
800 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
801 struct hsmmc *mmc_base;
802 unsigned int reg_val;
803 unsigned int dsor;
804 ulong start;
805
806 mmc_base = priv->base_addr;
807 mmc_board_init(mmc);
808
809 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
810 &mmc_base->sysconfig);
811 start = get_timer(0);
812 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
813 if (get_timer(0) - start > MAX_RETRY_MS) {
814 printf("%s: timedout waiting for cc2!\n", __func__);
815 return -ETIMEDOUT;
816 }
817 }
818 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
819 start = get_timer(0);
820 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
821 if (get_timer(0) - start > MAX_RETRY_MS) {
822 printf("%s: timedout waiting for softresetall!\n",
823 __func__);
824 return -ETIMEDOUT;
825 }
826 }
827 #ifdef CONFIG_MMC_OMAP_HS_ADMA
828 reg_val = readl(&mmc_base->hl_hwinfo);
829 if (reg_val & MADMA_EN)
830 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
831 #endif
832
833 #if CONFIG_IS_ENABLED(DM_MMC)
834 reg_val = omap_hsmmc_set_capabilities(mmc);
835 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
836 MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
837 #else
838 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
839 writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
840 &mmc_base->capa);
841 #endif
842
843 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
844
845 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
846 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
847 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
848
849 dsor = 240;
850 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
851 (ICE_STOP | DTO_15THDTO));
852 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
853 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
854 start = get_timer(0);
855 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
856 if (get_timer(0) - start > MAX_RETRY_MS) {
857 printf("%s: timedout waiting for ics!\n", __func__);
858 return -ETIMEDOUT;
859 }
860 }
861 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
862
863 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
864
865 mmc_enable_irq(mmc, NULL);
866
867 #if !CONFIG_IS_ENABLED(DM_MMC)
868 mmc_init_stream(mmc_base);
869 #endif
870
871 return 0;
872 }
873
874 /*
875 * MMC controller internal finite state machine reset
876 *
877 * Used to reset command or data internal state machines, using respectively
878 * SRC or SRD bit of SYSCTL register
879 */
mmc_reset_controller_fsm(struct hsmmc * mmc_base,u32 bit)880 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
881 {
882 ulong start;
883
884 mmc_reg_out(&mmc_base->sysctl, bit, bit);
885
886 /*
887 * CMD(DAT) lines reset procedures are slightly different
888 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
889 * According to OMAP3 TRM:
890 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
891 * returns to 0x0.
892 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
893 * procedure steps must be as follows:
894 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
895 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
896 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
897 * 3. Wait until the SRC (SRD) bit returns to 0x0
898 * (reset procedure is completed).
899 */
900 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
901 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
902 if (!(readl(&mmc_base->sysctl) & bit)) {
903 start = get_timer(0);
904 while (!(readl(&mmc_base->sysctl) & bit)) {
905 if (get_timer(0) - start > MMC_TIMEOUT_MS)
906 return;
907 }
908 }
909 #endif
910 start = get_timer(0);
911 while ((readl(&mmc_base->sysctl) & bit) != 0) {
912 if (get_timer(0) - start > MAX_RETRY_MS) {
913 printf("%s: timedout waiting for sysctl %x to clear\n",
914 __func__, bit);
915 return;
916 }
917 }
918 }
919
920 #ifdef CONFIG_MMC_OMAP_HS_ADMA
omap_hsmmc_adma_desc(struct mmc * mmc,char * buf,u16 len,bool end)921 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
922 {
923 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
924 struct omap_hsmmc_adma_desc *desc;
925 u8 attr;
926
927 desc = &priv->adma_desc_table[priv->desc_slot];
928
929 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
930 if (!end)
931 priv->desc_slot++;
932 else
933 attr |= ADMA_DESC_ATTR_END;
934
935 desc->len = len;
936 desc->addr = (u32)buf;
937 desc->reserved = 0;
938 desc->attr = attr;
939 }
940
omap_hsmmc_prepare_adma_table(struct mmc * mmc,struct mmc_data * data)941 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
942 struct mmc_data *data)
943 {
944 uint total_len = data->blocksize * data->blocks;
945 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
946 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
947 int i = desc_count;
948 char *buf;
949
950 priv->desc_slot = 0;
951 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
952 memalign(ARCH_DMA_MINALIGN, desc_count *
953 sizeof(struct omap_hsmmc_adma_desc));
954
955 if (data->flags & MMC_DATA_READ)
956 buf = data->dest;
957 else
958 buf = (char *)data->src;
959
960 while (--i) {
961 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
962 buf += ADMA_MAX_LEN;
963 total_len -= ADMA_MAX_LEN;
964 }
965
966 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
967
968 flush_dcache_range((long)priv->adma_desc_table,
969 (long)priv->adma_desc_table +
970 ROUND(desc_count *
971 sizeof(struct omap_hsmmc_adma_desc),
972 ARCH_DMA_MINALIGN));
973 }
974
omap_hsmmc_prepare_data(struct mmc * mmc,struct mmc_data * data)975 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
976 {
977 struct hsmmc *mmc_base;
978 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
979 u32 val;
980 char *buf;
981
982 mmc_base = priv->base_addr;
983 omap_hsmmc_prepare_adma_table(mmc, data);
984
985 if (data->flags & MMC_DATA_READ)
986 buf = data->dest;
987 else
988 buf = (char *)data->src;
989
990 val = readl(&mmc_base->hctl);
991 val |= DMA_SELECT;
992 writel(val, &mmc_base->hctl);
993
994 val = readl(&mmc_base->con);
995 val |= DMA_MASTER;
996 writel(val, &mmc_base->con);
997
998 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
999
1000 flush_dcache_range((u32)buf,
1001 (u32)buf +
1002 ROUND(data->blocksize * data->blocks,
1003 ARCH_DMA_MINALIGN));
1004 }
1005
omap_hsmmc_dma_cleanup(struct mmc * mmc)1006 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1007 {
1008 struct hsmmc *mmc_base;
1009 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1010 u32 val;
1011
1012 mmc_base = priv->base_addr;
1013
1014 val = readl(&mmc_base->con);
1015 val &= ~DMA_MASTER;
1016 writel(val, &mmc_base->con);
1017
1018 val = readl(&mmc_base->hctl);
1019 val &= ~DMA_SELECT;
1020 writel(val, &mmc_base->hctl);
1021
1022 kfree(priv->adma_desc_table);
1023 }
1024 #else
1025 #define omap_hsmmc_adma_desc
1026 #define omap_hsmmc_prepare_adma_table
1027 #define omap_hsmmc_prepare_data
1028 #define omap_hsmmc_dma_cleanup
1029 #endif
1030
1031 #if !CONFIG_IS_ENABLED(DM_MMC)
omap_hsmmc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)1032 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1033 struct mmc_data *data)
1034 {
1035 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1036 #else
1037 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1038 struct mmc_data *data)
1039 {
1040 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1041 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1042 struct mmc *mmc = upriv->mmc;
1043 #endif
1044 struct hsmmc *mmc_base;
1045 unsigned int flags, mmc_stat;
1046 ulong start;
1047 priv->last_cmd = cmd->cmdidx;
1048
1049 mmc_base = priv->base_addr;
1050
1051 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1052 return 0;
1053
1054 start = get_timer(0);
1055 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1056 if (get_timer(0) - start > MAX_RETRY_MS) {
1057 printf("%s: timedout waiting on cmd inhibit to clear\n",
1058 __func__);
1059 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1060 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1061 return -ETIMEDOUT;
1062 }
1063 }
1064 writel(0xFFFFFFFF, &mmc_base->stat);
1065 if (readl(&mmc_base->stat)) {
1066 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1067 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1068 }
1069
1070 /*
1071 * CMDREG
1072 * CMDIDX[13:8] : Command index
1073 * DATAPRNT[5] : Data Present Select
1074 * ENCMDIDX[4] : Command Index Check Enable
1075 * ENCMDCRC[3] : Command CRC Check Enable
1076 * RSPTYP[1:0]
1077 * 00 = No Response
1078 * 01 = Length 136
1079 * 10 = Length 48
1080 * 11 = Length 48 Check busy after response
1081 */
1082 /* Delay added before checking the status of frq change
1083 * retry not supported by mmc.c(core file)
1084 */
1085 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1086 udelay(50000); /* wait 50 ms */
1087
1088 if (!(cmd->resp_type & MMC_RSP_PRESENT))
1089 flags = 0;
1090 else if (cmd->resp_type & MMC_RSP_136)
1091 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1092 else if (cmd->resp_type & MMC_RSP_BUSY)
1093 flags = RSP_TYPE_LGHT48B;
1094 else
1095 flags = RSP_TYPE_LGHT48;
1096
1097 /* enable default flags */
1098 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1099 MSBS_SGLEBLK);
1100 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1101
1102 if (cmd->resp_type & MMC_RSP_CRC)
1103 flags |= CCCE_CHECK;
1104 if (cmd->resp_type & MMC_RSP_OPCODE)
1105 flags |= CICE_CHECK;
1106
1107 if (data) {
1108 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1109 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1110 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1111 data->blocksize = 512;
1112 writel(data->blocksize | (data->blocks << 16),
1113 &mmc_base->blk);
1114 } else
1115 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1116
1117 if (data->flags & MMC_DATA_READ)
1118 flags |= (DP_DATA | DDIR_READ);
1119 else
1120 flags |= (DP_DATA | DDIR_WRITE);
1121
1122 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1123 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1124 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1125 omap_hsmmc_prepare_data(mmc, data);
1126 flags |= DE_ENABLE;
1127 }
1128 #endif
1129 }
1130
1131 mmc_enable_irq(mmc, cmd);
1132
1133 writel(cmd->cmdarg, &mmc_base->arg);
1134 udelay(20); /* To fix "No status update" error on eMMC */
1135 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1136
1137 start = get_timer(0);
1138 do {
1139 mmc_stat = readl(&mmc_base->stat);
1140 if (get_timer(start) > MAX_RETRY_MS) {
1141 printf("%s : timeout: No status update\n", __func__);
1142 return -ETIMEDOUT;
1143 }
1144 } while (!mmc_stat);
1145
1146 if ((mmc_stat & IE_CTO) != 0) {
1147 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1148 return -ETIMEDOUT;
1149 } else if ((mmc_stat & ERRI_MASK) != 0)
1150 return -1;
1151
1152 if (mmc_stat & CC_MASK) {
1153 writel(CC_MASK, &mmc_base->stat);
1154 if (cmd->resp_type & MMC_RSP_PRESENT) {
1155 if (cmd->resp_type & MMC_RSP_136) {
1156 /* response type 2 */
1157 cmd->response[3] = readl(&mmc_base->rsp10);
1158 cmd->response[2] = readl(&mmc_base->rsp32);
1159 cmd->response[1] = readl(&mmc_base->rsp54);
1160 cmd->response[0] = readl(&mmc_base->rsp76);
1161 } else
1162 /* response types 1, 1b, 3, 4, 5, 6 */
1163 cmd->response[0] = readl(&mmc_base->rsp10);
1164 }
1165 }
1166
1167 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1168 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1169 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1170 u32 sz_mb, timeout;
1171
1172 if (mmc_stat & IE_ADMAE) {
1173 omap_hsmmc_dma_cleanup(mmc);
1174 return -EIO;
1175 }
1176
1177 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
1178 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1179 if (timeout < MAX_RETRY_MS)
1180 timeout = MAX_RETRY_MS;
1181
1182 start = get_timer(0);
1183 do {
1184 mmc_stat = readl(&mmc_base->stat);
1185 if (mmc_stat & TC_MASK) {
1186 writel(readl(&mmc_base->stat) | TC_MASK,
1187 &mmc_base->stat);
1188 break;
1189 }
1190 if (get_timer(start) > timeout) {
1191 printf("%s : DMA timeout: No status update\n",
1192 __func__);
1193 return -ETIMEDOUT;
1194 }
1195 } while (1);
1196
1197 omap_hsmmc_dma_cleanup(mmc);
1198 return 0;
1199 }
1200 #endif
1201
1202 if (data && (data->flags & MMC_DATA_READ)) {
1203 mmc_read_data(mmc_base, data->dest,
1204 data->blocksize * data->blocks);
1205 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1206 mmc_write_data(mmc_base, data->src,
1207 data->blocksize * data->blocks);
1208 }
1209 return 0;
1210 }
1211
1212 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1213 {
1214 unsigned int *output_buf = (unsigned int *)buf;
1215 unsigned int mmc_stat;
1216 unsigned int count;
1217
1218 /*
1219 * Start Polled Read
1220 */
1221 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1222 count /= 4;
1223
1224 while (size) {
1225 ulong start = get_timer(0);
1226 do {
1227 mmc_stat = readl(&mmc_base->stat);
1228 if (get_timer(0) - start > MAX_RETRY_MS) {
1229 printf("%s: timedout waiting for status!\n",
1230 __func__);
1231 return -ETIMEDOUT;
1232 }
1233 } while (mmc_stat == 0);
1234
1235 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1236 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1237
1238 if ((mmc_stat & ERRI_MASK) != 0)
1239 return 1;
1240
1241 if (mmc_stat & BRR_MASK) {
1242 unsigned int k;
1243
1244 writel(readl(&mmc_base->stat) | BRR_MASK,
1245 &mmc_base->stat);
1246 for (k = 0; k < count; k++) {
1247 *output_buf = readl(&mmc_base->data);
1248 output_buf++;
1249 }
1250 size -= (count*4);
1251 }
1252
1253 if (mmc_stat & BWR_MASK)
1254 writel(readl(&mmc_base->stat) | BWR_MASK,
1255 &mmc_base->stat);
1256
1257 if (mmc_stat & TC_MASK) {
1258 writel(readl(&mmc_base->stat) | TC_MASK,
1259 &mmc_base->stat);
1260 break;
1261 }
1262 }
1263 return 0;
1264 }
1265
1266 #if CONFIG_IS_ENABLED(MMC_WRITE)
1267 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1268 unsigned int size)
1269 {
1270 unsigned int *input_buf = (unsigned int *)buf;
1271 unsigned int mmc_stat;
1272 unsigned int count;
1273
1274 /*
1275 * Start Polled Write
1276 */
1277 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1278 count /= 4;
1279
1280 while (size) {
1281 ulong start = get_timer(0);
1282 do {
1283 mmc_stat = readl(&mmc_base->stat);
1284 if (get_timer(0) - start > MAX_RETRY_MS) {
1285 printf("%s: timedout waiting for status!\n",
1286 __func__);
1287 return -ETIMEDOUT;
1288 }
1289 } while (mmc_stat == 0);
1290
1291 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1292 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1293
1294 if ((mmc_stat & ERRI_MASK) != 0)
1295 return 1;
1296
1297 if (mmc_stat & BWR_MASK) {
1298 unsigned int k;
1299
1300 writel(readl(&mmc_base->stat) | BWR_MASK,
1301 &mmc_base->stat);
1302 for (k = 0; k < count; k++) {
1303 writel(*input_buf, &mmc_base->data);
1304 input_buf++;
1305 }
1306 size -= (count*4);
1307 }
1308
1309 if (mmc_stat & BRR_MASK)
1310 writel(readl(&mmc_base->stat) | BRR_MASK,
1311 &mmc_base->stat);
1312
1313 if (mmc_stat & TC_MASK) {
1314 writel(readl(&mmc_base->stat) | TC_MASK,
1315 &mmc_base->stat);
1316 break;
1317 }
1318 }
1319 return 0;
1320 }
1321 #else
1322 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1323 unsigned int size)
1324 {
1325 return -ENOTSUPP;
1326 }
1327 #endif
1328 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1329 {
1330 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1331 }
1332
1333 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1334 {
1335 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1336 }
1337
1338 static void omap_hsmmc_set_clock(struct mmc *mmc)
1339 {
1340 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1341 struct hsmmc *mmc_base;
1342 unsigned int dsor = 0;
1343 ulong start;
1344
1345 mmc_base = priv->base_addr;
1346 omap_hsmmc_stop_clock(mmc_base);
1347
1348 /* TODO: Is setting DTO required here? */
1349 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1350 (ICE_STOP | DTO_15THDTO));
1351
1352 if (mmc->clock != 0) {
1353 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1354 if (dsor > CLKD_MAX)
1355 dsor = CLKD_MAX;
1356 } else {
1357 dsor = CLKD_MAX;
1358 }
1359
1360 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1361 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1362
1363 start = get_timer(0);
1364 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1365 if (get_timer(0) - start > MAX_RETRY_MS) {
1366 printf("%s: timedout waiting for ics!\n", __func__);
1367 return;
1368 }
1369 }
1370
1371 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1372 mmc->clock = priv->clock;
1373 omap_hsmmc_start_clock(mmc_base);
1374 }
1375
1376 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1377 {
1378 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1379 struct hsmmc *mmc_base;
1380
1381 mmc_base = priv->base_addr;
1382 /* configue bus width */
1383 switch (mmc->bus_width) {
1384 case 8:
1385 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1386 &mmc_base->con);
1387 break;
1388
1389 case 4:
1390 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1391 &mmc_base->con);
1392 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1393 &mmc_base->hctl);
1394 break;
1395
1396 case 1:
1397 default:
1398 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1399 &mmc_base->con);
1400 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1401 &mmc_base->hctl);
1402 break;
1403 }
1404
1405 priv->bus_width = mmc->bus_width;
1406 }
1407
1408 #if !CONFIG_IS_ENABLED(DM_MMC)
1409 static int omap_hsmmc_set_ios(struct mmc *mmc)
1410 {
1411 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1412 #else
1413 static int omap_hsmmc_set_ios(struct udevice *dev)
1414 {
1415 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1416 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1417 struct mmc *mmc = upriv->mmc;
1418 #endif
1419 struct hsmmc *mmc_base = priv->base_addr;
1420 int ret = 0;
1421
1422 if (priv->bus_width != mmc->bus_width)
1423 omap_hsmmc_set_bus_width(mmc);
1424
1425 if (priv->clock != mmc->clock)
1426 omap_hsmmc_set_clock(mmc);
1427
1428 if (mmc->clk_disable)
1429 omap_hsmmc_stop_clock(mmc_base);
1430 else
1431 omap_hsmmc_start_clock(mmc_base);
1432
1433 #if CONFIG_IS_ENABLED(DM_MMC)
1434 if (priv->mode != mmc->selected_mode)
1435 omap_hsmmc_set_timing(mmc);
1436
1437 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1438 if (priv->signal_voltage != mmc->signal_voltage)
1439 ret = omap_hsmmc_set_signal_voltage(mmc);
1440 #endif
1441 #endif
1442 return ret;
1443 }
1444
1445 #ifdef OMAP_HSMMC_USE_GPIO
1446 #if CONFIG_IS_ENABLED(DM_MMC)
1447 static int omap_hsmmc_getcd(struct udevice *dev)
1448 {
1449 int value = -1;
1450 #if CONFIG_IS_ENABLED(DM_GPIO)
1451 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1452 value = dm_gpio_get_value(&priv->cd_gpio);
1453 #endif
1454 /* if no CD return as 1 */
1455 if (value < 0)
1456 return 1;
1457
1458 return value;
1459 }
1460
1461 static int omap_hsmmc_getwp(struct udevice *dev)
1462 {
1463 int value = 0;
1464 #if CONFIG_IS_ENABLED(DM_GPIO)
1465 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1466 value = dm_gpio_get_value(&priv->wp_gpio);
1467 #endif
1468 /* if no WP return as 0 */
1469 if (value < 0)
1470 return 0;
1471 return value;
1472 }
1473 #else
1474 static int omap_hsmmc_getcd(struct mmc *mmc)
1475 {
1476 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1477 int cd_gpio;
1478
1479 /* if no CD return as 1 */
1480 cd_gpio = priv->cd_gpio;
1481 if (cd_gpio < 0)
1482 return 1;
1483
1484 /* NOTE: assumes card detect signal is active-low */
1485 return !gpio_get_value(cd_gpio);
1486 }
1487
1488 static int omap_hsmmc_getwp(struct mmc *mmc)
1489 {
1490 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1491 int wp_gpio;
1492
1493 /* if no WP return as 0 */
1494 wp_gpio = priv->wp_gpio;
1495 if (wp_gpio < 0)
1496 return 0;
1497
1498 /* NOTE: assumes write protect signal is active-high */
1499 return gpio_get_value(wp_gpio);
1500 }
1501 #endif
1502 #endif
1503
1504 #if CONFIG_IS_ENABLED(DM_MMC)
1505 static const struct dm_mmc_ops omap_hsmmc_ops = {
1506 .send_cmd = omap_hsmmc_send_cmd,
1507 .set_ios = omap_hsmmc_set_ios,
1508 #ifdef OMAP_HSMMC_USE_GPIO
1509 .get_cd = omap_hsmmc_getcd,
1510 .get_wp = omap_hsmmc_getwp,
1511 #endif
1512 #ifdef MMC_SUPPORTS_TUNING
1513 .execute_tuning = omap_hsmmc_execute_tuning,
1514 #endif
1515 .wait_dat0 = omap_hsmmc_wait_dat0,
1516 };
1517 #else
1518 static const struct mmc_ops omap_hsmmc_ops = {
1519 .send_cmd = omap_hsmmc_send_cmd,
1520 .set_ios = omap_hsmmc_set_ios,
1521 .init = omap_hsmmc_init_setup,
1522 #ifdef OMAP_HSMMC_USE_GPIO
1523 .getcd = omap_hsmmc_getcd,
1524 .getwp = omap_hsmmc_getwp,
1525 #endif
1526 };
1527 #endif
1528
1529 #if !CONFIG_IS_ENABLED(DM_MMC)
1530 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1531 int wp_gpio)
1532 {
1533 struct mmc *mmc;
1534 struct omap_hsmmc_data *priv;
1535 struct mmc_config *cfg;
1536 uint host_caps_val;
1537
1538 priv = calloc(1, sizeof(*priv));
1539 if (priv == NULL)
1540 return -1;
1541
1542 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1543
1544 switch (dev_index) {
1545 case 0:
1546 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1547 break;
1548 #ifdef OMAP_HSMMC2_BASE
1549 case 1:
1550 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1551 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1552 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1553 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1554 defined(CONFIG_HSMMC2_8BIT)
1555 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1556 host_caps_val |= MMC_MODE_8BIT;
1557 #endif
1558 break;
1559 #endif
1560 #ifdef OMAP_HSMMC3_BASE
1561 case 2:
1562 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1563 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1564 /* Enable 8-bit interface for eMMC on DRA7XX */
1565 host_caps_val |= MMC_MODE_8BIT;
1566 #endif
1567 break;
1568 #endif
1569 default:
1570 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1571 return 1;
1572 }
1573 #ifdef OMAP_HSMMC_USE_GPIO
1574 /* on error gpio values are set to -1, which is what we want */
1575 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1576 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1577 #endif
1578
1579 cfg = &priv->cfg;
1580
1581 cfg->name = "OMAP SD/MMC";
1582 cfg->ops = &omap_hsmmc_ops;
1583
1584 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1585 cfg->host_caps = host_caps_val & ~host_caps_mask;
1586
1587 cfg->f_min = 400000;
1588
1589 if (f_max != 0)
1590 cfg->f_max = f_max;
1591 else {
1592 if (cfg->host_caps & MMC_MODE_HS) {
1593 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1594 cfg->f_max = 52000000;
1595 else
1596 cfg->f_max = 26000000;
1597 } else
1598 cfg->f_max = 20000000;
1599 }
1600
1601 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1602
1603 #if defined(CONFIG_OMAP34XX)
1604 /*
1605 * Silicon revs 2.1 and older do not support multiblock transfers.
1606 */
1607 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1608 cfg->b_max = 1;
1609 #endif
1610
1611 mmc = mmc_create(cfg, priv);
1612 if (mmc == NULL)
1613 return -1;
1614
1615 return 0;
1616 }
1617 #else
1618
1619 #ifdef CONFIG_IODELAY_RECALIBRATION
1620 static struct pad_conf_entry *
1621 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1622 {
1623 int index = 0;
1624 struct pad_conf_entry *padconf;
1625
1626 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1627 if (!padconf) {
1628 debug("failed to allocate memory\n");
1629 return 0;
1630 }
1631
1632 while (index < count) {
1633 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1634 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1635 index++;
1636 }
1637
1638 return padconf;
1639 }
1640
1641 static struct iodelay_cfg_entry *
1642 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1643 {
1644 int index = 0;
1645 struct iodelay_cfg_entry *iodelay;
1646
1647 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1648 if (!iodelay) {
1649 debug("failed to allocate memory\n");
1650 return 0;
1651 }
1652
1653 while (index < count) {
1654 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1655 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1656 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1657 index++;
1658 }
1659
1660 return iodelay;
1661 }
1662
1663 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1664 const char *name, int *len)
1665 {
1666 const void *fdt = gd->fdt_blob;
1667 int offset;
1668 const fdt32_t *pinctrl;
1669
1670 offset = fdt_node_offset_by_phandle(fdt, phandle);
1671 if (offset < 0) {
1672 debug("failed to get pinctrl node %s.\n",
1673 fdt_strerror(offset));
1674 return 0;
1675 }
1676
1677 pinctrl = fdt_getprop(fdt, offset, name, len);
1678 if (!pinctrl) {
1679 debug("failed to get property %s\n", name);
1680 return 0;
1681 }
1682
1683 return pinctrl;
1684 }
1685
1686 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1687 char *prop_name)
1688 {
1689 const void *fdt = gd->fdt_blob;
1690 const __be32 *phandle;
1691 int node = dev_of_offset(mmc->dev);
1692
1693 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1694 if (!phandle) {
1695 debug("failed to get property %s\n", prop_name);
1696 return 0;
1697 }
1698
1699 return fdt32_to_cpu(*phandle);
1700 }
1701
1702 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1703 char *prop_name)
1704 {
1705 const void *fdt = gd->fdt_blob;
1706 const __be32 *phandle;
1707 int len;
1708 int count;
1709 int node = dev_of_offset(mmc->dev);
1710
1711 phandle = fdt_getprop(fdt, node, prop_name, &len);
1712 if (!phandle) {
1713 debug("failed to get property %s\n", prop_name);
1714 return 0;
1715 }
1716
1717 /* No manual mode iodelay values if count < 2 */
1718 count = len / sizeof(*phandle);
1719 if (count < 2)
1720 return 0;
1721
1722 return fdt32_to_cpu(*(phandle + 1));
1723 }
1724
1725 static struct pad_conf_entry *
1726 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1727 {
1728 int len;
1729 int count;
1730 struct pad_conf_entry *padconf;
1731 u32 phandle;
1732 const fdt32_t *pinctrl;
1733
1734 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1735 if (!phandle)
1736 return ERR_PTR(-EINVAL);
1737
1738 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1739 &len);
1740 if (!pinctrl)
1741 return ERR_PTR(-EINVAL);
1742
1743 count = (len / sizeof(*pinctrl)) / 2;
1744 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1745 if (!padconf)
1746 return ERR_PTR(-EINVAL);
1747
1748 *npads = count;
1749
1750 return padconf;
1751 }
1752
1753 static struct iodelay_cfg_entry *
1754 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1755 {
1756 int len;
1757 int count;
1758 struct iodelay_cfg_entry *iodelay;
1759 u32 phandle;
1760 const fdt32_t *pinctrl;
1761
1762 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1763 /* Not all modes have manual mode iodelay values. So its not fatal */
1764 if (!phandle)
1765 return 0;
1766
1767 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1768 &len);
1769 if (!pinctrl)
1770 return ERR_PTR(-EINVAL);
1771
1772 count = (len / sizeof(*pinctrl)) / 3;
1773 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1774 if (!iodelay)
1775 return ERR_PTR(-EINVAL);
1776
1777 *niodelay = count;
1778
1779 return iodelay;
1780 }
1781
1782 static struct omap_hsmmc_pinctrl_state *
1783 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1784 {
1785 int index;
1786 int npads = 0;
1787 int niodelays = 0;
1788 const void *fdt = gd->fdt_blob;
1789 int node = dev_of_offset(mmc->dev);
1790 char prop_name[11];
1791 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1792
1793 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1794 malloc(sizeof(*pinctrl_state));
1795 if (!pinctrl_state) {
1796 debug("failed to allocate memory\n");
1797 return 0;
1798 }
1799
1800 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1801 if (index < 0) {
1802 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1803 goto err_pinctrl_state;
1804 }
1805
1806 sprintf(prop_name, "pinctrl-%d", index);
1807
1808 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1809 &npads);
1810 if (IS_ERR(pinctrl_state->padconf))
1811 goto err_pinctrl_state;
1812 pinctrl_state->npads = npads;
1813
1814 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1815 &niodelays);
1816 if (IS_ERR(pinctrl_state->iodelay))
1817 goto err_padconf;
1818 pinctrl_state->niodelays = niodelays;
1819
1820 return pinctrl_state;
1821
1822 err_padconf:
1823 kfree(pinctrl_state->padconf);
1824
1825 err_pinctrl_state:
1826 kfree(pinctrl_state);
1827 return 0;
1828 }
1829
1830 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1831 do { \
1832 struct omap_hsmmc_pinctrl_state *s = NULL; \
1833 char str[20]; \
1834 if (!(cfg->host_caps & capmask)) \
1835 break; \
1836 \
1837 if (priv->hw_rev) { \
1838 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1839 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1840 } \
1841 \
1842 if (!s) \
1843 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1844 \
1845 if (!s && !optional) { \
1846 debug("%s: no pinctrl for %s\n", \
1847 mmc->dev->name, #mode); \
1848 cfg->host_caps &= ~(capmask); \
1849 } else { \
1850 priv->mode##_pinctrl_state = s; \
1851 } \
1852 } while (0)
1853
1854 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1855 {
1856 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1857 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1858 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1859
1860 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1861 return 0;
1862
1863 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1864 if (!default_pinctrl) {
1865 printf("no pinctrl state for default mode\n");
1866 return -EINVAL;
1867 }
1868
1869 priv->default_pinctrl_state = default_pinctrl;
1870
1871 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1872 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1873 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1874 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1875 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1876
1877 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1878 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1879 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1880
1881 return 0;
1882 }
1883 #endif
1884
1885 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1886 #ifdef CONFIG_OMAP54XX
1887 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1888 {
1889 return NULL;
1890 }
1891 #endif
1892
1893 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1894 {
1895 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1896 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1897
1898 struct mmc_config *cfg = &plat->cfg;
1899 #ifdef CONFIG_OMAP54XX
1900 const struct mmc_platform_fixups *fixups;
1901 #endif
1902 const void *fdt = gd->fdt_blob;
1903 int node = dev_of_offset(dev);
1904 int ret;
1905
1906 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1907 sizeof(struct hsmmc *),
1908 MAP_NOCACHE);
1909
1910 ret = mmc_of_parse(dev, cfg);
1911 if (ret < 0)
1912 return ret;
1913
1914 if (!cfg->f_max)
1915 cfg->f_max = 52000000;
1916 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1917 cfg->f_min = 400000;
1918 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1919 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1920 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1921 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1922 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1923 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1924 if (of_data)
1925 plat->controller_flags |= of_data->controller_flags;
1926
1927 #ifdef CONFIG_OMAP54XX
1928 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1929 if (fixups) {
1930 plat->hw_rev = fixups->hw_rev;
1931 cfg->host_caps &= ~fixups->unsupported_caps;
1932 cfg->f_max = fixups->max_freq;
1933 }
1934 #endif
1935
1936 return 0;
1937 }
1938 #endif
1939
1940 #ifdef CONFIG_BLK
1941
1942 static int omap_hsmmc_bind(struct udevice *dev)
1943 {
1944 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1945 plat->mmc = calloc(1, sizeof(struct mmc));
1946 return mmc_bind(dev, plat->mmc, &plat->cfg);
1947 }
1948 #endif
1949 static int omap_hsmmc_probe(struct udevice *dev)
1950 {
1951 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1952 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1953 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1954 struct mmc_config *cfg = &plat->cfg;
1955 struct mmc *mmc;
1956 #ifdef CONFIG_IODELAY_RECALIBRATION
1957 int ret;
1958 #endif
1959
1960 cfg->name = "OMAP SD/MMC";
1961 priv->base_addr = plat->base_addr;
1962 priv->controller_flags = plat->controller_flags;
1963 priv->hw_rev = plat->hw_rev;
1964
1965 #ifdef CONFIG_BLK
1966 mmc = plat->mmc;
1967 #else
1968 mmc = mmc_create(cfg, priv);
1969 if (mmc == NULL)
1970 return -1;
1971 #endif
1972 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1973 device_get_supply_regulator(dev, "pbias-supply",
1974 &priv->pbias_supply);
1975 #endif
1976 #if defined(OMAP_HSMMC_USE_GPIO)
1977 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1978 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1979 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1980 #endif
1981 #endif
1982
1983 mmc->dev = dev;
1984 upriv->mmc = mmc;
1985
1986 #ifdef CONFIG_IODELAY_RECALIBRATION
1987 ret = omap_hsmmc_get_pinctrl_state(mmc);
1988 /*
1989 * disable high speed modes for the platforms that require IO delay
1990 * and for which we don't have this information
1991 */
1992 if ((ret < 0) &&
1993 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1994 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1995 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1996 UHS_CAPS);
1997 }
1998 #endif
1999
2000 return omap_hsmmc_init_setup(mmc);
2001 }
2002
2003 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2004
2005 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2006 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2007 };
2008
2009 static const struct udevice_id omap_hsmmc_ids[] = {
2010 { .compatible = "ti,omap3-hsmmc" },
2011 { .compatible = "ti,omap4-hsmmc" },
2012 { .compatible = "ti,am33xx-hsmmc" },
2013 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2014 { }
2015 };
2016 #endif
2017
2018 U_BOOT_DRIVER(omap_hsmmc) = {
2019 .name = "omap_hsmmc",
2020 .id = UCLASS_MMC,
2021 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2022 .of_match = omap_hsmmc_ids,
2023 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2024 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2025 #endif
2026 #ifdef CONFIG_BLK
2027 .bind = omap_hsmmc_bind,
2028 #endif
2029 .ops = &omap_hsmmc_ops,
2030 .probe = omap_hsmmc_probe,
2031 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2032 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2033 .flags = DM_FLAG_PRE_RELOC,
2034 #endif
2035 };
2036 #endif
2037