1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ENETC ethernet controller driver
4 * Copyright 2017-2019 NXP
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <memalign.h>
11 #include <asm/io.h>
12 #include <pci.h>
13 #include <miiphy.h>
14
15 #include "fsl_enetc.h"
16
17 /*
18 * Bind the device:
19 * - set a more explicit name on the interface
20 */
enetc_bind(struct udevice * dev)21 static int enetc_bind(struct udevice *dev)
22 {
23 char name[16];
24 static int eth_num_devices;
25
26 /*
27 * prefer using PCI function numbers to number interfaces, but these
28 * are only available if dts nodes are present. For PCI they are
29 * optional, handle that case too. Just in case some nodes are present
30 * and some are not, use different naming scheme - enetc-N based on
31 * PCI function # and enetc#N based on interface count
32 */
33 if (ofnode_valid(dev->node))
34 sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
35 else
36 sprintf(name, "enetc#%u", eth_num_devices++);
37 device_set_name(dev, name);
38
39 return 0;
40 }
41
42 /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
enetc_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)43 static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
44 {
45 struct enetc_mdio_priv priv;
46
47 priv.regs_base = bus->priv;
48 return enetc_mdio_read_priv(&priv, addr, devad, reg);
49 }
50
enetc_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)51 static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
52 u16 val)
53 {
54 struct enetc_mdio_priv priv;
55
56 priv.regs_base = bus->priv;
57 return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
58 }
59
60 /* only interfaces that can pin out through serdes have internal MDIO */
enetc_has_imdio(struct udevice * dev)61 static bool enetc_has_imdio(struct udevice *dev)
62 {
63 struct enetc_priv *priv = dev_get_priv(dev);
64
65 return !!(priv->imdio.priv);
66 }
67
68 /* set up serdes for SGMII */
enetc_init_sgmii(struct udevice * dev)69 static int enetc_init_sgmii(struct udevice *dev)
70 {
71 struct enetc_priv *priv = dev_get_priv(dev);
72 bool is2500 = false;
73 u16 reg;
74
75 if (!enetc_has_imdio(dev))
76 return 0;
77
78 if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
79 is2500 = true;
80
81 /*
82 * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
83 * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
84 * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
85 * but intentional.
86 */
87 reg = ENETC_PCS_IF_MODE_SGMII;
88 reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
89 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
90 ENETC_PCS_IF_MODE, reg);
91
92 /* Dev ability - SGMII */
93 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
94 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
95
96 /* Adjust link timer for SGMII */
97 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
98 ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
99 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
100 ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
101
102 reg = ENETC_PCS_CR_DEF_VAL;
103 reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
104 /* restart PCS AN */
105 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
106 ENETC_PCS_CR, reg);
107
108 return 0;
109 }
110
111 /* set up MAC for RGMII */
enetc_init_rgmii(struct udevice * dev)112 static int enetc_init_rgmii(struct udevice *dev)
113 {
114 struct enetc_priv *priv = dev_get_priv(dev);
115 u32 if_mode;
116
117 /* enable RGMII AN */
118 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
119 if_mode |= ENETC_PM_IF_MODE_AN_ENA;
120 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
121
122 return 0;
123 }
124
125 /* set up MAC and serdes for SXGMII */
enetc_init_sxgmii(struct udevice * dev)126 static int enetc_init_sxgmii(struct udevice *dev)
127 {
128 struct enetc_priv *priv = dev_get_priv(dev);
129 u32 if_mode;
130
131 /* set ifmode to (US)XGMII */
132 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
133 if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
134 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
135
136 if (!enetc_has_imdio(dev))
137 return 0;
138
139 /* Dev ability - SXGMII */
140 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
141 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
142
143 /* Restart PCS AN */
144 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
145 ENETC_PCS_CR,
146 ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
147
148 return 0;
149 }
150
151 /* Apply protocol specific configuration to MAC, serdes as needed */
enetc_start_pcs(struct udevice * dev)152 static void enetc_start_pcs(struct udevice *dev)
153 {
154 struct enetc_priv *priv = dev_get_priv(dev);
155 const char *if_str;
156
157 priv->if_type = PHY_INTERFACE_MODE_NONE;
158
159 /* register internal MDIO for debug purposes */
160 if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
161 priv->imdio.read = enetc_mdio_read;
162 priv->imdio.write = enetc_mdio_write;
163 priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
164 strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
165 if (!miiphy_get_dev_by_name(priv->imdio.name))
166 mdio_register(&priv->imdio);
167 }
168
169 if (!ofnode_valid(dev->node)) {
170 enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
171 return;
172 }
173
174 if_str = ofnode_read_string(dev->node, "phy-mode");
175 if (if_str)
176 priv->if_type = phy_get_interface_by_name(if_str);
177 else
178 enetc_dbg(dev,
179 "phy-mode property not found, defaulting to SGMII\n");
180 if (priv->if_type < 0)
181 priv->if_type = PHY_INTERFACE_MODE_NONE;
182
183 switch (priv->if_type) {
184 case PHY_INTERFACE_MODE_SGMII:
185 case PHY_INTERFACE_MODE_SGMII_2500:
186 enetc_init_sgmii(dev);
187 break;
188 case PHY_INTERFACE_MODE_XGMII:
189 case PHY_INTERFACE_MODE_USXGMII:
190 case PHY_INTERFACE_MODE_XFI:
191 enetc_init_sxgmii(dev);
192 break;
193 };
194 }
195
196 /* Configure the actual/external ethernet PHY, if one is found */
enetc_config_phy(struct udevice * dev)197 static void enetc_config_phy(struct udevice *dev)
198 {
199 struct enetc_priv *priv = dev_get_priv(dev);
200 int supported;
201
202 priv->phy = dm_eth_phy_connect(dev);
203
204 if (!priv->phy)
205 return;
206
207 supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
208 priv->phy->supported &= supported;
209 priv->phy->advertising &= supported;
210
211 phy_config(priv->phy);
212 }
213
214 /*
215 * Probe ENETC driver:
216 * - initialize port and station interface BARs
217 */
enetc_probe(struct udevice * dev)218 static int enetc_probe(struct udevice *dev)
219 {
220 struct enetc_priv *priv = dev_get_priv(dev);
221
222 if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
223 enetc_dbg(dev, "interface disabled\n");
224 return -ENODEV;
225 }
226
227 priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
228 sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
229 priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
230 sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
231
232 if (!priv->enetc_txbd || !priv->enetc_rxbd) {
233 /* free should be able to handle NULL, just free all pointers */
234 free(priv->enetc_txbd);
235 free(priv->enetc_rxbd);
236
237 return -ENOMEM;
238 }
239
240 /* initialize register */
241 priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
242 if (!priv->regs_base) {
243 enetc_dbg(dev, "failed to map BAR0\n");
244 return -EINVAL;
245 }
246 priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
247
248 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
249
250 enetc_start_pcs(dev);
251 enetc_config_phy(dev);
252
253 return 0;
254 }
255
256 /*
257 * Remove the driver from an interface:
258 * - free up allocated memory
259 */
enetc_remove(struct udevice * dev)260 static int enetc_remove(struct udevice *dev)
261 {
262 struct enetc_priv *priv = dev_get_priv(dev);
263
264 free(priv->enetc_txbd);
265 free(priv->enetc_rxbd);
266
267 return 0;
268 }
269
270 /* ENETC Port MAC address registers, accepts big-endian format */
enetc_set_primary_mac_addr(struct enetc_priv * priv,const u8 * addr)271 static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
272 {
273 u16 lower = *(const u16 *)(addr + 4);
274 u32 upper = *(const u32 *)addr;
275
276 enetc_write_port(priv, ENETC_PSIPMAR0, upper);
277 enetc_write_port(priv, ENETC_PSIPMAR1, lower);
278 }
279
280 /* Configure port parameters (# of rings, frame size, enable port) */
enetc_enable_si_port(struct enetc_priv * priv)281 static void enetc_enable_si_port(struct enetc_priv *priv)
282 {
283 u32 val;
284
285 /* set Rx/Tx BDR count */
286 val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
287 val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
288 enetc_write_port(priv, ENETC_PSICFGR(0), val);
289 /* set Rx max frame size */
290 enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
291 /* enable MAC port */
292 enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
293 /* enable port */
294 enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
295 /* set SI cache policy */
296 enetc_write(priv, ENETC_SICAR0,
297 ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
298 /* enable SI */
299 enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
300 }
301
302 /* returns DMA address for a given buffer index */
enetc_rxb_address(struct udevice * dev,int i)303 static inline u64 enetc_rxb_address(struct udevice *dev, int i)
304 {
305 return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
306 }
307
308 /*
309 * Setup a single Tx BD Ring (ID = 0):
310 * - set Tx buffer descriptor address
311 * - set the BD count
312 * - initialize the producer and consumer index
313 */
enetc_setup_tx_bdr(struct udevice * dev)314 static void enetc_setup_tx_bdr(struct udevice *dev)
315 {
316 struct enetc_priv *priv = dev_get_priv(dev);
317 struct bd_ring *tx_bdr = &priv->tx_bdr;
318 u64 tx_bd_add = (u64)priv->enetc_txbd;
319
320 /* used later to advance to the next Tx BD */
321 tx_bdr->bd_count = ENETC_BD_CNT;
322 tx_bdr->next_prod_idx = 0;
323 tx_bdr->next_cons_idx = 0;
324 tx_bdr->cons_idx = priv->regs_base +
325 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
326 tx_bdr->prod_idx = priv->regs_base +
327 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
328
329 /* set Tx BD address */
330 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
331 lower_32_bits(tx_bd_add));
332 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
333 upper_32_bits(tx_bd_add));
334 /* set Tx 8 BD count */
335 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
336 tx_bdr->bd_count);
337
338 /* reset both producer/consumer indexes */
339 enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
340 enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
341
342 /* enable TX ring */
343 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
344 }
345
346 /*
347 * Setup a single Rx BD Ring (ID = 0):
348 * - set Rx buffer descriptors address (one descriptor per buffer)
349 * - set buffer size as max frame size
350 * - enable Rx ring
351 * - reset consumer and producer indexes
352 * - set buffer for each descriptor
353 */
enetc_setup_rx_bdr(struct udevice * dev)354 static void enetc_setup_rx_bdr(struct udevice *dev)
355 {
356 struct enetc_priv *priv = dev_get_priv(dev);
357 struct bd_ring *rx_bdr = &priv->rx_bdr;
358 u64 rx_bd_add = (u64)priv->enetc_rxbd;
359 int i;
360
361 /* used later to advance to the next BD produced by ENETC HW */
362 rx_bdr->bd_count = ENETC_BD_CNT;
363 rx_bdr->next_prod_idx = 0;
364 rx_bdr->next_cons_idx = 0;
365 rx_bdr->cons_idx = priv->regs_base +
366 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
367 rx_bdr->prod_idx = priv->regs_base +
368 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
369
370 /* set Rx BD address */
371 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
372 lower_32_bits(rx_bd_add));
373 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
374 upper_32_bits(rx_bd_add));
375 /* set Rx BD count (multiple of 8) */
376 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
377 rx_bdr->bd_count);
378 /* set Rx buffer size */
379 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
380
381 /* fill Rx BD */
382 memset(priv->enetc_rxbd, 0,
383 rx_bdr->bd_count * sizeof(union enetc_rx_bd));
384 for (i = 0; i < rx_bdr->bd_count; i++) {
385 priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
386 /* each RX buffer must be aligned to 64B */
387 WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
388 }
389
390 /* reset producer (ENETC owned) and consumer (SW owned) index */
391 enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
392 enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
393
394 /* enable Rx ring */
395 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
396 }
397
398 /*
399 * Start ENETC interface:
400 * - perform FLR
401 * - enable access to port and SI registers
402 * - set mac address
403 * - setup TX/RX buffer descriptors
404 * - enable Tx/Rx rings
405 */
enetc_start(struct udevice * dev)406 static int enetc_start(struct udevice *dev)
407 {
408 struct eth_pdata *plat = dev_get_platdata(dev);
409 struct enetc_priv *priv = dev_get_priv(dev);
410
411 /* reset and enable the PCI device */
412 dm_pci_flr(dev);
413 dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
414 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
415
416 if (!is_valid_ethaddr(plat->enetaddr)) {
417 enetc_dbg(dev, "invalid MAC address, generate random ...\n");
418 net_random_ethaddr(plat->enetaddr);
419 }
420 enetc_set_primary_mac_addr(priv, plat->enetaddr);
421
422 enetc_enable_si_port(priv);
423
424 /* setup Tx/Rx buffer descriptors */
425 enetc_setup_tx_bdr(dev);
426 enetc_setup_rx_bdr(dev);
427
428 if (priv->if_type == PHY_INTERFACE_MODE_RGMII ||
429 priv->if_type == PHY_INTERFACE_MODE_RGMII_ID ||
430 priv->if_type == PHY_INTERFACE_MODE_RGMII_RXID ||
431 priv->if_type == PHY_INTERFACE_MODE_RGMII_TXID)
432 enetc_init_rgmii(dev);
433
434 if (priv->phy)
435 phy_startup(priv->phy);
436
437 return 0;
438 }
439
440 /*
441 * Stop the network interface:
442 * - just quiesce it, we can wipe all configuration as _start starts from
443 * scratch each time
444 */
enetc_stop(struct udevice * dev)445 static void enetc_stop(struct udevice *dev)
446 {
447 /* FLR is sufficient to quiesce the device */
448 dm_pci_flr(dev);
449 /* leave the BARs accessible after we stop, this is needed to use
450 * internal MDIO in command line.
451 */
452 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
453 }
454
455 /*
456 * ENETC transmit packet:
457 * - check if Tx BD ring is full
458 * - set buffer/packet address (dma address)
459 * - set final fragment flag
460 * - try while producer index equals consumer index or timeout
461 */
enetc_send(struct udevice * dev,void * packet,int length)462 static int enetc_send(struct udevice *dev, void *packet, int length)
463 {
464 struct enetc_priv *priv = dev_get_priv(dev);
465 struct bd_ring *txr = &priv->tx_bdr;
466 void *nv_packet = (void *)packet;
467 int tries = ENETC_POLL_TRIES;
468 u32 pi, ci;
469
470 pi = txr->next_prod_idx;
471 ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
472 /* Tx ring is full when */
473 if (((pi + 1) % txr->bd_count) == ci) {
474 enetc_dbg(dev, "Tx BDR full\n");
475 return -ETIMEDOUT;
476 }
477 enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
478 upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
479
480 /* prepare Tx BD */
481 memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
482 priv->enetc_txbd[pi].addr =
483 cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
484 priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
485 priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
486 priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
487 dmb();
488 /* send frame: increment producer index */
489 pi = (pi + 1) % txr->bd_count;
490 txr->next_prod_idx = pi;
491 enetc_write_reg(txr->prod_idx, pi);
492 while ((--tries >= 0) &&
493 (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
494 udelay(10);
495
496 return tries > 0 ? 0 : -ETIMEDOUT;
497 }
498
499 /*
500 * Receive frame:
501 * - wait for the next BD to get ready bit set
502 * - clean up the descriptor
503 * - move on and indicate to HW that the cleaned BD is available for Rx
504 */
enetc_recv(struct udevice * dev,int flags,uchar ** packetp)505 static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
506 {
507 struct enetc_priv *priv = dev_get_priv(dev);
508 struct bd_ring *rxr = &priv->rx_bdr;
509 int tries = ENETC_POLL_TRIES;
510 int pi = rxr->next_prod_idx;
511 int ci = rxr->next_cons_idx;
512 u32 status;
513 int len;
514 u8 rdy;
515
516 do {
517 dmb();
518 status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
519 /* check if current BD is ready to be consumed */
520 rdy = ENETC_RXBD_STATUS_R(status);
521 } while (--tries >= 0 && !rdy);
522
523 if (!rdy)
524 return -EAGAIN;
525
526 dmb();
527 len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
528 *packetp = (uchar *)enetc_rxb_address(dev, pi);
529 enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
530 ENETC_RXBD_STATUS_ERRORS(status),
531 upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
532
533 /* BD clean up and advance to next in ring */
534 memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
535 priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
536 rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
537 ci = (ci + 1) % rxr->bd_count;
538 rxr->next_cons_idx = ci;
539 dmb();
540 /* free up the slot in the ring for HW */
541 enetc_write_reg(rxr->cons_idx, ci);
542
543 return len;
544 }
545
546 static const struct eth_ops enetc_ops = {
547 .start = enetc_start,
548 .send = enetc_send,
549 .recv = enetc_recv,
550 .stop = enetc_stop,
551 };
552
553 U_BOOT_DRIVER(eth_enetc) = {
554 .name = "enetc_eth",
555 .id = UCLASS_ETH,
556 .bind = enetc_bind,
557 .probe = enetc_probe,
558 .remove = enetc_remove,
559 .ops = &enetc_ops,
560 .priv_auto_alloc_size = sizeof(struct enetc_priv),
561 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
562 };
563
564 static struct pci_device_id enetc_ids[] = {
565 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
566 {}
567 };
568
569 U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);
570