1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Aquantia PHY drivers
4 *
5 * Copyright 2014 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 */
8 #include <config.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <phy.h>
12 #include <u-boot/crc.h>
13 #include <malloc.h>
14 #include <asm/byteorder.h>
15 #include <fs.h>
16
17 #define AQUNTIA_10G_CTL 0x20
18 #define AQUNTIA_VENDOR_P1 0xc400
19
20 #define AQUNTIA_SPEED_LSB_MASK 0x2000
21 #define AQUNTIA_SPEED_MSB_MASK 0x40
22
23 #define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
24 #define AQUANTIA_SYSTEM_INTERFACE_SR_READY BIT(0)
25 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
26 #define AQUANTIA_FIRMWARE_ID 0x20
27 #define AQUANTIA_RESERVED_STATUS 0xc885
28 #define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
29 #define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
30 #define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
31
32 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
33 #define AQUANTIA_SI_IN_USE_MASK 0x0078
34 #define AQUANTIA_SI_USXGMII 0x0018
35
36 /* registers in MDIO_MMD_VEND1 region */
37 #define AQUANTIA_VND1_GLOBAL_SC 0x000
38 #define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb)
39
40 #define GLOBAL_FIRMWARE_ID 0x20
41 #define GLOBAL_FAULT 0xc850
42 #define GLOBAL_RSTATUS_1 0xc885
43
44 #define GLOBAL_ALARM_1 0xcc00
45 #define SYSTEM_READY_BIT 0x40
46
47 #define GLOBAL_STANDARD_CONTROL 0x0
48 #define SOFT_RESET BIT(15)
49 #define LOW_POWER BIT(11)
50
51 #define MAILBOX_CONTROL 0x0200
52 #define MAILBOX_EXECUTE BIT(15)
53 #define MAILBOX_WRITE BIT(14)
54 #define MAILBOX_RESET_CRC BIT(12)
55 #define MAILBOX_BUSY BIT(8)
56
57 #define MAILBOX_CRC 0x0201
58
59 #define MAILBOX_ADDR_MSW 0x0202
60 #define MAILBOX_ADDR_LSW 0x0203
61
62 #define MAILBOX_DATA_MSW 0x0204
63 #define MAILBOX_DATA_LSW 0x0205
64
65 #define UP_CONTROL 0xc001
66 #define UP_RESET BIT(15)
67 #define UP_RUN_STALL_OVERRIDE BIT(6)
68 #define UP_RUN_STALL BIT(0)
69
70 #define AQUANTIA_PMA_RX_VENDOR_P1 0xe400
71 #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0)
72 /* MDI reversal configured through registers */
73 #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1)
74 /* MDI reversal enabled */
75 #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0)
76
77 /*
78 * global start rate, the protocol associated with this speed is used by default
79 * on SI.
80 */
81 #define AQUANTIA_VND1_GSTART_RATE 0x31a
82 #define AQUANTIA_VND1_GSTART_RATE_OFF 0
83 #define AQUANTIA_VND1_GSTART_RATE_100M 1
84 #define AQUANTIA_VND1_GSTART_RATE_1G 2
85 #define AQUANTIA_VND1_GSTART_RATE_10G 3
86 #define AQUANTIA_VND1_GSTART_RATE_2_5G 4
87 #define AQUANTIA_VND1_GSTART_RATE_5G 5
88
89 /* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
90 #define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
91 #define AQUANTIA_VND1_GSYSCFG_100M 0
92 #define AQUANTIA_VND1_GSYSCFG_1G 1
93 #define AQUANTIA_VND1_GSYSCFG_2_5G 2
94 #define AQUANTIA_VND1_GSYSCFG_5G 3
95 #define AQUANTIA_VND1_GSYSCFG_10G 4
96
97 #define AQUANTIA_VND1_SMBUS0 0xc485
98 #define AQUANTIA_VND1_SMBUS1 0xc495
99
100 /* addresses of memory segments in the phy */
101 #define DRAM_BASE_ADDR 0x3FFE0000
102 #define IRAM_BASE_ADDR 0x40000000
103
104 /* firmware image format constants */
105 #define VERSION_STRING_SIZE 0x40
106 #define VERSION_STRING_OFFSET 0x0200
107 #define HEADER_OFFSET 0x300
108
109 /* driver private data */
110 #define AQUANTIA_NA 0
111 #define AQUANTIA_GEN1 1
112 #define AQUANTIA_GEN2 2
113 #define AQUANTIA_GEN3 3
114
115 #pragma pack(1)
116 struct fw_header {
117 u8 padding[4];
118 u8 iram_offset[3];
119 u8 iram_size[3];
120 u8 dram_offset[3];
121 u8 dram_size[3];
122 };
123
124 #pragma pack()
125
126 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
aquantia_read_fw(u8 ** fw_addr,size_t * fw_length)127 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
128 {
129 loff_t length, read;
130 int ret;
131 void *addr = NULL;
132
133 *fw_addr = NULL;
134 *fw_length = 0;
135 debug("Loading Acquantia microcode from %s %s\n",
136 CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
137 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
138 if (ret < 0)
139 goto cleanup;
140
141 ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
142 if (ret < 0)
143 goto cleanup;
144
145 addr = malloc(length);
146 if (!addr) {
147 ret = -ENOMEM;
148 goto cleanup;
149 }
150
151 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
152 if (ret < 0)
153 goto cleanup;
154
155 ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
156 &read);
157 if (ret < 0)
158 goto cleanup;
159
160 *fw_addr = addr;
161 *fw_length = length;
162 debug("Found Acquantia microcode.\n");
163
164 cleanup:
165 if (ret < 0) {
166 printf("loading firmware file %s %s failed with error %d\n",
167 CONFIG_PHY_AQUANTIA_FW_PART,
168 CONFIG_PHY_AQUANTIA_FW_NAME, ret);
169 free(addr);
170 }
171 return ret;
172 }
173
174 /* load data into the phy's memory */
aquantia_load_memory(struct phy_device * phydev,u32 addr,const u8 * data,size_t len)175 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
176 const u8 *data, size_t len)
177 {
178 size_t pos;
179 u16 crc = 0, up_crc;
180
181 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
182 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
183 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
184
185 for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
186 u32 word = 0;
187
188 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
189
190 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
191 (word >> 16));
192 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
193 word & 0xffff);
194
195 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
196 MAILBOX_EXECUTE | MAILBOX_WRITE);
197
198 /* keep a big endian CRC to match the phy processor */
199 word = cpu_to_be32(word);
200 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
201 }
202
203 up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
204 if (crc != up_crc) {
205 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
206 phydev->dev->name, crc, up_crc);
207 return -EINVAL;
208 }
209 return 0;
210 }
211
unpack_u24(const u8 * data)212 static u32 unpack_u24(const u8 *data)
213 {
214 return (data[2] << 16) + (data[1] << 8) + data[0];
215 }
216
aquantia_upload_firmware(struct phy_device * phydev)217 static int aquantia_upload_firmware(struct phy_device *phydev)
218 {
219 int ret;
220 u8 *addr = NULL;
221 size_t fw_length = 0;
222 u16 calculated_crc, read_crc;
223 char version[VERSION_STRING_SIZE];
224 u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
225 const struct fw_header *header;
226
227 ret = aquantia_read_fw(&addr, &fw_length);
228 if (ret != 0)
229 return ret;
230
231 read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1];
232 calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
233 if (read_crc != calculated_crc) {
234 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
235 phydev->dev->name, read_crc, calculated_crc);
236 ret = -EINVAL;
237 goto done;
238 }
239
240 /* Find the DRAM and IRAM sections within the firmware file. */
241 primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
242
243 header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
244
245 iram_offset = primary_offset + unpack_u24(header->iram_offset);
246 iram_size = unpack_u24(header->iram_size);
247
248 dram_offset = primary_offset + unpack_u24(header->dram_offset);
249 dram_size = unpack_u24(header->dram_size);
250
251 debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
252 primary_offset, iram_offset, iram_size, dram_offset, dram_size);
253
254 strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
255 VERSION_STRING_SIZE);
256 printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
257
258 /* stall the microcprocessor */
259 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
260 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
261
262 debug("loading dram 0x%08x from offset=%d size=%d\n",
263 DRAM_BASE_ADDR, dram_offset, dram_size);
264 ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
265 dram_size);
266 if (ret != 0)
267 goto done;
268
269 debug("loading iram 0x%08x from offset=%d size=%d\n",
270 IRAM_BASE_ADDR, iram_offset, iram_size);
271 ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
272 iram_size);
273 if (ret != 0)
274 goto done;
275
276 /* make sure soft reset and low power mode are clear */
277 phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
278
279 /* Release the microprocessor. UP_RESET must be held for 100 usec. */
280 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
281 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
282
283 udelay(100);
284
285 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
286
287 printf("%s firmare loading done.\n", phydev->dev->name);
288 done:
289 free(addr);
290 return ret;
291 }
292 #else
aquantia_upload_firmware(struct phy_device * phydev)293 static int aquantia_upload_firmware(struct phy_device *phydev)
294 {
295 printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
296 return -1;
297 }
298 #endif
299
300 struct {
301 u16 syscfg;
302 int cnt;
303 u16 start_rate;
304 } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
305 [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
306 AQUANTIA_VND1_GSTART_RATE_1G},
307 [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
308 AQUANTIA_VND1_GSTART_RATE_2_5G},
309 [PHY_INTERFACE_MODE_XGMII] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
310 AQUANTIA_VND1_GSTART_RATE_10G},
311 [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
312 AQUANTIA_VND1_GSTART_RATE_10G},
313 [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
314 AQUANTIA_VND1_GSTART_RATE_10G},
315 };
316
aquantia_set_proto(struct phy_device * phydev)317 static int aquantia_set_proto(struct phy_device *phydev)
318 {
319 int i;
320
321 if (!aquantia_syscfg[phydev->interface].cnt)
322 return 0;
323
324 /* set the default rate to enable the SI link */
325 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
326 aquantia_syscfg[phydev->interface].start_rate);
327
328 /* set selected protocol for all relevant line side link speeds */
329 for (i = 0; i <= aquantia_syscfg[phydev->interface].cnt; i++)
330 phy_write(phydev, MDIO_MMD_VEND1,
331 AQUANTIA_VND1_GSYSCFG_BASE + i,
332 aquantia_syscfg[phydev->interface].syscfg);
333 return 0;
334 }
335
aquantia_dts_config(struct phy_device * phydev)336 static int aquantia_dts_config(struct phy_device *phydev)
337 {
338 #ifdef CONFIG_DM_ETH
339 ofnode node = phydev->node;
340 u32 prop;
341 u16 reg;
342
343 /* this code only works on gen2 and gen3 PHYs */
344 if (phydev->drv->data != AQUANTIA_GEN2 &&
345 phydev->drv->data != AQUANTIA_GEN3)
346 return -ENOTSUPP;
347
348 if (!ofnode_valid(node))
349 return 0;
350
351 if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
352 debug("mdi-reversal = %d\n", (int)prop);
353 reg = phy_read(phydev, MDIO_MMD_PMAPMD,
354 AQUANTIA_PMA_RX_VENDOR_P1);
355 reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
356 reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
357 reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
358 phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
359 reg);
360 }
361 if (!ofnode_read_u32(node, "smb-addr", &prop)) {
362 debug("smb-addr = %x\n", (int)prop);
363 /*
364 * there are two addresses here, normally just one bus would
365 * be in use so we're setting both regs using the same DT
366 * property.
367 */
368 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
369 (u16)(prop << 1));
370 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
371 (u16)(prop << 1));
372 }
373
374 #endif
375 return 0;
376 }
377
aquantia_link_is_up(struct phy_device * phydev)378 static bool aquantia_link_is_up(struct phy_device *phydev)
379 {
380 u16 reg, regmask;
381 int devad, regnum;
382
383 /*
384 * On Gen 2 and 3 we have a bit that indicates that both system and
385 * line side are ready for data, use that if possible.
386 */
387 if (phydev->drv->data == AQUANTIA_GEN2 ||
388 phydev->drv->data == AQUANTIA_GEN3) {
389 devad = MDIO_MMD_PHYXS;
390 regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
391 regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
392 } else {
393 devad = MDIO_MMD_AN;
394 regnum = MDIO_STAT1;
395 regmask = MDIO_AN_STAT1_COMPLETE;
396 }
397 /* the register should be latched, do a double read */
398 phy_read(phydev, devad, regnum);
399 reg = phy_read(phydev, devad, regnum);
400
401 return !!(reg & regmask);
402 }
403
aquantia_config(struct phy_device * phydev)404 int aquantia_config(struct phy_device *phydev)
405 {
406 int interface = phydev->interface;
407 u32 val, id, rstatus, fault;
408 u32 reg_val1 = 0;
409 int num_retries = 5;
410 int usx_an = 0;
411
412 /*
413 * check if the system is out of reset and init sequence completed.
414 * chip-wide reset for gen1 quad phys takes longer
415 */
416 while (--num_retries) {
417 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
418 if (rstatus & SYSTEM_READY_BIT)
419 break;
420 mdelay(10);
421 }
422
423 id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
424 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
425 fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
426
427 if (id != 0)
428 printf("%s running firmware version %X.%X.%X\n",
429 phydev->dev->name, (id >> 8), id & 0xff,
430 (rstatus >> 4) & 0xf);
431
432 if (fault != 0)
433 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
434
435 if (id == 0 || fault != 0) {
436 int ret;
437
438 ret = aquantia_upload_firmware(phydev);
439 if (ret != 0)
440 return ret;
441 }
442 /*
443 * for backward compatibility convert XGMII into either XFI or USX based
444 * on FW config
445 */
446 if (interface == PHY_INTERFACE_MODE_XGMII) {
447 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
448 AQUANTIA_SYSTEM_INTERFACE_SR);
449 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
450 interface = PHY_INTERFACE_MODE_USXGMII;
451 else
452 interface = PHY_INTERFACE_MODE_XFI;
453 }
454
455 /*
456 * if link is up already we can just use it, otherwise configure
457 * the protocols in the PHY. If link is down set the system
458 * interface protocol to use based on phydev->interface
459 */
460 if (!aquantia_link_is_up(phydev) &&
461 (phydev->drv->data == AQUANTIA_GEN2 ||
462 phydev->drv->data == AQUANTIA_GEN3)) {
463 /* set PHY in low power mode so we can configure protocols */
464 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
465 AQUANTIA_VND1_GLOBAL_SC_LP);
466 mdelay(10);
467
468 /* configure protocol based on phydev->interface */
469 aquantia_set_proto(phydev);
470 /* apply custom configuration based on DT */
471 aquantia_dts_config(phydev);
472
473 /* wake PHY back up */
474 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
475 mdelay(10);
476 }
477
478 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
479
480 switch (interface) {
481 case PHY_INTERFACE_MODE_SGMII:
482 /* 1000BASE-T mode */
483 phydev->advertising = SUPPORTED_1000baseT_Full;
484 phydev->supported = phydev->advertising;
485
486 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
487 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
488 break;
489 case PHY_INTERFACE_MODE_USXGMII:
490 usx_an = 1;
491 /* FALLTHROUGH */
492 case PHY_INTERFACE_MODE_XFI:
493 /* 10GBASE-T mode */
494 phydev->advertising = SUPPORTED_10000baseT_Full;
495 phydev->supported = phydev->advertising;
496
497 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
498 !(val & AQUNTIA_SPEED_MSB_MASK))
499 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
500 AQUNTIA_SPEED_LSB_MASK |
501 AQUNTIA_SPEED_MSB_MASK);
502
503 /* If SI is USXGMII then start USXGMII autoneg */
504 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
505 AQUANTIA_VENDOR_PROVISIONING_REG);
506
507 if (usx_an) {
508 reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
509 printf("%s: system interface USXGMII\n",
510 phydev->dev->name);
511 } else {
512 reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
513 printf("%s: system interface XFI\n",
514 phydev->dev->name);
515 }
516
517 phy_write(phydev, MDIO_MMD_PHYXS,
518 AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
519 break;
520 case PHY_INTERFACE_MODE_SGMII_2500:
521 /* 2.5GBASE-T mode */
522 phydev->advertising = SUPPORTED_1000baseT_Full;
523 phydev->supported = phydev->advertising;
524
525 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
526 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
527 break;
528 case PHY_INTERFACE_MODE_MII:
529 /* 100BASE-TX mode */
530 phydev->advertising = SUPPORTED_100baseT_Full;
531 phydev->supported = phydev->advertising;
532
533 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
534 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
535 break;
536 };
537
538 val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
539 reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
540
541 printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
542 phydev->drv->name,
543 (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
544 reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
545 (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
546
547 return 0;
548 }
549
aquantia_startup(struct phy_device * phydev)550 int aquantia_startup(struct phy_device *phydev)
551 {
552 u32 reg, speed;
553 int i = 0;
554
555 phydev->duplex = DUPLEX_FULL;
556
557 /* if the AN is still in progress, wait till timeout. */
558 if (!aquantia_link_is_up(phydev)) {
559 printf("%s Waiting for PHY auto negotiation to complete",
560 phydev->dev->name);
561 do {
562 udelay(1000);
563 if ((i++ % 500) == 0)
564 printf(".");
565 } while (!aquantia_link_is_up(phydev) &&
566 i < (4 * PHY_ANEG_TIMEOUT));
567
568 if (i > PHY_ANEG_TIMEOUT)
569 printf(" TIMEOUT !\n");
570 }
571
572 /* Read twice because link state is latched and a
573 * read moves the current state into the register */
574 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
575 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
576 if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
577 phydev->link = 0;
578 else
579 phydev->link = 1;
580
581 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
582 if (speed & AQUNTIA_SPEED_MSB_MASK) {
583 if (speed & AQUNTIA_SPEED_LSB_MASK)
584 phydev->speed = SPEED_10000;
585 else
586 phydev->speed = SPEED_1000;
587 } else {
588 if (speed & AQUNTIA_SPEED_LSB_MASK)
589 phydev->speed = SPEED_100;
590 else
591 phydev->speed = SPEED_10;
592 }
593
594 return 0;
595 }
596
597 struct phy_driver aq1202_driver = {
598 .name = "Aquantia AQ1202",
599 .uid = 0x3a1b445,
600 .mask = 0xfffffff0,
601 .features = PHY_10G_FEATURES,
602 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
603 MDIO_MMD_PHYXS | MDIO_MMD_AN |
604 MDIO_MMD_VEND1),
605 .config = &aquantia_config,
606 .startup = &aquantia_startup,
607 .shutdown = &gen10g_shutdown,
608 };
609
610 struct phy_driver aq2104_driver = {
611 .name = "Aquantia AQ2104",
612 .uid = 0x3a1b460,
613 .mask = 0xfffffff0,
614 .features = PHY_10G_FEATURES,
615 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
616 MDIO_MMD_PHYXS | MDIO_MMD_AN |
617 MDIO_MMD_VEND1),
618 .config = &aquantia_config,
619 .startup = &aquantia_startup,
620 .shutdown = &gen10g_shutdown,
621 };
622
623 struct phy_driver aqr105_driver = {
624 .name = "Aquantia AQR105",
625 .uid = 0x3a1b4a2,
626 .mask = 0xfffffff0,
627 .features = PHY_10G_FEATURES,
628 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
629 MDIO_MMD_PHYXS | MDIO_MMD_AN |
630 MDIO_MMD_VEND1),
631 .config = &aquantia_config,
632 .startup = &aquantia_startup,
633 .shutdown = &gen10g_shutdown,
634 .data = AQUANTIA_GEN1,
635 };
636
637 struct phy_driver aqr106_driver = {
638 .name = "Aquantia AQR106",
639 .uid = 0x3a1b4d0,
640 .mask = 0xfffffff0,
641 .features = PHY_10G_FEATURES,
642 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
643 MDIO_MMD_PHYXS | MDIO_MMD_AN |
644 MDIO_MMD_VEND1),
645 .config = &aquantia_config,
646 .startup = &aquantia_startup,
647 .shutdown = &gen10g_shutdown,
648 };
649
650 struct phy_driver aqr107_driver = {
651 .name = "Aquantia AQR107",
652 .uid = 0x3a1b4e0,
653 .mask = 0xfffffff0,
654 .features = PHY_10G_FEATURES,
655 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
656 MDIO_MMD_PHYXS | MDIO_MMD_AN |
657 MDIO_MMD_VEND1),
658 .config = &aquantia_config,
659 .startup = &aquantia_startup,
660 .shutdown = &gen10g_shutdown,
661 .data = AQUANTIA_GEN2,
662 };
663
664 struct phy_driver aqr112_driver = {
665 .name = "Aquantia AQR112",
666 .uid = 0x3a1b660,
667 .mask = 0xfffffff0,
668 .features = PHY_10G_FEATURES,
669 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
670 MDIO_MMD_PHYXS | MDIO_MMD_AN |
671 MDIO_MMD_VEND1),
672 .config = &aquantia_config,
673 .startup = &aquantia_startup,
674 .shutdown = &gen10g_shutdown,
675 .data = AQUANTIA_GEN3,
676 };
677
678 struct phy_driver aqr405_driver = {
679 .name = "Aquantia AQR405",
680 .uid = 0x3a1b4b2,
681 .mask = 0xfffffff0,
682 .features = PHY_10G_FEATURES,
683 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
684 MDIO_MMD_PHYXS | MDIO_MMD_AN |
685 MDIO_MMD_VEND1),
686 .config = &aquantia_config,
687 .startup = &aquantia_startup,
688 .shutdown = &gen10g_shutdown,
689 .data = AQUANTIA_GEN1,
690 };
691
692 struct phy_driver aqr412_driver = {
693 .name = "Aquantia AQR412",
694 .uid = 0x3a1b710,
695 .mask = 0xfffffff0,
696 .features = PHY_10G_FEATURES,
697 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
698 MDIO_MMD_PHYXS | MDIO_MMD_AN |
699 MDIO_MMD_VEND1),
700 .config = &aquantia_config,
701 .startup = &aquantia_startup,
702 .shutdown = &gen10g_shutdown,
703 .data = AQUANTIA_GEN3,
704 };
705
phy_aquantia_init(void)706 int phy_aquantia_init(void)
707 {
708 phy_register(&aq1202_driver);
709 phy_register(&aq2104_driver);
710 phy_register(&aqr105_driver);
711 phy_register(&aqr106_driver);
712 phy_register(&aqr107_driver);
713 phy_register(&aqr112_driver);
714 phy_register(&aqr405_driver);
715 phy_register(&aqr412_driver);
716
717 return 0;
718 }
719