1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale Three Speed Ethernet Controller driver
4 *
5 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6 * (C) Copyright 2003, Motorola, Inc.
7 * author Andy Fleming
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <dm.h>
13 #include <malloc.h>
14 #include <net.h>
15 #include <command.h>
16 #include <tsec.h>
17 #include <fsl_mdio.h>
18 #include <linux/errno.h>
19 #include <asm/processor.h>
20 #include <asm/io.h>
21
22 #ifndef CONFIG_DM_ETH
23 /* Default initializations for TSEC controllers. */
24
25 static struct tsec_info_struct tsec_info[] = {
26 #ifdef CONFIG_TSEC1
27 STD_TSEC_INFO(1), /* TSEC1 */
28 #endif
29 #ifdef CONFIG_TSEC2
30 STD_TSEC_INFO(2), /* TSEC2 */
31 #endif
32 #ifdef CONFIG_MPC85XX_FEC
33 {
34 .regs = TSEC_GET_REGS(2, 0x2000),
35 .devname = CONFIG_MPC85XX_FEC_NAME,
36 .phyaddr = FEC_PHY_ADDR,
37 .flags = FEC_FLAGS,
38 .mii_devname = DEFAULT_MII_NAME
39 }, /* FEC */
40 #endif
41 #ifdef CONFIG_TSEC3
42 STD_TSEC_INFO(3), /* TSEC3 */
43 #endif
44 #ifdef CONFIG_TSEC4
45 STD_TSEC_INFO(4), /* TSEC4 */
46 #endif
47 };
48 #endif /* CONFIG_DM_ETH */
49
50 #define TBIANA_SETTINGS ( \
51 TBIANA_ASYMMETRIC_PAUSE \
52 | TBIANA_SYMMETRIC_PAUSE \
53 | TBIANA_FULL_DUPLEX \
54 )
55
56 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
57 #ifndef CONFIG_TSEC_TBICR_SETTINGS
58 #define CONFIG_TSEC_TBICR_SETTINGS ( \
59 TBICR_PHY_RESET \
60 | TBICR_ANEG_ENABLE \
61 | TBICR_FULL_DUPLEX \
62 | TBICR_SPEED1_SET \
63 )
64 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
65
66 /* Configure the TBI for SGMII operation */
tsec_configure_serdes(struct tsec_private * priv)67 static void tsec_configure_serdes(struct tsec_private *priv)
68 {
69 /*
70 * Access TBI PHY registers at given TSEC register offset as opposed
71 * to the register offset used for external PHY accesses
72 */
73 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
74 0, TBI_ANA, TBIANA_SETTINGS);
75 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
76 0, TBI_TBICON, TBICON_CLK_SELECT);
77 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
78 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
79 }
80
81 /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
82 * and this is the ethernet-crc method needed for TSEC -- and perhaps
83 * some other adapter -- hash tables
84 */
85 #define CRCPOLY_LE 0xedb88320
ether_crc(size_t len,unsigned char const * p)86 static u32 ether_crc(size_t len, unsigned char const *p)
87 {
88 int i;
89 u32 crc;
90
91 crc = ~0;
92 while (len--) {
93 crc ^= *p++;
94 for (i = 0; i < 8; i++)
95 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
96 }
97 /* an reverse the bits, cuz of way they arrive -- last-first */
98 crc = (crc >> 16) | (crc << 16);
99 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
100 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
101 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
102 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
103 return crc;
104 }
105
106 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
107
108 /* Set the appropriate hash bit for the given addr */
109
110 /*
111 * The algorithm works like so:
112 * 1) Take the Destination Address (ie the multicast address), and
113 * do a CRC on it (little endian), and reverse the bits of the
114 * result.
115 * 2) Use the 8 most significant bits as a hash into a 256-entry
116 * table. The table is controlled through 8 32-bit registers:
117 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
118 * 255. This means that the 3 most significant bits in the
119 * hash index which gaddr register to use, and the 5 other bits
120 * indicate which bit (assuming an IBM numbering scheme, which
121 * for PowerPC (tm) is usually the case) in the register holds
122 * the entry.
123 */
124 #ifndef CONFIG_DM_ETH
tsec_mcast_addr(struct eth_device * dev,const u8 * mcast_mac,int join)125 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
126 int join)
127 #else
128 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
129 #endif
130 {
131 struct tsec_private *priv = (struct tsec_private *)dev->priv;
132 struct tsec __iomem *regs = priv->regs;
133 u32 result, value;
134 u8 whichbit, whichreg;
135
136 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
137 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
138 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
139
140 value = BIT(31 - whichbit);
141
142 if (join)
143 setbits_be32(®s->hash.gaddr0 + whichreg, value);
144 else
145 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
146
147 return 0;
148 }
149
150 /*
151 * Initialized required registers to appropriate values, zeroing
152 * those we don't care about (unless zero is bad, in which case,
153 * choose a more appropriate value)
154 */
init_registers(struct tsec __iomem * regs)155 static void init_registers(struct tsec __iomem *regs)
156 {
157 /* Clear IEVENT */
158 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
159
160 out_be32(®s->imask, IMASK_INIT_CLEAR);
161
162 out_be32(®s->hash.iaddr0, 0);
163 out_be32(®s->hash.iaddr1, 0);
164 out_be32(®s->hash.iaddr2, 0);
165 out_be32(®s->hash.iaddr3, 0);
166 out_be32(®s->hash.iaddr4, 0);
167 out_be32(®s->hash.iaddr5, 0);
168 out_be32(®s->hash.iaddr6, 0);
169 out_be32(®s->hash.iaddr7, 0);
170
171 out_be32(®s->hash.gaddr0, 0);
172 out_be32(®s->hash.gaddr1, 0);
173 out_be32(®s->hash.gaddr2, 0);
174 out_be32(®s->hash.gaddr3, 0);
175 out_be32(®s->hash.gaddr4, 0);
176 out_be32(®s->hash.gaddr5, 0);
177 out_be32(®s->hash.gaddr6, 0);
178 out_be32(®s->hash.gaddr7, 0);
179
180 out_be32(®s->rctrl, 0x00000000);
181
182 /* Init RMON mib registers */
183 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
184
185 out_be32(®s->rmon.cam1, 0xffffffff);
186 out_be32(®s->rmon.cam2, 0xffffffff);
187
188 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
189
190 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
191
192 out_be32(®s->attr, ATTR_INIT_SETTINGS);
193 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
194 }
195
196 /*
197 * Configure maccfg2 based on negotiated speed and duplex
198 * reported by PHY handling code
199 */
adjust_link(struct tsec_private * priv,struct phy_device * phydev)200 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
201 {
202 struct tsec __iomem *regs = priv->regs;
203 u32 ecntrl, maccfg2;
204
205 if (!phydev->link) {
206 printf("%s: No link.\n", phydev->dev->name);
207 return;
208 }
209
210 /* clear all bits relative with interface mode */
211 ecntrl = in_be32(®s->ecntrl);
212 ecntrl &= ~ECNTRL_R100;
213
214 maccfg2 = in_be32(®s->maccfg2);
215 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
216
217 if (phydev->duplex)
218 maccfg2 |= MACCFG2_FULL_DUPLEX;
219
220 switch (phydev->speed) {
221 case 1000:
222 maccfg2 |= MACCFG2_GMII;
223 break;
224 case 100:
225 case 10:
226 maccfg2 |= MACCFG2_MII;
227
228 /*
229 * Set R100 bit in all modes although
230 * it is only used in RGMII mode
231 */
232 if (phydev->speed == 100)
233 ecntrl |= ECNTRL_R100;
234 break;
235 default:
236 printf("%s: Speed was bad\n", phydev->dev->name);
237 break;
238 }
239
240 out_be32(®s->ecntrl, ecntrl);
241 out_be32(®s->maccfg2, maccfg2);
242
243 printf("Speed: %d, %s duplex%s\n", phydev->speed,
244 (phydev->duplex) ? "full" : "half",
245 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
246 }
247
248 /*
249 * This returns the status bits of the device. The return value
250 * is never checked, and this is what the 8260 driver did, so we
251 * do the same. Presumably, this would be zero if there were no
252 * errors
253 */
254 #ifndef CONFIG_DM_ETH
tsec_send(struct eth_device * dev,void * packet,int length)255 static int tsec_send(struct eth_device *dev, void *packet, int length)
256 #else
257 static int tsec_send(struct udevice *dev, void *packet, int length)
258 #endif
259 {
260 struct tsec_private *priv = (struct tsec_private *)dev->priv;
261 struct tsec __iomem *regs = priv->regs;
262 int result = 0;
263 u16 status;
264 int i;
265
266 /* Find an empty buffer descriptor */
267 for (i = 0;
268 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
269 i++) {
270 if (i >= TOUT_LOOP) {
271 printf("%s: tsec: tx buffers full\n", dev->name);
272 return result;
273 }
274 }
275
276 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
277 out_be16(&priv->txbd[priv->tx_idx].length, length);
278 status = in_be16(&priv->txbd[priv->tx_idx].status);
279 out_be16(&priv->txbd[priv->tx_idx].status, status |
280 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
281
282 /* Tell the DMA to go */
283 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
284
285 /* Wait for buffer to be transmitted */
286 for (i = 0;
287 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
288 i++) {
289 if (i >= TOUT_LOOP) {
290 printf("%s: tsec: tx error\n", dev->name);
291 return result;
292 }
293 }
294
295 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
296 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
297
298 return result;
299 }
300
301 #ifndef CONFIG_DM_ETH
tsec_recv(struct eth_device * dev)302 static int tsec_recv(struct eth_device *dev)
303 {
304 struct tsec_private *priv = (struct tsec_private *)dev->priv;
305 struct tsec __iomem *regs = priv->regs;
306
307 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
308 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
309 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
310 uchar *packet = net_rx_packets[priv->rx_idx];
311
312 /* Send the packet up if there were no errors */
313 if (!(status & RXBD_STATS))
314 net_process_received_packet(packet, length - 4);
315 else
316 printf("Got error %x\n", (status & RXBD_STATS));
317
318 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
319
320 status = RXBD_EMPTY;
321 /* Set the wrap bit if this is the last element in the list */
322 if ((priv->rx_idx + 1) == PKTBUFSRX)
323 status |= RXBD_WRAP;
324 out_be16(&priv->rxbd[priv->rx_idx].status, status);
325
326 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
327 }
328
329 if (in_be32(®s->ievent) & IEVENT_BSY) {
330 out_be32(®s->ievent, IEVENT_BSY);
331 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
332 }
333
334 return -1;
335 }
336 #else
tsec_recv(struct udevice * dev,int flags,uchar ** packetp)337 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
338 {
339 struct tsec_private *priv = (struct tsec_private *)dev->priv;
340 struct tsec __iomem *regs = priv->regs;
341 int ret = -1;
342
343 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
344 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
345 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
346 u32 buf;
347
348 /* Send the packet up if there were no errors */
349 if (!(status & RXBD_STATS)) {
350 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
351 *packetp = (uchar *)buf;
352 ret = length - 4;
353 } else {
354 printf("Got error %x\n", (status & RXBD_STATS));
355 }
356 }
357
358 if (in_be32(®s->ievent) & IEVENT_BSY) {
359 out_be32(®s->ievent, IEVENT_BSY);
360 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
361 }
362
363 return ret;
364 }
365
tsec_free_pkt(struct udevice * dev,uchar * packet,int length)366 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
367 {
368 struct tsec_private *priv = (struct tsec_private *)dev->priv;
369 u16 status;
370
371 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
372
373 status = RXBD_EMPTY;
374 /* Set the wrap bit if this is the last element in the list */
375 if ((priv->rx_idx + 1) == PKTBUFSRX)
376 status |= RXBD_WRAP;
377 out_be16(&priv->rxbd[priv->rx_idx].status, status);
378
379 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
380
381 return 0;
382 }
383 #endif
384
385 /* Stop the interface */
386 #ifndef CONFIG_DM_ETH
tsec_halt(struct eth_device * dev)387 static void tsec_halt(struct eth_device *dev)
388 #else
389 static void tsec_halt(struct udevice *dev)
390 #endif
391 {
392 struct tsec_private *priv = (struct tsec_private *)dev->priv;
393 struct tsec __iomem *regs = priv->regs;
394
395 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
396 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
397
398 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
399 != (IEVENT_GRSC | IEVENT_GTSC))
400 ;
401
402 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
403
404 /* Shut down the PHY, as needed */
405 phy_shutdown(priv->phydev);
406 }
407
408 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
409 /*
410 * When MACCFG1[Rx_EN] is enabled during system boot as part
411 * of the eTSEC port initialization sequence,
412 * the eTSEC Rx logic may not be properly initialized.
413 */
redundant_init(struct tsec_private * priv)414 void redundant_init(struct tsec_private *priv)
415 {
416 struct tsec __iomem *regs = priv->regs;
417 uint t, count = 0;
418 int fail = 1;
419 static const u8 pkt[] = {
420 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
421 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
422 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
423 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
424 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
425 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
426 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
427 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
428 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
429 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
430 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
431 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
432 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
433 0x71, 0x72};
434
435 /* Enable promiscuous mode */
436 setbits_be32(®s->rctrl, 0x8);
437 /* Enable loopback mode */
438 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
439 /* Enable transmit and receive */
440 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
441
442 /* Tell the DMA it is clear to go */
443 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
444 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
445 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
446 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
447
448 do {
449 u16 status;
450
451 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
452
453 /* Wait for buffer to be received */
454 for (t = 0;
455 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
456 t++) {
457 if (t >= 10 * TOUT_LOOP) {
458 printf("%s: tsec: rx error\n", priv->dev->name);
459 break;
460 }
461 }
462
463 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
464 fail = 0;
465
466 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
467 status = RXBD_EMPTY;
468 if ((priv->rx_idx + 1) == PKTBUFSRX)
469 status |= RXBD_WRAP;
470 out_be16(&priv->rxbd[priv->rx_idx].status, status);
471 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
472
473 if (in_be32(®s->ievent) & IEVENT_BSY) {
474 out_be32(®s->ievent, IEVENT_BSY);
475 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
476 }
477 if (fail) {
478 printf("loopback recv packet error!\n");
479 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
480 udelay(1000);
481 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
482 }
483 } while ((count++ < 4) && (fail == 1));
484
485 if (fail)
486 panic("eTSEC init fail!\n");
487 /* Disable promiscuous mode */
488 clrbits_be32(®s->rctrl, 0x8);
489 /* Disable loopback mode */
490 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
491 }
492 #endif
493
494 /*
495 * Set up the buffers and their descriptors, and bring up the
496 * interface
497 */
startup_tsec(struct tsec_private * priv)498 static void startup_tsec(struct tsec_private *priv)
499 {
500 struct tsec __iomem *regs = priv->regs;
501 u16 status;
502 int i;
503
504 /* reset the indices to zero */
505 priv->rx_idx = 0;
506 priv->tx_idx = 0;
507 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
508 uint svr;
509 #endif
510
511 /* Point to the buffer descriptors */
512 out_be32(®s->tbase, (u32)&priv->txbd[0]);
513 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
514
515 /* Initialize the Rx Buffer descriptors */
516 for (i = 0; i < PKTBUFSRX; i++) {
517 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
518 out_be16(&priv->rxbd[i].length, 0);
519 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
520 }
521 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
522 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
523
524 /* Initialize the TX Buffer Descriptors */
525 for (i = 0; i < TX_BUF_CNT; i++) {
526 out_be16(&priv->txbd[i].status, 0);
527 out_be16(&priv->txbd[i].length, 0);
528 out_be32(&priv->txbd[i].bufptr, 0);
529 }
530 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
531 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
532
533 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
534 svr = get_svr();
535 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
536 redundant_init(priv);
537 #endif
538 /* Enable Transmit and Receive */
539 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
540
541 /* Tell the DMA it is clear to go */
542 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
543 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
544 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
545 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
546 }
547
548 /*
549 * Initializes data structures and registers for the controller,
550 * and brings the interface up. Returns the link status, meaning
551 * that it returns success if the link is up, failure otherwise.
552 * This allows U-Boot to find the first active controller.
553 */
554 #ifndef CONFIG_DM_ETH
tsec_init(struct eth_device * dev,bd_t * bd)555 static int tsec_init(struct eth_device *dev, bd_t *bd)
556 #else
557 static int tsec_init(struct udevice *dev)
558 #endif
559 {
560 struct tsec_private *priv = (struct tsec_private *)dev->priv;
561 #ifdef CONFIG_DM_ETH
562 struct eth_pdata *pdata = dev_get_platdata(dev);
563 #else
564 struct eth_device *pdata = dev;
565 #endif
566 struct tsec __iomem *regs = priv->regs;
567 u32 tempval;
568 int ret;
569
570 /* Make sure the controller is stopped */
571 tsec_halt(dev);
572
573 /* Init MACCFG2. Defaults to GMII */
574 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
575
576 /* Init ECNTRL */
577 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
578
579 /*
580 * Copy the station address into the address registers.
581 * For a station address of 0x12345678ABCD in transmission
582 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
583 * MACnADDR2 is set to 0x34120000.
584 */
585 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
586 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
587
588 out_be32(®s->macstnaddr1, tempval);
589
590 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
591
592 out_be32(®s->macstnaddr2, tempval);
593
594 /* Clear out (for the most part) the other registers */
595 init_registers(regs);
596
597 /* Ready the device for tx/rx */
598 startup_tsec(priv);
599
600 /* Start up the PHY */
601 ret = phy_startup(priv->phydev);
602 if (ret) {
603 printf("Could not initialize PHY %s\n",
604 priv->phydev->dev->name);
605 return ret;
606 }
607
608 adjust_link(priv, priv->phydev);
609
610 /* If there's no link, fail */
611 return priv->phydev->link ? 0 : -1;
612 }
613
tsec_get_interface(struct tsec_private * priv)614 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
615 {
616 struct tsec __iomem *regs = priv->regs;
617 u32 ecntrl;
618
619 ecntrl = in_be32(®s->ecntrl);
620
621 if (ecntrl & ECNTRL_SGMII_MODE)
622 return PHY_INTERFACE_MODE_SGMII;
623
624 if (ecntrl & ECNTRL_TBI_MODE) {
625 if (ecntrl & ECNTRL_REDUCED_MODE)
626 return PHY_INTERFACE_MODE_RTBI;
627 else
628 return PHY_INTERFACE_MODE_TBI;
629 }
630
631 if (ecntrl & ECNTRL_REDUCED_MODE) {
632 phy_interface_t interface;
633
634 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
635 return PHY_INTERFACE_MODE_RMII;
636
637 interface = priv->interface;
638
639 /*
640 * This isn't autodetected, so it must
641 * be set by the platform code.
642 */
643 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
644 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
645 interface == PHY_INTERFACE_MODE_RGMII_RXID)
646 return interface;
647
648 return PHY_INTERFACE_MODE_RGMII;
649 }
650
651 if (priv->flags & TSEC_GIGABIT)
652 return PHY_INTERFACE_MODE_GMII;
653
654 return PHY_INTERFACE_MODE_MII;
655 }
656
657 /*
658 * Discover which PHY is attached to the device, and configure it
659 * properly. If the PHY is not recognized, then return 0
660 * (failure). Otherwise, return 1
661 */
init_phy(struct tsec_private * priv)662 static int init_phy(struct tsec_private *priv)
663 {
664 struct phy_device *phydev;
665 struct tsec __iomem *regs = priv->regs;
666 u32 supported = (SUPPORTED_10baseT_Half |
667 SUPPORTED_10baseT_Full |
668 SUPPORTED_100baseT_Half |
669 SUPPORTED_100baseT_Full);
670
671 if (priv->flags & TSEC_GIGABIT)
672 supported |= SUPPORTED_1000baseT_Full;
673
674 /* Assign a Physical address to the TBI */
675 out_be32(®s->tbipa, priv->tbiaddr);
676
677 priv->interface = tsec_get_interface(priv);
678
679 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
680 tsec_configure_serdes(priv);
681
682 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
683 priv->interface);
684 if (!phydev)
685 return 0;
686
687 phydev->supported &= supported;
688 phydev->advertising = phydev->supported;
689
690 priv->phydev = phydev;
691
692 phy_config(phydev);
693
694 return 1;
695 }
696
697 #ifndef CONFIG_DM_ETH
698 /*
699 * Initialize device structure. Returns success if PHY
700 * initialization succeeded (i.e. if it recognizes the PHY)
701 */
tsec_initialize(bd_t * bis,struct tsec_info_struct * tsec_info)702 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
703 {
704 struct tsec_private *priv;
705 struct eth_device *dev;
706 int i;
707
708 dev = (struct eth_device *)malloc(sizeof(*dev));
709
710 if (!dev)
711 return 0;
712
713 memset(dev, 0, sizeof(*dev));
714
715 priv = (struct tsec_private *)malloc(sizeof(*priv));
716
717 if (!priv) {
718 free(dev);
719 return 0;
720 }
721
722 priv->regs = tsec_info->regs;
723 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
724
725 priv->phyaddr = tsec_info->phyaddr;
726 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
727 priv->flags = tsec_info->flags;
728
729 strcpy(dev->name, tsec_info->devname);
730 priv->interface = tsec_info->interface;
731 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
732 priv->dev = dev;
733 dev->iobase = 0;
734 dev->priv = priv;
735 dev->init = tsec_init;
736 dev->halt = tsec_halt;
737 dev->send = tsec_send;
738 dev->recv = tsec_recv;
739 dev->mcast = tsec_mcast_addr;
740
741 /* Tell U-Boot to get the addr from the env */
742 for (i = 0; i < 6; i++)
743 dev->enetaddr[i] = 0;
744
745 eth_register(dev);
746
747 /* Reset the MAC */
748 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
749 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
750 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
751
752 /* Try to initialize PHY here, and return */
753 return init_phy(priv);
754 }
755
756 /*
757 * Initialize all the TSEC devices
758 *
759 * Returns the number of TSEC devices that were initialized
760 */
tsec_eth_init(bd_t * bis,struct tsec_info_struct * tsecs,int num)761 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
762 {
763 int i;
764 int count = 0;
765
766 for (i = 0; i < num; i++) {
767 int ret = tsec_initialize(bis, &tsecs[i]);
768
769 if (ret > 0)
770 count += ret;
771 }
772
773 return count;
774 }
775
tsec_standard_init(bd_t * bis)776 int tsec_standard_init(bd_t *bis)
777 {
778 struct fsl_pq_mdio_info info;
779
780 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
781 info.name = DEFAULT_MII_NAME;
782
783 fsl_pq_mdio_init(bis, &info);
784
785 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
786 }
787 #else /* CONFIG_DM_ETH */
tsec_probe(struct udevice * dev)788 int tsec_probe(struct udevice *dev)
789 {
790 struct eth_pdata *pdata = dev_get_platdata(dev);
791 struct tsec_private *priv = dev_get_priv(dev);
792 struct ofnode_phandle_args phandle_args;
793 u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
794 struct fsl_pq_mdio_info mdio_info;
795 const char *phy_mode;
796 fdt_addr_t reg;
797 ofnode parent;
798 int ret;
799
800 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
801 priv->regs = (struct tsec *)pdata->iobase;
802
803 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
804 &phandle_args)) {
805 printf("phy-handle does not exist under tsec %s\n", dev->name);
806 return -ENOENT;
807 } else {
808 int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
809
810 priv->phyaddr = reg;
811 }
812
813 parent = ofnode_get_parent(phandle_args.node);
814 if (!ofnode_valid(parent)) {
815 printf("No parent node for PHY?\n");
816 return -ENOENT;
817 }
818
819 reg = ofnode_get_addr_index(parent, 0);
820 priv->phyregs_sgmii = (struct tsec_mii_mng *)
821 (reg + TSEC_MDIO_REGS_OFFSET);
822
823 ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
824 &phandle_args);
825 if (ret == 0)
826 ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
827
828 priv->tbiaddr = tbiaddr;
829
830 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
831 if (phy_mode)
832 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
833 if (pdata->phy_interface == -1) {
834 printf("Invalid PHY interface '%s'\n", phy_mode);
835 return -EINVAL;
836 }
837 priv->interface = pdata->phy_interface;
838
839 /* Initialize flags */
840 priv->flags = TSEC_GIGABIT;
841 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
842 priv->flags |= TSEC_SGMII;
843
844 mdio_info.regs = priv->phyregs_sgmii;
845 mdio_info.name = (char *)dev->name;
846 ret = fsl_pq_mdio_init(NULL, &mdio_info);
847 if (ret)
848 return ret;
849
850 /* Reset the MAC */
851 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
852 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
853 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
854
855 priv->dev = dev;
856 priv->bus = miiphy_get_dev_by_name(dev->name);
857
858 /* Try to initialize PHY here, and return */
859 return !init_phy(priv);
860 }
861
tsec_remove(struct udevice * dev)862 int tsec_remove(struct udevice *dev)
863 {
864 struct tsec_private *priv = dev->priv;
865
866 free(priv->phydev);
867 mdio_unregister(priv->bus);
868 mdio_free(priv->bus);
869
870 return 0;
871 }
872
873 static const struct eth_ops tsec_ops = {
874 .start = tsec_init,
875 .send = tsec_send,
876 .recv = tsec_recv,
877 .free_pkt = tsec_free_pkt,
878 .stop = tsec_halt,
879 .mcast = tsec_mcast_addr,
880 };
881
882 static const struct udevice_id tsec_ids[] = {
883 { .compatible = "fsl,etsec2" },
884 { }
885 };
886
887 U_BOOT_DRIVER(eth_tsec) = {
888 .name = "tsec",
889 .id = UCLASS_ETH,
890 .of_match = tsec_ids,
891 .probe = tsec_probe,
892 .remove = tsec_remove,
893 .ops = &tsec_ops,
894 .priv_auto_alloc_size = sizeof(struct tsec_private),
895 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
896 .flags = DM_FLAG_ALLOC_PRIV_DMA,
897 };
898 #endif /* CONFIG_DM_ETH */
899