1 #include <common.h>
2 #include <dm.h>
3 #include <hwspinlock.h>
4 #include <asm/arch/gpio.h>
5 #include <asm/gpio.h>
6 #include <asm/io.h>
7 #include <dm/lists.h>
8 #include <dm/pinctrl.h>
9
10 DECLARE_GLOBAL_DATA_PTR;
11
12 #define MAX_PINS_ONE_IP 70
13 #define MODE_BITS_MASK 3
14 #define OSPEED_MASK 3
15 #define PUPD_MASK 3
16 #define OTYPE_MSK 1
17 #define AFR_MASK 0xF
18
19 struct stm32_pinctrl_priv {
20 struct hwspinlock hws;
21 int pinctrl_ngpios;
22 struct list_head gpio_dev;
23 };
24
25 struct stm32_gpio_bank {
26 struct udevice *gpio_dev;
27 struct list_head list;
28 };
29
30 #ifndef CONFIG_SPL_BUILD
31
32 static char pin_name[PINNAME_SIZE];
33 #define PINMUX_MODE_COUNT 5
34 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
35 "gpio input",
36 "gpio output",
37 "analog",
38 "unknown",
39 "alt function",
40 };
41
stm32_pinctrl_get_af(struct udevice * dev,unsigned int offset)42 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
43 {
44 struct stm32_gpio_priv *priv = dev_get_priv(dev);
45 struct stm32_gpio_regs *regs = priv->regs;
46 u32 af;
47 u32 alt_shift = (offset % 8) * 4;
48 u32 alt_index = offset / 8;
49
50 af = (readl(®s->afr[alt_index]) &
51 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
52
53 return af;
54 }
55
stm32_populate_gpio_dev_list(struct udevice * dev)56 static int stm32_populate_gpio_dev_list(struct udevice *dev)
57 {
58 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
59 struct udevice *gpio_dev;
60 struct udevice *child;
61 struct stm32_gpio_bank *gpio_bank;
62 int ret;
63
64 /*
65 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
66 * a list with all gpio device reference which belongs to the
67 * current pin-controller. This list is used to find pin_name and
68 * pin muxing
69 */
70 list_for_each_entry(child, &dev->child_head, sibling_node) {
71 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
72 &gpio_dev);
73 if (ret < 0)
74 continue;
75
76 gpio_bank = malloc(sizeof(*gpio_bank));
77 if (!gpio_bank) {
78 dev_err(dev, "Not enough memory\n");
79 return -ENOMEM;
80 }
81
82 gpio_bank->gpio_dev = gpio_dev;
83 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
84 }
85
86 return 0;
87 }
88
stm32_pinctrl_get_pins_count(struct udevice * dev)89 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
90 {
91 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
92 struct gpio_dev_priv *uc_priv;
93 struct stm32_gpio_bank *gpio_bank;
94
95 /*
96 * if get_pins_count has already been executed once on this
97 * pin-controller, no need to run it again
98 */
99 if (priv->pinctrl_ngpios)
100 return priv->pinctrl_ngpios;
101
102 if (list_empty(&priv->gpio_dev))
103 stm32_populate_gpio_dev_list(dev);
104 /*
105 * walk through all banks to retrieve the pin-controller
106 * pins number
107 */
108 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
109 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
110
111 priv->pinctrl_ngpios += uc_priv->gpio_count;
112 }
113
114 return priv->pinctrl_ngpios;
115 }
116
stm32_pinctrl_get_gpio_dev(struct udevice * dev,unsigned int selector,unsigned int * idx)117 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
118 unsigned int selector,
119 unsigned int *idx)
120 {
121 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
122 struct stm32_gpio_bank *gpio_bank;
123 struct gpio_dev_priv *uc_priv;
124 int pin_count = 0;
125
126 if (list_empty(&priv->gpio_dev))
127 stm32_populate_gpio_dev_list(dev);
128
129 /* look up for the bank which owns the requested pin */
130 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
131 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
132
133 if (selector < (pin_count + uc_priv->gpio_count)) {
134 /*
135 * we found the bank, convert pin selector to
136 * gpio bank index
137 */
138 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
139 selector - pin_count);
140 if (IS_ERR_VALUE(*idx))
141 return NULL;
142
143 return gpio_bank->gpio_dev;
144 }
145 pin_count += uc_priv->gpio_count;
146 }
147
148 return NULL;
149 }
150
stm32_pinctrl_get_pin_name(struct udevice * dev,unsigned int selector)151 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
152 unsigned int selector)
153 {
154 struct gpio_dev_priv *uc_priv;
155 struct udevice *gpio_dev;
156 unsigned int gpio_idx;
157
158 /* look up for the bank which owns the requested pin */
159 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
160 if (!gpio_dev) {
161 snprintf(pin_name, PINNAME_SIZE, "Error");
162 } else {
163 uc_priv = dev_get_uclass_priv(gpio_dev);
164
165 snprintf(pin_name, PINNAME_SIZE, "%s%d",
166 uc_priv->bank_name,
167 gpio_idx);
168 }
169
170 return pin_name;
171 }
172
stm32_pinctrl_get_pin_muxing(struct udevice * dev,unsigned int selector,char * buf,int size)173 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
174 unsigned int selector,
175 char *buf,
176 int size)
177 {
178 struct udevice *gpio_dev;
179 const char *label;
180 int mode;
181 int af_num;
182 unsigned int gpio_idx;
183
184 /* look up for the bank which owns the requested pin */
185 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
186
187 if (!gpio_dev)
188 return -ENODEV;
189
190 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
191
192 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
193 selector, gpio_idx, mode);
194
195
196 switch (mode) {
197 case GPIOF_UNKNOWN:
198 /* should never happen */
199 return -EINVAL;
200 case GPIOF_UNUSED:
201 snprintf(buf, size, "%s", pinmux_mode[mode]);
202 break;
203 case GPIOF_FUNC:
204 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
205 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
206 break;
207 case GPIOF_OUTPUT:
208 case GPIOF_INPUT:
209 snprintf(buf, size, "%s %s",
210 pinmux_mode[mode], label ? label : "");
211 break;
212 }
213
214 return 0;
215 }
216
217 #endif
218
stm32_pinctrl_probe(struct udevice * dev)219 static int stm32_pinctrl_probe(struct udevice *dev)
220 {
221 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
222 int ret;
223
224 INIT_LIST_HEAD(&priv->gpio_dev);
225
226 /* hwspinlock property is optional, just log the error */
227 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
228 if (ret)
229 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
230 __func__, ret);
231
232 return 0;
233 }
234
stm32_gpio_config(struct gpio_desc * desc,const struct stm32_gpio_ctl * ctl)235 static int stm32_gpio_config(struct gpio_desc *desc,
236 const struct stm32_gpio_ctl *ctl)
237 {
238 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
239 struct stm32_gpio_regs *regs = priv->regs;
240 struct stm32_pinctrl_priv *ctrl_priv;
241 int ret;
242 u32 index;
243
244 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
245 ctl->pupd > 2 || ctl->speed > 3)
246 return -EINVAL;
247
248 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
249 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
250 if (ret == -ETIME) {
251 dev_err(desc->dev, "HWSpinlock timeout\n");
252 return ret;
253 }
254
255 index = (desc->offset & 0x07) * 4;
256 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
257 ctl->af << index);
258
259 index = desc->offset * 2;
260 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
261 ctl->mode << index);
262 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
263 ctl->speed << index);
264 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
265
266 index = desc->offset;
267 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
268
269 hwspinlock_unlock(&ctrl_priv->hws);
270
271 return 0;
272 }
273
prep_gpio_dsc(struct stm32_gpio_dsc * gpio_dsc,u32 port_pin)274 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
275 {
276 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
277 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
278 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
279 gpio_dsc->pin);
280
281 return 0;
282 }
283
prep_gpio_ctl(struct stm32_gpio_ctl * gpio_ctl,u32 gpio_fn,int node)284 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
285 {
286 gpio_fn &= 0x00FF;
287 gpio_ctl->af = 0;
288
289 switch (gpio_fn) {
290 case 0:
291 gpio_ctl->mode = STM32_GPIO_MODE_IN;
292 break;
293 case 1 ... 16:
294 gpio_ctl->mode = STM32_GPIO_MODE_AF;
295 gpio_ctl->af = gpio_fn - 1;
296 break;
297 case 17:
298 gpio_ctl->mode = STM32_GPIO_MODE_AN;
299 break;
300 default:
301 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
302 break;
303 }
304
305 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
306
307 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
308 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
309 else
310 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
311
312 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
313 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
314 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
315 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
316 else
317 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
318
319 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
320 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
321 gpio_ctl->pupd);
322
323 return 0;
324 }
325
stm32_pinctrl_config(int offset)326 static int stm32_pinctrl_config(int offset)
327 {
328 u32 pin_mux[MAX_PINS_ONE_IP];
329 int rv, len;
330
331 /*
332 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
333 * usart1) of pin controller phandle "pinctrl-0"
334 * */
335 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
336 struct stm32_gpio_dsc gpio_dsc;
337 struct stm32_gpio_ctl gpio_ctl;
338 int i;
339
340 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
341 "pinmux", pin_mux,
342 ARRAY_SIZE(pin_mux));
343 debug("%s: no of pinmux entries= %d\n", __func__, len);
344 if (len < 0)
345 return -EINVAL;
346 for (i = 0; i < len; i++) {
347 struct gpio_desc desc;
348
349 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
350 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
351 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
352 rv = uclass_get_device_by_seq(UCLASS_GPIO,
353 gpio_dsc.port,
354 &desc.dev);
355 if (rv)
356 return rv;
357 desc.offset = gpio_dsc.pin;
358 rv = stm32_gpio_config(&desc, &gpio_ctl);
359 debug("%s: rv = %d\n\n", __func__, rv);
360 if (rv)
361 return rv;
362 }
363 }
364
365 return 0;
366 }
367
stm32_pinctrl_bind(struct udevice * dev)368 static int stm32_pinctrl_bind(struct udevice *dev)
369 {
370 ofnode node;
371 const char *name;
372 int ret;
373
374 dev_for_each_subnode(node, dev) {
375 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
376
377 ofnode_get_property(node, "gpio-controller", &ret);
378 if (ret < 0)
379 continue;
380 /* Get the name of each gpio node */
381 name = ofnode_get_name(node);
382 if (!name)
383 return -EINVAL;
384
385 /* Bind each gpio node */
386 ret = device_bind_driver_to_node(dev, "gpio_stm32",
387 name, node, NULL);
388 if (ret)
389 return ret;
390
391 debug("%s: bind %s\n", __func__, name);
392 }
393
394 return 0;
395 }
396
397 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
stm32_pinctrl_set_state(struct udevice * dev,struct udevice * config)398 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
399 {
400 return stm32_pinctrl_config(dev_of_offset(config));
401 }
402 #else /* PINCTRL_FULL */
stm32_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)403 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
404 struct udevice *periph)
405 {
406 const void *fdt = gd->fdt_blob;
407 const fdt32_t *list;
408 uint32_t phandle;
409 int config_node;
410 int size, i, ret;
411
412 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
413 if (!list)
414 return -EINVAL;
415
416 debug("%s: periph->name = %s\n", __func__, periph->name);
417
418 size /= sizeof(*list);
419 for (i = 0; i < size; i++) {
420 phandle = fdt32_to_cpu(*list++);
421
422 config_node = fdt_node_offset_by_phandle(fdt, phandle);
423 if (config_node < 0) {
424 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
425 return -EINVAL;
426 }
427
428 ret = stm32_pinctrl_config(config_node);
429 if (ret)
430 return ret;
431 }
432
433 return 0;
434 }
435 #endif /* PINCTRL_FULL */
436
437 static struct pinctrl_ops stm32_pinctrl_ops = {
438 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
439 .set_state = stm32_pinctrl_set_state,
440 #else /* PINCTRL_FULL */
441 .set_state_simple = stm32_pinctrl_set_state_simple,
442 #endif /* PINCTRL_FULL */
443 #ifndef CONFIG_SPL_BUILD
444 .get_pin_name = stm32_pinctrl_get_pin_name,
445 .get_pins_count = stm32_pinctrl_get_pins_count,
446 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
447 #endif
448 };
449
450 static const struct udevice_id stm32_pinctrl_ids[] = {
451 { .compatible = "st,stm32f429-pinctrl" },
452 { .compatible = "st,stm32f469-pinctrl" },
453 { .compatible = "st,stm32f746-pinctrl" },
454 { .compatible = "st,stm32f769-pinctrl" },
455 { .compatible = "st,stm32h743-pinctrl" },
456 { .compatible = "st,stm32mp157-pinctrl" },
457 { .compatible = "st,stm32mp157-z-pinctrl" },
458 { }
459 };
460
461 U_BOOT_DRIVER(pinctrl_stm32) = {
462 .name = "pinctrl_stm32",
463 .id = UCLASS_PINCTRL,
464 .of_match = stm32_pinctrl_ids,
465 .ops = &stm32_pinctrl_ops,
466 .bind = stm32_pinctrl_bind,
467 .probe = stm32_pinctrl_probe,
468 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
469 };
470