1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Texas Instruments' AM654 DDRSS driver
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
9 #include <common.h>
10 #include <clk.h>
11 #include <dm.h>
12 #include <ram.h>
13 #include <asm/io.h>
14 #include <power-domain.h>
15 #include <dm.h>
16 #include <asm/arch/sys_proto.h>
17 #include <power/regulator.h>
18 #include "k3-am654-ddrss.h"
19
20 #define LDELAY 10000
21
22 /* DDRSS PHY configuration register fixed values */
23 #define DDRSS_DDRPHY_RANKIDR_RANK0 0
24
25 /**
26 * struct am654_ddrss_desc - Description of ddrss integration.
27 * @dev: DDRSS device pointer
28 * @ddrss_ss_cfg: DDRSS wrapper logic region base address
29 * @ddrss_ctl_cfg: DDRSS controller region base address
30 * @ddrss_phy_cfg: DDRSS PHY region base address
31 * @ddrss_clk: DDRSS clock description
32 * @vtt_supply: VTT Supply regulator
33 * @ddrss_pwrdmn: DDRSS power domain description
34 * @params: SDRAM configuration parameters
35 */
36 struct am654_ddrss_desc {
37 struct udevice *dev;
38 void __iomem *ddrss_ss_cfg;
39 void __iomem *ddrss_ctl_cfg;
40 void __iomem *ddrss_phy_cfg;
41 struct clk ddrss_clk;
42 struct udevice *vtt_supply;
43 struct power_domain ddrcfg_pwrdmn;
44 struct power_domain ddrdata_pwrdmn;
45 struct ddrss_params params;
46 };
47
ddrss_readl(void __iomem * addr,unsigned int offset)48 static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
49 {
50 return readl(addr + offset);
51 }
52
ddrss_writel(void __iomem * addr,unsigned int offset,u32 data)53 static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
54 u32 data)
55 {
56 debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
57 writel(data, addr + offset);
58 }
59
60 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
61 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
62
am654_ddrss_get_type(struct am654_ddrss_desc * ddrss)63 static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
64 {
65 return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
66 }
67
68 /**
69 * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
70 *
71 * After detecting the DDR type this function will pause until the
72 * initialization is complete. Each DDR type has mask of multiple bits.
73 * The size of the field depends on the DDR Type. If the initialization
74 * does not complete and error will be returned and will cause the boot to halt.
75 *
76 */
am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc * ddrss)77 static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
78 {
79 u32 val, mask;
80
81 val = am654_ddrss_get_type(ddrss);
82
83 switch (val) {
84 case DDR_TYPE_LPDDR4:
85 case DDR_TYPE_DDR4:
86 mask = DDR4_STAT_MODE_MASK;
87 break;
88 case DDR_TYPE_DDR3:
89 mask = DDR3_STAT_MODE_MASK;
90 break;
91 default:
92 printf("Unsupported DDR type 0x%x\n", val);
93 return -EINVAL;
94 }
95
96 if (!wait_on_value(mask, DDR_MODE_NORMAL,
97 ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
98 return -ETIMEDOUT;
99
100 return 0;
101 }
102
103 /**
104 * am654_ddrss_ctrl_configuration() - Configure Controller specific registers
105 * @dev: corresponding ddrss device
106 */
am654_ddrss_ctrl_configuration(struct am654_ddrss_desc * ddrss)107 static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
108 {
109 struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
110 struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
111 struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
112 struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
113 struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
114 u32 val;
115
116 debug("%s: DDR controller register configuration started\n", __func__);
117
118 ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
119 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
120 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
121
122 ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
123 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
124 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
125 ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
126
127 ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
128 ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
129 ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
130 ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
131 ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
132 ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
133 ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
134
135 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
136 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
137 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
138 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
139 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
140 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
141 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
142 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
143 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
144 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
145 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
146 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14);
147 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
148 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
149
150 ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
151 ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
152
153 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
154 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
155 ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
156 ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc);
157
158 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
159 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
160 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
161 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
162 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
163 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
164 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
165 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
166 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
167 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
168 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
169 ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
170
171 ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
172 ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
173
174 /* Disable refreshes */
175 val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
176 val |= 0x01;
177 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
178
179 debug("%s: DDR controller configuration completed\n", __func__);
180 }
181
182 #define ddrss_phy_writel(off, val) \
183 do { \
184 ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \
185 sdelay(10); /* Delay at least 20 clock cycles */ \
186 } while (0)
187
188 #define ddrss_phy_readl(off) \
189 ({ \
190 u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \
191 sdelay(10); /* Delay at least 20 clock cycles */ \
192 val; \
193 })
194
195 /**
196 * am654_ddrss_phy_configuration() - Configure PHY specific registers
197 * @ddrss: corresponding ddrss device
198 */
am654_ddrss_phy_configuration(struct am654_ddrss_desc * ddrss)199 static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
200 {
201 struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
202 struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
203 struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
204 struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
205 struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
206
207 debug("%s: DDR phy register configuration started\n", __func__);
208
209 ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0);
210 ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
211 ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
212 ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
213 ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
214
215 ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2);
216 ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
217 ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
218 ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
219 ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
220
221 ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
222
223 ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
224 ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
225
226 ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
227
228 ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
229 ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
230 ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
231 ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
232 ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
233 ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
234 ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
235
236 ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
237 ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
238 ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
239
240 ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
241 ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
242 ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
243 ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
244 ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
245 ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
246 ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
247 ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11);
248 ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12);
249 ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13);
250 ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14);
251 ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22);
252
253 ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
254
255 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
256 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
257 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
258
259 ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
260 ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
261
262 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
263 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
264 ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
265 ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
266
267 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
268 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
269 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
270 ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
271
272 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
273 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
274 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
275 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
276
277 ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
278 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
279 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
280 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
281 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
282
283 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
284
285 ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
286 ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
287 ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
288 ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
289 ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
290
291 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
292 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
293 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
294
295 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
296 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
297 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
298
299 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
300 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
301 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
302
303 debug("%s: DDR phy register configuration completed\n", __func__);
304 }
305
__phy_builtin_init_routine(struct am654_ddrss_desc * ddrss,u32 init_value,u32 sts_mask,u32 err_mask)306 static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
307 u32 init_value, u32 sts_mask,
308 u32 err_mask)
309 {
310 int ret;
311
312 ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
313
314 sdelay(5); /* Delay at least 10 clock cycles */
315
316 if (!wait_on_value(sts_mask, sts_mask,
317 ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
318 return -ETIMEDOUT;
319
320 sdelay(16); /* Delay at least 32 clock cycles */
321
322 ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
323 debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
324 if (ret & err_mask)
325 return -EINVAL;
326
327 return 0;
328 }
329
write_leveling(struct am654_ddrss_desc * ddrss)330 int write_leveling(struct am654_ddrss_desc *ddrss)
331 {
332 int ret;
333
334 debug("%s: Write leveling started\n", __func__);
335
336 ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
337 PGSR0_WLERR_MASK);
338 if (ret) {
339 if (ret == -ETIMEDOUT)
340 printf("%s: ERROR: Write leveling timedout\n",
341 __func__);
342 else
343 printf("%s:ERROR: Write leveling failed\n", __func__);
344 return ret;
345 }
346
347 debug("%s: Write leveling completed\n", __func__);
348 return 0;
349 }
350
read_dqs_training(struct am654_ddrss_desc * ddrss)351 int read_dqs_training(struct am654_ddrss_desc *ddrss)
352 {
353 int ret;
354
355 debug("%s: Read DQS training started\n", __func__);
356
357 ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
358 PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
359 if (ret) {
360 if (ret == -ETIMEDOUT)
361 printf("%s: ERROR: Read DQS timedout\n", __func__);
362 else
363 printf("%s:ERROR: Read DQS Gate training failed\n",
364 __func__);
365 return ret;
366 }
367
368 debug("%s: Read DQS training completed\n", __func__);
369 return 0;
370 }
371
dqs2dq_training(struct am654_ddrss_desc * ddrss)372 int dqs2dq_training(struct am654_ddrss_desc *ddrss)
373 {
374 int ret;
375
376 debug("%s: DQS2DQ training started\n", __func__);
377
378 ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK,
379 PGSR0_DQS2DQDONE_MASK,
380 PGSR0_DQS2DQERR_MASK);
381 if (ret) {
382 if (ret == -ETIMEDOUT)
383 printf("%s: ERROR: DQS2DQ training timedout\n",
384 __func__);
385 else
386 printf("%s:ERROR: DQS2DQ training failed\n",
387 __func__);
388 return ret;
389 }
390
391 debug("%s: DQS2DQ training completed\n", __func__);
392 return 0;
393 }
394
write_leveling_adjustment(struct am654_ddrss_desc * ddrss)395 int write_leveling_adjustment(struct am654_ddrss_desc *ddrss)
396 {
397 int ret;
398
399 debug("%s: Write Leveling adjustment\n", __func__);
400 ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
401 PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
402 if (ret) {
403 if (ret == -ETIMEDOUT)
404 printf("%s:ERROR: Write Leveling adjustment timedout\n",
405 __func__);
406 else
407 printf("%s: ERROR: Write Leveling adjustment failed\n",
408 __func__);
409 return ret;
410 }
411 return 0;
412 }
413
rest_training(struct am654_ddrss_desc * ddrss)414 int rest_training(struct am654_ddrss_desc *ddrss)
415 {
416 int ret;
417
418 debug("%s: Rest of the training started\n", __func__);
419
420 debug("%s: Read Deskew adjustment\n", __func__);
421 ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
422 PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
423 if (ret) {
424 if (ret == -ETIMEDOUT)
425 printf("%s: ERROR: Read Deskew timedout\n", __func__);
426 else
427 printf("%s: ERROR: Read Deskew failed\n", __func__);
428 return ret;
429 }
430
431 debug("%s: Write Deskew adjustment\n", __func__);
432 ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
433 PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
434 if (ret) {
435 if (ret == -ETIMEDOUT)
436 printf("%s: ERROR: Write Deskew timedout\n", __func__);
437 else
438 printf("%s: ERROR: Write Deskew failed\n", __func__);
439 return ret;
440 }
441
442 debug("%s: Read Eye training\n", __func__);
443 ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
444 PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
445 if (ret) {
446 if (ret == -ETIMEDOUT)
447 printf("%s: ERROR: Read Eye training timedout\n",
448 __func__);
449 else
450 printf("%s: ERROR: Read Eye training failed\n",
451 __func__);
452 return ret;
453 }
454
455 debug("%s: Write Eye training\n", __func__);
456 ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
457 PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
458 if (ret) {
459 if (ret == -ETIMEDOUT)
460 printf("%s: ERROR: Write Eye training timedout\n",
461 __func__);
462 else
463 printf("%s: ERROR: Write Eye training failed\n",
464 __func__);
465 return ret;
466 }
467 return 0;
468 }
469
VREF_training(struct am654_ddrss_desc * ddrss)470 int VREF_training(struct am654_ddrss_desc *ddrss)
471 {
472 int ret;
473 debug("%s: VREF training\n", __func__);
474 ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
475 PGSR0_VERR_MASK);
476 if (ret) {
477 if (ret == -ETIMEDOUT)
478 printf("%s: ERROR: VREF training timedout\n", __func__);
479 else
480 printf("%s: ERROR: VREF training failed\n", __func__);
481 return ret;
482 }
483 return 0;
484 }
485
enable_dqs_pd(struct am654_ddrss_desc * ddrss)486 int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
487 {
488 u32 val;
489
490 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
491 val &= ~0xFF;
492 val |= 0xF7;
493 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
494
495 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
496 val &= ~0xFF;
497 val |= 0xF7;
498 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
499
500 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
501 val &= ~0xFF;
502 val |= 0xF7;
503 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
504
505 sdelay(16);
506 return 0;
507 }
508
disable_dqs_pd(struct am654_ddrss_desc * ddrss)509 int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
510 {
511 u32 val;
512
513 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
514 val &= ~0xFF;
515 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
516
517 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
518 val &= ~0xFF;
519 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
520
521 val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
522 val &= ~0xFF;
523 ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
524
525 sdelay(16);
526 return 0;
527 }
528
cleanup_training(struct am654_ddrss_desc * ddrss)529 int cleanup_training(struct am654_ddrss_desc *ddrss)
530 {
531 u32 val;
532 u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
533
534 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
535 dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
536 dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
537 dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
538 dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
539
540 rddly = dgsl0;
541 if (dgsl1 < rddly)
542 rddly = dgsl1;
543 if (dgsl2 < rddly)
544 rddly = dgsl2;
545 if (dgsl3 < rddly)
546 rddly = dgsl3;
547
548 rddly += 5;
549
550 /* Update rddly based on dgsl values */
551 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
552 val |= (rddly << 20);
553 ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
554
555 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
556 val |= (rddly << 20);
557 ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
558
559 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
560 val |= (rddly << 20);
561 ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
562
563 val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
564 val |= (rddly << 20);
565 ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
566
567 /*
568 * Add system latency derived from training back into rd2wr and wr2rd
569 * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
570 * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
571 */
572
573 /* Select rank 0 */
574 ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
575
576 dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
577 dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
578 dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
579 dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
580
581 /* Find maximum value across all bytes */
582 rd2wr_wr2rd = dgsl0;
583 if (dgsl1 > rd2wr_wr2rd)
584 rd2wr_wr2rd = dgsl1;
585 if (dgsl2 > rd2wr_wr2rd)
586 rd2wr_wr2rd = dgsl2;
587 if (dgsl3 > rd2wr_wr2rd)
588 rd2wr_wr2rd = dgsl3;
589
590 rd2wr_wr2rd >>= 1;
591
592 /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
593 /* Clear VSWCTL.sw_done */
594 ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
595 ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
596 /* Adjust rd2wr */
597 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
598 ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
599 (rd2wr_wr2rd << 8));
600 /* Adjust wr2rd */
601 ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
602 ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
603 rd2wr_wr2rd);
604 /* Set VSWCTL.sw_done */
605 ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
606 ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
607 /* Wait until settings are applied */
608 while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
609 /* Do nothing */
610 };
611
612 debug("%s: Rest of the training completed\n", __func__);
613 return 0;
614 }
615
616 /**
617 * am654_ddrss_init() - Initialization sequence for enabling the SDRAM
618 * device attached to ddrss.
619 * @dev: corresponding ddrss device
620 *
621 * Does all the initialization sequence that is required to get attached
622 * ddr in a working state. After this point, ddr should be accessible.
623 * Return: 0 if all went ok, else corresponding error message.
624 */
am654_ddrss_init(struct am654_ddrss_desc * ddrss)625 static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
626 {
627 int ret;
628 u32 val;
629 struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
630
631 debug("Starting DDR initialization...\n");
632
633 debug("%s(ddrss=%p)\n", __func__, ddrss);
634
635 ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
636 reg->ddrss_v2h_ctl_reg);
637
638 am654_ddrss_ctrl_configuration(ddrss);
639
640 /* Release the reset to the controller */
641 clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
642 SS_CTL_REG_CTL_ARST_MASK);
643
644 am654_ddrss_phy_configuration(ddrss);
645
646 debug("Starting DDR training...\n");
647 ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
648 if (ret) {
649 dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
650 return ret;
651 }
652
653 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
654 PGSR0_DRAM_INIT_MASK, 0);
655 if (ret) {
656 dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
657 return ret;
658 }
659
660 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
661 if (ret) {
662 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
663 __func__);
664 return ret;
665 }
666
667 val = am654_ddrss_get_type(ddrss);
668
669 switch (val) {
670 case DDR_TYPE_LPDDR4:
671
672 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
673 PGSR0_DRAM_INIT_MASK, 0);
674 if (ret) {
675 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
676 ret);
677 return ret;
678 }
679
680 /* must perform DRAM_INIT twice for LPDDR4 */
681 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
682 PGSR0_DRAM_INIT_MASK, 0);
683 if (ret) {
684 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
685 ret);
686 return ret;
687 }
688
689 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
690 if (ret) {
691 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
692 __func__);
693 return ret;
694 }
695
696 ret = write_leveling(ddrss);
697 if (ret)
698 return ret;
699
700 ret = enable_dqs_pd(ddrss);
701 if (ret)
702 return ret;
703
704 ret = read_dqs_training(ddrss);
705 if (ret)
706 return ret;
707
708 ret = disable_dqs_pd(ddrss);
709 if (ret)
710 return ret;
711
712 ret = dqs2dq_training(ddrss);
713 if (ret)
714 return ret;
715
716 ret = write_leveling_adjustment(ddrss);
717 if (ret)
718 return ret;
719
720 ret = rest_training(ddrss);
721 if (ret)
722 return ret;
723
724 ret = VREF_training(ddrss);
725 if (ret)
726 return ret;
727
728 debug("LPDDR4 training complete\n");
729 break;
730
731 case DDR_TYPE_DDR4:
732
733 debug("Starting DDR4 training\n");
734
735 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
736 PGSR0_DRAM_INIT_MASK, 0);
737 if (ret) {
738 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
739 ret);
740 return ret;
741 }
742
743 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
744 if (ret) {
745 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
746 __func__);
747 return ret;
748 }
749
750 ret = write_leveling(ddrss);
751 if (ret)
752 return ret;
753
754 ret = read_dqs_training(ddrss);
755 if (ret)
756 return ret;
757
758 ret = write_leveling_adjustment(ddrss);
759 if (ret)
760 return ret;
761
762 ret = rest_training(ddrss);
763 if (ret)
764 return ret;
765
766 ret = VREF_training(ddrss);
767 if (ret)
768 return ret;
769 debug("DDR4 training complete\n");
770 break;
771
772 case DDR_TYPE_DDR3:
773
774 debug("Starting DDR3 training\n");
775
776 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
777 PGSR0_DRAM_INIT_MASK, 0);
778 if (ret) {
779 dev_err(ddrss->dev, "DRAM initialization failed %d\n",
780 ret);
781 return ret;
782 }
783
784 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
785 if (ret) {
786 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
787 __func__);
788 return ret;
789 }
790
791 ret = write_leveling(ddrss);
792 if (ret)
793 return ret;
794
795 ret = enable_dqs_pd(ddrss);
796 if (ret)
797 return ret;
798
799 ret = read_dqs_training(ddrss);
800 if (ret)
801 return ret;
802
803 ret = disable_dqs_pd(ddrss);
804 if (ret)
805 return ret;
806
807 ret = write_leveling_adjustment(ddrss);
808 if (ret)
809 return ret;
810
811 ret = rest_training(ddrss);
812 if (ret)
813 return ret;
814
815 debug("DDR3 training complete\n");
816 break;
817 default:
818 printf("%s: ERROR: Unsupported DDR type\n", __func__);
819 return -EINVAL;
820 }
821
822 ret = cleanup_training(ddrss);
823 if (ret)
824 return ret;
825
826 /* Enabling refreshes after training is done */
827 ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
828 ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
829
830 /* Disable PUBMODE after training is done */
831 ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
832 ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
833
834 debug("Completed DDR training\n");
835
836 return 0;
837 }
838
839 /**
840 * am654_ddrss_power_on() - Enable power and clocks for ddrss
841 * @dev: corresponding ddrss device
842 *
843 * Tries to enable all the corresponding clocks to the ddrss and sets it
844 * to the right frequency and then power on the ddrss.
845 * Return: 0 if all went ok, else corresponding error message.
846 */
am654_ddrss_power_on(struct am654_ddrss_desc * ddrss)847 static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
848 {
849 int ret;
850
851 debug("%s(ddrss=%p)\n", __func__, ddrss);
852
853 ret = clk_enable(&ddrss->ddrss_clk);
854 if (ret) {
855 dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
856 return ret;
857 }
858
859 ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
860 if (ret) {
861 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
862 return ret;
863 }
864
865 ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
866 if (ret) {
867 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
868 return ret;
869 }
870
871 /* VTT enable */
872 #if CONFIG_IS_ENABLED(DM_REGULATOR)
873 device_get_supply_regulator(ddrss->dev, "vtt-supply",
874 &ddrss->vtt_supply);
875 ret = regulator_set_value(ddrss->vtt_supply, 3300000);
876 if (ret)
877 return ret;
878 debug("VTT regulator enabled\n");
879 #endif
880
881 return 0;
882 }
883
884 /**
885 * am654_ddrss_ofdata_to_priv() - generate private data from device tree
886 * @dev: corresponding ddrss device
887 *
888 * Return: 0 if all went ok, else corresponding error message.
889 */
am654_ddrss_ofdata_to_priv(struct udevice * dev)890 static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
891 {
892 struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
893 phys_addr_t reg;
894 int ret;
895
896 debug("%s(dev=%p)\n", __func__, dev);
897
898 ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
899 if (ret) {
900 dev_err(dev, "clk_get failed: %d\n", ret);
901 return ret;
902 }
903
904 ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
905 if (ret) {
906 dev_err(dev, "power_domain_get() failed: %d\n", ret);
907 return ret;
908 }
909
910 ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
911 if (ret) {
912 dev_err(dev, "power_domain_get() failed: %d\n", ret);
913 return ret;
914 }
915
916 reg = devfdt_get_addr_name(dev, "ss");
917 if (reg == FDT_ADDR_T_NONE) {
918 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
919 return -EINVAL;
920 }
921 ddrss->ddrss_ss_cfg = (void *)reg;
922
923 reg = devfdt_get_addr_name(dev, "ctl");
924 if (reg == FDT_ADDR_T_NONE) {
925 dev_err(dev, "No reg property for Controller region\n");
926 return -EINVAL;
927 }
928 ddrss->ddrss_ctl_cfg = (void *)reg;
929
930 reg = devfdt_get_addr_name(dev, "phy");
931 if (reg == FDT_ADDR_T_NONE) {
932 dev_err(dev, "No reg property for PHY region\n");
933 return -EINVAL;
934 }
935 ddrss->ddrss_phy_cfg = (void *)reg;
936
937 ret = dev_read_u32_array(dev, "ti,ss-reg",
938 (u32 *)&ddrss->params.ss_reg,
939 sizeof(ddrss->params.ss_reg) / sizeof(u32));
940 if (ret) {
941 dev_err(dev, "Cannot read ti,ss-reg params\n");
942 return ret;
943 }
944
945 ret = dev_read_u32_array(dev, "ti,ctl-reg",
946 (u32 *)&ddrss->params.ctl_reg,
947 sizeof(ddrss->params.ctl_reg) / sizeof(u32));
948 if (ret) {
949 dev_err(dev, "Cannot read ti,ctl-reg params\n");
950 return ret;
951 }
952
953 ret = dev_read_u32_array(dev, "ti,ctl-crc",
954 (u32 *)&ddrss->params.ctl_crc,
955 sizeof(ddrss->params.ctl_crc) / sizeof(u32));
956 if (ret) {
957 dev_err(dev, "Cannot read ti,ctl-crc params\n");
958 return ret;
959 }
960
961 ret = dev_read_u32_array(dev, "ti,ctl-ecc",
962 (u32 *)&ddrss->params.ctl_ecc,
963 sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
964 if (ret) {
965 dev_err(dev, "Cannot read ti,ctl-ecc params\n");
966 return ret;
967 }
968
969 ret = dev_read_u32_array(dev, "ti,ctl-map",
970 (u32 *)&ddrss->params.ctl_map,
971 sizeof(ddrss->params.ctl_map) / sizeof(u32));
972 if (ret) {
973 dev_err(dev, "Cannot read ti,ctl-map params\n");
974 return ret;
975 }
976
977 ret = dev_read_u32_array(dev, "ti,ctl-pwr",
978 (u32 *)&ddrss->params.ctl_pwr,
979 sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
980 if (ret) {
981 dev_err(dev, "Cannot read ti,ctl-pwr params\n");
982 return ret;
983 }
984
985 ret = dev_read_u32_array(dev, "ti,ctl-timing",
986 (u32 *)&ddrss->params.ctl_timing,
987 sizeof(ddrss->params.ctl_timing) /
988 sizeof(u32));
989 if (ret) {
990 dev_err(dev, "Cannot read ti,ctl-timing params\n");
991 return ret;
992 }
993
994 ret = dev_read_u32_array(dev, "ti,phy-cfg",
995 (u32 *)&ddrss->params.phy_cfg,
996 sizeof(ddrss->params.phy_cfg) / sizeof(u32));
997 if (ret) {
998 dev_err(dev, "Cannot read ti,phy-cfg params\n");
999 return ret;
1000 }
1001
1002 ret = dev_read_u32_array(dev, "ti,phy-ctl",
1003 (u32 *)&ddrss->params.phy_ctrl,
1004 sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
1005 if (ret) {
1006 dev_err(dev, "Cannot read ti,phy-ctl params\n");
1007 return ret;
1008 }
1009
1010 ret = dev_read_u32_array(dev, "ti,phy-ioctl",
1011 (u32 *)&ddrss->params.phy_ioctl,
1012 sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
1013 if (ret) {
1014 dev_err(dev, "Cannot read ti,phy-ioctl params\n");
1015 return ret;
1016 }
1017
1018 ret = dev_read_u32_array(dev, "ti,phy-timing",
1019 (u32 *)&ddrss->params.phy_timing,
1020 sizeof(ddrss->params.phy_timing) /
1021 sizeof(u32));
1022 if (ret) {
1023 dev_err(dev, "Cannot read ti,phy-timing params\n");
1024 return ret;
1025 }
1026
1027 ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
1028 sizeof(ddrss->params.phy_zq) / sizeof(u32));
1029 if (ret) {
1030 dev_err(dev, "Cannot read ti,phy-zq params\n");
1031 return ret;
1032 }
1033
1034 return ret;
1035 }
1036
1037 /**
1038 * am654_ddrss_probe() - Basic probe
1039 * @dev: corresponding ddrss device
1040 *
1041 * Return: 0 if all went ok, else corresponding error message
1042 */
am654_ddrss_probe(struct udevice * dev)1043 static int am654_ddrss_probe(struct udevice *dev)
1044 {
1045 struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
1046 int ret;
1047
1048 debug("%s(dev=%p)\n", __func__, dev);
1049
1050 ret = am654_ddrss_ofdata_to_priv(dev);
1051 if (ret)
1052 return ret;
1053
1054 ddrss->dev = dev;
1055 ret = am654_ddrss_power_on(ddrss);
1056 if (ret)
1057 return ret;
1058
1059 ret = am654_ddrss_init(ddrss);
1060
1061 return ret;
1062 }
1063
am654_ddrss_get_info(struct udevice * dev,struct ram_info * info)1064 static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
1065 {
1066 return 0;
1067 }
1068
1069 static struct ram_ops am654_ddrss_ops = {
1070 .get_info = am654_ddrss_get_info,
1071 };
1072
1073 static const struct udevice_id am654_ddrss_ids[] = {
1074 { .compatible = "ti,am654-ddrss" },
1075 { }
1076 };
1077
1078 U_BOOT_DRIVER(am654_ddrss) = {
1079 .name = "am654_ddrss",
1080 .id = UCLASS_RAM,
1081 .of_match = am654_ddrss_ids,
1082 .ops = &am654_ddrss_ops,
1083 .probe = am654_ddrss_probe,
1084 .priv_auto_alloc_size = sizeof(struct am654_ddrss_desc),
1085 };
1086