1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
4 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
5 *
6 * Modified to add device model (DM) support
7 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
8 *
9 * Modified to add DM and fdt support, removed non DM code
10 * (C) Copyright 2018 Angelo Dureghello <angelo@sysam.it>
11 */
12
13 /*
14 * Minimal serial functions needed to use one of the uart ports
15 * as serial console interface.
16 */
17
18 #include <common.h>
19 #include <dm.h>
20 #include <dm/platform_data/serial_coldfire.h>
21 #include <serial.h>
22 #include <linux/compiler.h>
23 #include <asm/immap.h>
24 #include <asm/uart.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 extern void uart_port_conf(int port);
29
mcf_serial_init_common(uart_t * uart,int port_idx,int baudrate)30 static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
31 {
32 u32 counter;
33
34 uart_port_conf(port_idx);
35
36 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
37 writeb(UART_UCR_RESET_RX, &uart->ucr);
38 writeb(UART_UCR_RESET_TX, &uart->ucr);
39 writeb(UART_UCR_RESET_ERROR, &uart->ucr);
40 writeb(UART_UCR_RESET_MR, &uart->ucr);
41 __asm__("nop");
42
43 writeb(0, &uart->uimr);
44
45 /* write to CSR: RX/TX baud rate from timers */
46 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
47
48 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
49 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
50
51 /* Setting up BaudRate */
52 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
53 counter = counter / baudrate;
54
55 /* write to CTUR: divide counter upper byte */
56 writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
57 /* write to CTLR: divide counter lower byte */
58 writeb((u8)(counter & 0x00ff), &uart->ubg2);
59
60 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
61
62 return (0);
63 }
64
mcf_serial_setbrg_common(uart_t * uart,int baudrate)65 static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
66 {
67 u32 counter;
68
69 /* Setting up BaudRate */
70 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
71 counter = counter / baudrate;
72
73 /* write to CTUR: divide counter upper byte */
74 writeb(((counter & 0xff00) >> 8), &uart->ubg1);
75 /* write to CTLR: divide counter lower byte */
76 writeb((counter & 0x00ff), &uart->ubg2);
77
78 writeb(UART_UCR_RESET_RX, &uart->ucr);
79 writeb(UART_UCR_RESET_TX, &uart->ucr);
80
81 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
82 }
83
coldfire_serial_probe(struct udevice * dev)84 static int coldfire_serial_probe(struct udevice *dev)
85 {
86 struct coldfire_serial_platdata *plat = dev->platdata;
87
88 return mcf_serial_init_common((uart_t *)plat->base,
89 plat->port, plat->baudrate);
90 }
91
coldfire_serial_putc(struct udevice * dev,const char ch)92 static int coldfire_serial_putc(struct udevice *dev, const char ch)
93 {
94 struct coldfire_serial_platdata *plat = dev->platdata;
95 uart_t *uart = (uart_t *)plat->base;
96
97 /* Wait for last character to go. */
98 if (!(readb(&uart->usr) & UART_USR_TXRDY))
99 return -EAGAIN;
100
101 writeb(ch, &uart->utb);
102
103 return 0;
104 }
105
coldfire_serial_getc(struct udevice * dev)106 static int coldfire_serial_getc(struct udevice *dev)
107 {
108 struct coldfire_serial_platdata *plat = dev->platdata;
109 uart_t *uart = (uart_t *)(plat->base);
110
111 /* Wait for a character to arrive. */
112 if (!(readb(&uart->usr) & UART_USR_RXRDY))
113 return -EAGAIN;
114
115 return readb(&uart->urb);
116 }
117
coldfire_serial_setbrg(struct udevice * dev,int baudrate)118 int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
119 {
120 struct coldfire_serial_platdata *plat = dev->platdata;
121 uart_t *uart = (uart_t *)(plat->base);
122
123 mcf_serial_setbrg_common(uart, baudrate);
124
125 return 0;
126 }
127
coldfire_serial_pending(struct udevice * dev,bool input)128 static int coldfire_serial_pending(struct udevice *dev, bool input)
129 {
130 struct coldfire_serial_platdata *plat = dev->platdata;
131 uart_t *uart = (uart_t *)(plat->base);
132
133 if (input)
134 return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
135 else
136 return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
137
138 return 0;
139 }
140
coldfire_ofdata_to_platdata(struct udevice * dev)141 static int coldfire_ofdata_to_platdata(struct udevice *dev)
142 {
143 struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
144 fdt_addr_t addr_base;
145
146 addr_base = devfdt_get_addr(dev);
147 if (addr_base == FDT_ADDR_T_NONE)
148 return -ENODEV;
149
150 plat->base = (uint32_t)addr_base;
151
152 plat->port = dev->seq;
153 plat->baudrate = gd->baudrate;
154
155 return 0;
156 }
157
158 static const struct dm_serial_ops coldfire_serial_ops = {
159 .putc = coldfire_serial_putc,
160 .pending = coldfire_serial_pending,
161 .getc = coldfire_serial_getc,
162 .setbrg = coldfire_serial_setbrg,
163 };
164
165 static const struct udevice_id coldfire_serial_ids[] = {
166 { .compatible = "fsl,mcf-uart" },
167 { }
168 };
169
170 U_BOOT_DRIVER(serial_coldfire) = {
171 .name = "serial_coldfire",
172 .id = UCLASS_SERIAL,
173 .of_match = coldfire_serial_ids,
174 .ofdata_to_platdata = coldfire_ofdata_to_platdata,
175 .platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata),
176 .probe = coldfire_serial_probe,
177 .ops = &coldfire_serial_ops,
178 .flags = DM_FLAG_PRE_RELOC,
179 };
180