1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <reset.h>
11 #include <serial.h>
12 #include <watchdog.h>
13 #include <asm/io.h>
14 #include <asm/arch/stm32.h>
15 #include "serial_stm32.h"
16
_stm32_serial_setbrg(fdt_addr_t base,struct stm32_uart_info * uart_info,u32 clock_rate,int baudrate)17 static void _stm32_serial_setbrg(fdt_addr_t base,
18 struct stm32_uart_info *uart_info,
19 u32 clock_rate,
20 int baudrate)
21 {
22 bool stm32f4 = uart_info->stm32f4;
23 u32 int_div, mantissa, fraction, oversampling;
24
25 int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
26
27 if (int_div < 16) {
28 oversampling = 8;
29 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
30 } else {
31 oversampling = 16;
32 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
33 }
34
35 mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
36 fraction = int_div % oversampling;
37
38 writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
39 }
40
stm32_serial_setbrg(struct udevice * dev,int baudrate)41 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
42 {
43 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
44
45 _stm32_serial_setbrg(plat->base, plat->uart_info,
46 plat->clock_rate, baudrate);
47
48 return 0;
49 }
50
stm32_serial_setconfig(struct udevice * dev,uint serial_config)51 static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
52 {
53 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
54 bool stm32f4 = plat->uart_info->stm32f4;
55 u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
56 u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
57 u32 config = 0;
58 uint parity = SERIAL_GET_PARITY(serial_config);
59 uint bits = SERIAL_GET_BITS(serial_config);
60 uint stop = SERIAL_GET_STOP(serial_config);
61
62 /*
63 * only parity config is implemented, check if other serial settings
64 * are the default one.
65 * (STM32F4 serial IP didn't support parity setting)
66 */
67 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
68 return -ENOTSUPP; /* not supported in driver*/
69
70 clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
71 /* update usart configuration (uart need to be disable)
72 * PCE: parity check enable
73 * PS : '0' : Even / '1' : Odd
74 * M[1:0] = '00' : 8 Data bits
75 * M[1:0] = '01' : 9 Data bits with parity
76 */
77 switch (parity) {
78 default:
79 case SERIAL_PAR_NONE:
80 config = 0;
81 break;
82 case SERIAL_PAR_ODD:
83 config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
84 break;
85 case SERIAL_PAR_EVEN:
86 config = USART_CR1_PCE | USART_CR1_M0;
87 break;
88 }
89
90 clrsetbits_le32(cr1,
91 USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
92 USART_CR1_M0,
93 config);
94 setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
95
96 return 0;
97 }
98
stm32_serial_getc(struct udevice * dev)99 static int stm32_serial_getc(struct udevice *dev)
100 {
101 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
102 bool stm32f4 = plat->uart_info->stm32f4;
103 fdt_addr_t base = plat->base;
104 u32 isr = readl(base + ISR_OFFSET(stm32f4));
105
106 if ((isr & USART_ISR_RXNE) == 0)
107 return -EAGAIN;
108
109 if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) {
110 if (!stm32f4)
111 setbits_le32(base + ICR_OFFSET,
112 USART_ICR_PCECF | USART_ICR_ORECF |
113 USART_ICR_FECF);
114 else
115 readl(base + RDR_OFFSET(stm32f4));
116 return -EIO;
117 }
118
119 return readl(base + RDR_OFFSET(stm32f4));
120 }
121
_stm32_serial_putc(fdt_addr_t base,struct stm32_uart_info * uart_info,const char c)122 static int _stm32_serial_putc(fdt_addr_t base,
123 struct stm32_uart_info *uart_info,
124 const char c)
125 {
126 bool stm32f4 = uart_info->stm32f4;
127
128 if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
129 return -EAGAIN;
130
131 writel(c, base + TDR_OFFSET(stm32f4));
132
133 return 0;
134 }
135
stm32_serial_putc(struct udevice * dev,const char c)136 static int stm32_serial_putc(struct udevice *dev, const char c)
137 {
138 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
139
140 return _stm32_serial_putc(plat->base, plat->uart_info, c);
141 }
142
stm32_serial_pending(struct udevice * dev,bool input)143 static int stm32_serial_pending(struct udevice *dev, bool input)
144 {
145 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
146 bool stm32f4 = plat->uart_info->stm32f4;
147 fdt_addr_t base = plat->base;
148
149 if (input)
150 return readl(base + ISR_OFFSET(stm32f4)) &
151 USART_ISR_RXNE ? 1 : 0;
152 else
153 return readl(base + ISR_OFFSET(stm32f4)) &
154 USART_ISR_TXE ? 0 : 1;
155 }
156
_stm32_serial_init(fdt_addr_t base,struct stm32_uart_info * uart_info)157 static void _stm32_serial_init(fdt_addr_t base,
158 struct stm32_uart_info *uart_info)
159 {
160 bool stm32f4 = uart_info->stm32f4;
161 u8 uart_enable_bit = uart_info->uart_enable_bit;
162
163 /* Disable uart-> enable fifo -> enable uart */
164 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
165 BIT(uart_enable_bit));
166 if (uart_info->has_fifo)
167 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
168 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
169 BIT(uart_enable_bit));
170 }
171
stm32_serial_probe(struct udevice * dev)172 static int stm32_serial_probe(struct udevice *dev)
173 {
174 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
175 struct clk clk;
176 struct reset_ctl reset;
177 int ret;
178
179 plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
180
181 ret = clk_get_by_index(dev, 0, &clk);
182 if (ret < 0)
183 return ret;
184
185 ret = clk_enable(&clk);
186 if (ret) {
187 dev_err(dev, "failed to enable clock\n");
188 return ret;
189 }
190
191 ret = reset_get_by_index(dev, 0, &reset);
192 if (!ret) {
193 reset_assert(&reset);
194 udelay(2);
195 reset_deassert(&reset);
196 }
197
198 plat->clock_rate = clk_get_rate(&clk);
199 if (!plat->clock_rate) {
200 clk_disable(&clk);
201 return -EINVAL;
202 };
203
204 _stm32_serial_init(plat->base, plat->uart_info);
205
206 return 0;
207 }
208
209 static const struct udevice_id stm32_serial_id[] = {
210 { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
211 { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
212 { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
213 {}
214 };
215
stm32_serial_ofdata_to_platdata(struct udevice * dev)216 static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
217 {
218 struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
219
220 plat->base = devfdt_get_addr(dev);
221 if (plat->base == FDT_ADDR_T_NONE)
222 return -EINVAL;
223
224 return 0;
225 }
226
227 static const struct dm_serial_ops stm32_serial_ops = {
228 .putc = stm32_serial_putc,
229 .pending = stm32_serial_pending,
230 .getc = stm32_serial_getc,
231 .setbrg = stm32_serial_setbrg,
232 .setconfig = stm32_serial_setconfig
233 };
234
235 U_BOOT_DRIVER(serial_stm32) = {
236 .name = "serial_stm32",
237 .id = UCLASS_SERIAL,
238 .of_match = of_match_ptr(stm32_serial_id),
239 .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
240 .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
241 .ops = &stm32_serial_ops,
242 .probe = stm32_serial_probe,
243 #if !CONFIG_IS_ENABLED(OF_CONTROL)
244 .flags = DM_FLAG_PRE_RELOC,
245 #endif
246 };
247
248 #ifdef CONFIG_DEBUG_UART_STM32
249 #include <debug_uart.h>
_debug_uart_info(void)250 static inline struct stm32_uart_info *_debug_uart_info(void)
251 {
252 struct stm32_uart_info *uart_info;
253
254 #if defined(CONFIG_STM32F4)
255 uart_info = &stm32f4_info;
256 #elif defined(CONFIG_STM32F7)
257 uart_info = &stm32f7_info;
258 #else
259 uart_info = &stm32h7_info;
260 #endif
261 return uart_info;
262 }
263
_debug_uart_init(void)264 static inline void _debug_uart_init(void)
265 {
266 fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
267 struct stm32_uart_info *uart_info = _debug_uart_info();
268
269 _stm32_serial_init(base, uart_info);
270 _stm32_serial_setbrg(base, uart_info,
271 CONFIG_DEBUG_UART_CLOCK,
272 CONFIG_BAUDRATE);
273 }
274
_debug_uart_putc(int c)275 static inline void _debug_uart_putc(int c)
276 {
277 fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
278 struct stm32_uart_info *uart_info = _debug_uart_info();
279
280 while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
281 ;
282 }
283
284 DEBUG_UART_FUNCS
285 #endif
286