1 // SPDX-License-Identifier: GPL-2.0+159
2 /*
3 * Take from dc tegra_ahub.c
4 *
5 * Copyright 2018 Google LLC
6 */
7
8 #define LOG_CATEGORY UCLASS_MISC
9
10 #include <common.h>
11 #include <dm.h>
12 #include <i2s.h>
13 #include <misc.h>
14 #include <asm/io.h>
15 #include <asm/arch-tegra/tegra_ahub.h>
16 #include <asm/arch-tegra/tegra_i2s.h>
17 #include "tegra_i2s_priv.h"
18
19 struct tegra_ahub_priv {
20 struct apbif_regs *apbif_regs;
21 struct xbar_regs *xbar_regs;
22 u32 full_mask;
23 int capacity_words; /* FIFO capacity in words */
24
25 /*
26 * This is unset intially, but is set by tegra_ahub_ioctl() called
27 * from the misc_ioctl() in tegra_sound_probe()
28 */
29 struct udevice *i2s;
30 struct udevice *dma;
31 };
32
tegra_ahub_xbar_enable_i2s(struct xbar_regs * regs,int i2s_id)33 static int tegra_ahub_xbar_enable_i2s(struct xbar_regs *regs, int i2s_id)
34 {
35 /*
36 * Enables I2S as the receiver of APBIF by writing APBIF_TX0 (0x01) to
37 * the rx0 register
38 */
39 switch (i2s_id) {
40 case 0:
41 writel(1, ®s->i2s0_rx0);
42 break;
43 case 1:
44 writel(1, ®s->i2s1_rx0);
45 break;
46 case 2:
47 writel(1, ®s->i2s2_rx0);
48 break;
49 case 3:
50 writel(1, ®s->i2s3_rx0);
51 break;
52 case 4:
53 writel(1, ®s->i2s4_rx0);
54 break;
55 default:
56 log_err("Invalid I2S component id: %d\n", i2s_id);
57 return -EINVAL;
58 }
59 return 0;
60 }
61
tegra_ahub_apbif_is_full(struct udevice * dev)62 static int tegra_ahub_apbif_is_full(struct udevice *dev)
63 {
64 struct tegra_ahub_priv *priv = dev_get_priv(dev);
65
66 return readl(&priv->apbif_regs->apbdma_live_stat) & priv->full_mask;
67 }
68
69 /**
70 * tegra_ahub_wait_for_space() - Wait for space in the FIFO
71 *
72 * @return 0 if OK, -ETIMEDOUT if no space was available in time
73 */
tegra_ahub_wait_for_space(struct udevice * dev)74 static int tegra_ahub_wait_for_space(struct udevice *dev)
75 {
76 int i = 100000;
77 ulong start;
78
79 /* Busy-wait initially, since this should take almost no time */
80 while (i--) {
81 if (!tegra_ahub_apbif_is_full(dev))
82 return 0;
83 }
84
85 /* Failed, so do a slower loop for 100ms */
86 start = get_timer(0);
87 while (tegra_ahub_apbif_is_full(dev)) {
88 if (get_timer(start) > 100)
89 return -ETIMEDOUT;
90 }
91
92 return 0;
93 }
94
tegra_ahub_apbif_send(struct udevice * dev,int offset,const void * buf,int len)95 static int tegra_ahub_apbif_send(struct udevice *dev, int offset,
96 const void *buf, int len)
97 {
98 struct tegra_ahub_priv *priv = dev_get_priv(dev);
99 const u32 *data = (const u32 *)buf;
100 ssize_t written = 0;
101
102 if (len % sizeof(*data)) {
103 log_err("Data size (%zd) must be aligned to %zd.\n", len,
104 sizeof(*data));
105 return -EFAULT;
106 }
107 while (written < len) {
108 int ret = tegra_ahub_wait_for_space(dev);
109
110 if (ret)
111 return ret;
112
113 writel(*data++, &priv->apbif_regs->channel0_txfifo);
114 written += sizeof(*data);
115 }
116
117 return written;
118 }
119
tegra_ahub_apbif_set_cif(struct udevice * dev,u32 value)120 static void tegra_ahub_apbif_set_cif(struct udevice *dev, u32 value)
121 {
122 struct tegra_ahub_priv *priv = dev_get_priv(dev);
123
124 writel(value, &priv->apbif_regs->channel0_cif_tx0_ctrl);
125 }
126
tegra_ahub_apbif_enable_channel0(struct udevice * dev,int fifo_threshold)127 static void tegra_ahub_apbif_enable_channel0(struct udevice *dev,
128 int fifo_threshold)
129 {
130 struct tegra_ahub_priv *priv = dev_get_priv(dev);
131
132 u32 ctrl = TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN |
133 TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 |
134 TEGRA_AHUB_CHANNEL_CTRL_TX_EN;
135
136 fifo_threshold--; /* fifo_threshold starts from 1 */
137 ctrl |= (fifo_threshold << TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT);
138 writel(ctrl, &priv->apbif_regs->channel0_ctrl);
139 }
140
tegra_ahub_get_cif(bool is_receive,uint channels,uint bits_per_sample,uint fifo_threshold)141 static u32 tegra_ahub_get_cif(bool is_receive, uint channels,
142 uint bits_per_sample, uint fifo_threshold)
143 {
144 uint audio_bits = (bits_per_sample >> 2) - 1;
145 u32 val;
146
147 channels--; /* Channels in CIF starts from 1 */
148 fifo_threshold--; /* FIFO threshold starts from 1 */
149 /* Assume input and output are always using same channel / bits */
150 val = channels << TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT |
151 channels << TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT |
152 audio_bits << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT |
153 audio_bits << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT |
154 fifo_threshold << TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT |
155 (is_receive ? TEGRA_AUDIOCIF_DIRECTION_RX <<
156 TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT : 0);
157
158 return val;
159 }
160
tegra_ahub_enable(struct udevice * dev)161 static int tegra_ahub_enable(struct udevice *dev)
162 {
163 struct tegra_ahub_priv *priv = dev_get_priv(dev);
164 struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(priv->i2s);
165 u32 cif_ctrl = 0;
166 int ret;
167
168 /* We use APBIF channel0 as a sender */
169 priv->full_mask = TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL;
170 priv->capacity_words = 8;
171
172 /*
173 * FIFO is inactive until (fifo_threshold) of words are sent. For
174 * better performance, we want to set it to half of capacity.
175 */
176 u32 fifo_threshold = priv->capacity_words / 2;
177
178 /*
179 * Setup audio client interface (ACIF): APBIF (channel0) as sender and
180 * I2S as receiver
181 */
182 cif_ctrl = tegra_ahub_get_cif(true, uc_priv->channels,
183 uc_priv->bitspersample, fifo_threshold);
184 tegra_i2s_set_cif_tx_ctrl(priv->i2s, cif_ctrl);
185
186 cif_ctrl = tegra_ahub_get_cif(false, uc_priv->channels,
187 uc_priv->bitspersample, fifo_threshold);
188 tegra_ahub_apbif_set_cif(dev, cif_ctrl);
189 tegra_ahub_apbif_enable_channel0(dev, fifo_threshold);
190
191 ret = tegra_ahub_xbar_enable_i2s(priv->xbar_regs, uc_priv->id);
192 if (ret)
193 return ret;
194 log_debug("ahub: channels=%d, bitspersample=%d, cif_ctrl=%x, fifo_threshold=%d, id=%d\n",
195 uc_priv->channels, uc_priv->bitspersample, cif_ctrl,
196 fifo_threshold, uc_priv->id);
197
198 return 0;
199 }
200
tegra_ahub_ioctl(struct udevice * dev,unsigned long request,void * buf)201 static int tegra_ahub_ioctl(struct udevice *dev, unsigned long request,
202 void *buf)
203 {
204 struct tegra_ahub_priv *priv = dev_get_priv(dev);
205
206 if (request != AHUB_MISCOP_SET_I2S)
207 return -ENOSYS;
208
209 priv->i2s = *(struct udevice **)buf;
210 log_debug("i2s set to '%s'\n", priv->i2s->name);
211
212 return tegra_ahub_enable(dev);
213 }
214
tegra_ahub_probe(struct udevice * dev)215 static int tegra_ahub_probe(struct udevice *dev)
216 {
217 struct tegra_ahub_priv *priv = dev_get_priv(dev);
218 ulong addr;
219
220 addr = dev_read_addr_index(dev, 0);
221 if (addr == FDT_ADDR_T_NONE) {
222 log_debug("Invalid apbif address\n");
223 return -EINVAL;
224 }
225 priv->apbif_regs = (struct apbif_regs *)addr;
226
227 addr = dev_read_addr_index(dev, 1);
228 if (addr == FDT_ADDR_T_NONE) {
229 log_debug("Invalid xbar address\n");
230 return -EINVAL;
231 }
232 priv->xbar_regs = (struct xbar_regs *)addr;
233 log_debug("ahub apbif_regs=%p, xbar_regs=%p\n", priv->apbif_regs,
234 priv->xbar_regs);
235
236 return 0;
237 }
238
239 static struct misc_ops tegra_ahub_ops = {
240 .write = tegra_ahub_apbif_send,
241 .ioctl = tegra_ahub_ioctl,
242 };
243
244 static const struct udevice_id tegra_ahub_ids[] = {
245 { .compatible = "nvidia,tegra124-ahub" },
246 { }
247 };
248
249 U_BOOT_DRIVER(tegra_ahub) = {
250 .name = "tegra_ahub",
251 .id = UCLASS_MISC,
252 .of_match = tegra_ahub_ids,
253 .ops = &tegra_ahub_ops,
254 .probe = tegra_ahub_probe,
255 .priv_auto_alloc_size = sizeof(struct tegra_ahub_priv),
256 };
257