1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 SiFive, Inc.
4 * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
5 *
6 * SiFive SPI controller driver (master mode only)
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <malloc.h>
12 #include <spi.h>
13 #include <asm/io.h>
14 #include <linux/log2.h>
15 #include <clk.h>
16
17 #define SIFIVE_SPI_MAX_CS 32
18
19 #define SIFIVE_SPI_DEFAULT_DEPTH 8
20 #define SIFIVE_SPI_DEFAULT_BITS 8
21
22 /* register offsets */
23 #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
24 #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
25 #define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
26 #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
27 #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
28 #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
29 #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
30 #define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
31 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
32 #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
33 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
34 #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
35 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
36 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
37 #define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
38 #define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
39
40 /* sckdiv bits */
41 #define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
42
43 /* sckmode bits */
44 #define SIFIVE_SPI_SCKMODE_PHA BIT(0)
45 #define SIFIVE_SPI_SCKMODE_POL BIT(1)
46 #define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
47 SIFIVE_SPI_SCKMODE_POL)
48
49 /* csmode bits */
50 #define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
51 #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
52 #define SIFIVE_SPI_CSMODE_MODE_OFF 3U
53
54 /* delay0 bits */
55 #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
56 #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
57 #define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
58 #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
59
60 /* delay1 bits */
61 #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
62 #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
63 #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
64 #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
65
66 /* fmt bits */
67 #define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
68 #define SIFIVE_SPI_FMT_PROTO_DUAL 1U
69 #define SIFIVE_SPI_FMT_PROTO_QUAD 2U
70 #define SIFIVE_SPI_FMT_PROTO_MASK 3U
71 #define SIFIVE_SPI_FMT_ENDIAN BIT(2)
72 #define SIFIVE_SPI_FMT_DIR BIT(3)
73 #define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
74 #define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
75
76 /* txdata bits */
77 #define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
78 #define SIFIVE_SPI_TXDATA_FULL BIT(31)
79
80 /* rxdata bits */
81 #define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
82 #define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
83
84 /* ie and ip bits */
85 #define SIFIVE_SPI_IP_TXWM BIT(0)
86 #define SIFIVE_SPI_IP_RXWM BIT(1)
87
88 struct sifive_spi {
89 void *regs; /* base address of the registers */
90 u32 fifo_depth;
91 u32 bits_per_word;
92 u32 cs_inactive; /* Level of the CS pins when inactive*/
93 u32 freq;
94 u32 num_cs;
95 };
96
sifive_spi_prep_device(struct sifive_spi * spi,struct dm_spi_slave_platdata * slave)97 static void sifive_spi_prep_device(struct sifive_spi *spi,
98 struct dm_spi_slave_platdata *slave)
99 {
100 /* Update the chip select polarity */
101 if (slave->mode & SPI_CS_HIGH)
102 spi->cs_inactive &= ~BIT(slave->cs);
103 else
104 spi->cs_inactive |= BIT(slave->cs);
105 writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
106
107 /* Select the correct device */
108 writel(slave->cs, spi->regs + SIFIVE_SPI_REG_CSID);
109 }
110
sifive_spi_set_cs(struct sifive_spi * spi,struct dm_spi_slave_platdata * slave)111 static int sifive_spi_set_cs(struct sifive_spi *spi,
112 struct dm_spi_slave_platdata *slave)
113 {
114 u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
115
116 if (slave->mode & SPI_CS_HIGH)
117 cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
118
119 writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
120
121 return 0;
122 }
123
sifive_spi_clear_cs(struct sifive_spi * spi)124 static void sifive_spi_clear_cs(struct sifive_spi *spi)
125 {
126 writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
127 }
128
sifive_spi_prep_transfer(struct sifive_spi * spi,bool is_rx_xfer,struct dm_spi_slave_platdata * slave)129 static void sifive_spi_prep_transfer(struct sifive_spi *spi,
130 bool is_rx_xfer,
131 struct dm_spi_slave_platdata *slave)
132 {
133 u32 cr;
134
135 /* Modify the SPI protocol mode */
136 cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
137
138 /* Bits per word ? */
139 cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
140 cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
141
142 /* LSB first? */
143 cr &= ~SIFIVE_SPI_FMT_ENDIAN;
144 if (slave->mode & SPI_LSB_FIRST)
145 cr |= SIFIVE_SPI_FMT_ENDIAN;
146
147 /* Number of wires ? */
148 cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
149 if ((slave->mode & SPI_TX_QUAD) || (slave->mode & SPI_RX_QUAD))
150 cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
151 else if ((slave->mode & SPI_TX_DUAL) || (slave->mode & SPI_RX_DUAL))
152 cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
153 else
154 cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
155
156 /* SPI direction in/out ? */
157 cr &= ~SIFIVE_SPI_FMT_DIR;
158 if (!is_rx_xfer)
159 cr |= SIFIVE_SPI_FMT_DIR;
160
161 writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
162 }
163
sifive_spi_rx(struct sifive_spi * spi,u8 * rx_ptr)164 static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
165 {
166 u32 data;
167
168 do {
169 data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
170 } while (data & SIFIVE_SPI_RXDATA_EMPTY);
171
172 if (rx_ptr)
173 *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
174 }
175
sifive_spi_tx(struct sifive_spi * spi,const u8 * tx_ptr)176 static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
177 {
178 u32 data;
179 u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
180 SIFIVE_SPI_TXDATA_DATA_MASK;
181
182 do {
183 data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
184 } while (data & SIFIVE_SPI_TXDATA_FULL);
185
186 writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
187 }
188
sifive_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)189 static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
190 const void *dout, void *din, unsigned long flags)
191 {
192 struct udevice *bus = dev->parent;
193 struct sifive_spi *spi = dev_get_priv(bus);
194 struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
195 const unsigned char *tx_ptr = dout;
196 u8 *rx_ptr = din;
197 u32 remaining_len;
198 int ret;
199
200 if (flags & SPI_XFER_BEGIN) {
201 sifive_spi_prep_device(spi, slave);
202
203 ret = sifive_spi_set_cs(spi, slave);
204 if (ret)
205 return ret;
206 }
207
208 sifive_spi_prep_transfer(spi, true, slave);
209
210 remaining_len = bitlen / 8;
211
212 while (remaining_len) {
213 int n_words, tx_words, rx_words;
214
215 n_words = min(remaining_len, spi->fifo_depth);
216
217 /* Enqueue n_words for transmission */
218 if (tx_ptr) {
219 for (tx_words = 0; tx_words < n_words; ++tx_words) {
220 sifive_spi_tx(spi, tx_ptr);
221 sifive_spi_rx(spi, NULL);
222 tx_ptr++;
223 }
224 }
225
226 /* Read out all the data from the RX FIFO */
227 if (rx_ptr) {
228 for (rx_words = 0; rx_words < n_words; ++rx_words) {
229 sifive_spi_tx(spi, NULL);
230 sifive_spi_rx(spi, rx_ptr);
231 rx_ptr++;
232 }
233 }
234
235 remaining_len -= n_words;
236 }
237
238 if (flags & SPI_XFER_END)
239 sifive_spi_clear_cs(spi);
240
241 return 0;
242 }
243
sifive_spi_set_speed(struct udevice * bus,uint speed)244 static int sifive_spi_set_speed(struct udevice *bus, uint speed)
245 {
246 struct sifive_spi *spi = dev_get_priv(bus);
247 u32 scale;
248
249 if (speed > spi->freq)
250 speed = spi->freq;
251
252 /* Cofigure max speed */
253 scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
254 & SIFIVE_SPI_SCKDIV_DIV_MASK;
255 writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
256
257 return 0;
258 }
259
sifive_spi_set_mode(struct udevice * bus,uint mode)260 static int sifive_spi_set_mode(struct udevice *bus, uint mode)
261 {
262 struct sifive_spi *spi = dev_get_priv(bus);
263 u32 cr;
264
265 /* Switch clock mode bits */
266 cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
267 ~SIFIVE_SPI_SCKMODE_MODE_MASK;
268 if (mode & SPI_CPHA)
269 cr |= SIFIVE_SPI_SCKMODE_PHA;
270 if (mode & SPI_CPOL)
271 cr |= SIFIVE_SPI_SCKMODE_POL;
272
273 writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
274
275 return 0;
276 }
277
sifive_spi_cs_info(struct udevice * bus,uint cs,struct spi_cs_info * info)278 static int sifive_spi_cs_info(struct udevice *bus, uint cs,
279 struct spi_cs_info *info)
280 {
281 struct sifive_spi *spi = dev_get_priv(bus);
282
283 if (cs >= spi->num_cs)
284 return -EINVAL;
285
286 return 0;
287 }
288
sifive_spi_init_hw(struct sifive_spi * spi)289 static void sifive_spi_init_hw(struct sifive_spi *spi)
290 {
291 u32 cs_bits;
292
293 /* probe the number of CS lines */
294 spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
295 writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
296 cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
297 writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
298 if (!cs_bits) {
299 printf("Could not auto probe CS lines\n");
300 return;
301 }
302
303 spi->num_cs = ilog2(cs_bits) + 1;
304 if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
305 printf("Invalid number of spi slaves\n");
306 return;
307 }
308
309 /* Watermark interrupts are disabled by default */
310 writel(0, spi->regs + SIFIVE_SPI_REG_IE);
311
312 /* Set CS/SCK Delays and Inactive Time to defaults */
313 writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
314 spi->regs + SIFIVE_SPI_REG_DELAY0);
315 writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
316 spi->regs + SIFIVE_SPI_REG_DELAY1);
317
318 /* Exit specialized memory-mapped SPI flash mode */
319 writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
320 }
321
sifive_spi_probe(struct udevice * bus)322 static int sifive_spi_probe(struct udevice *bus)
323 {
324 struct sifive_spi *spi = dev_get_priv(bus);
325 struct clk clkdev;
326 int ret;
327
328 spi->regs = (void *)(ulong)dev_remap_addr(bus);
329 if (!spi->regs)
330 return -ENODEV;
331
332 spi->fifo_depth = dev_read_u32_default(bus,
333 "sifive,fifo-depth",
334 SIFIVE_SPI_DEFAULT_DEPTH);
335
336 spi->bits_per_word = dev_read_u32_default(bus,
337 "sifive,max-bits-per-word",
338 SIFIVE_SPI_DEFAULT_BITS);
339
340 ret = clk_get_by_index(bus, 0, &clkdev);
341 if (ret)
342 return ret;
343 spi->freq = clk_get_rate(&clkdev);
344
345 /* init the sifive spi hw */
346 sifive_spi_init_hw(spi);
347
348 return 0;
349 }
350
351 static const struct dm_spi_ops sifive_spi_ops = {
352 .xfer = sifive_spi_xfer,
353 .set_speed = sifive_spi_set_speed,
354 .set_mode = sifive_spi_set_mode,
355 .cs_info = sifive_spi_cs_info,
356 };
357
358 static const struct udevice_id sifive_spi_ids[] = {
359 { .compatible = "sifive,spi0" },
360 { }
361 };
362
363 U_BOOT_DRIVER(sifive_spi) = {
364 .name = "sifive_spi",
365 .id = UCLASS_SPI,
366 .of_match = sifive_spi_ids,
367 .ops = &sifive_spi_ops,
368 .priv_auto_alloc_size = sizeof(struct sifive_spi),
369 .probe = sifive_spi_probe,
370 };
371