1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * uniphier_spi.c - Socionext UniPhier SPI driver
4 * Copyright 2019 Socionext, Inc.
5 */
6
7 #include <clk.h>
8 #include <common.h>
9 #include <dm.h>
10 #include <time.h>
11 #include <linux/bitfield.h>
12 #include <linux/io.h>
13 #include <spi.h>
14 #include <wait_bit.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define SSI_CTL 0x00
19 #define SSI_CTL_EN BIT(0)
20
21 #define SSI_CKS 0x04
22 #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
23 #define SSI_CKS_CKPHS BIT(14)
24 #define SSI_CKS_CKINIT BIT(13)
25 #define SSI_CKS_CKDLY BIT(12)
26
27 #define SSI_TXWDS 0x08
28 #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
29 #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
30 #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
31
32 #define SSI_RXWDS 0x0c
33 #define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
34 #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
35
36 #define SSI_FPS 0x10
37 #define SSI_FPS_FSPOL BIT(15)
38 #define SSI_FPS_FSTRT BIT(14)
39
40 #define SSI_SR 0x14
41 #define SSI_SR_BUSY BIT(7)
42 #define SSI_SR_TNF BIT(5)
43 #define SSI_SR_RNE BIT(0)
44
45 #define SSI_IE 0x18
46
47 #define SSI_IC 0x1c
48 #define SSI_IC_TCIC BIT(4)
49 #define SSI_IC_RCIC BIT(3)
50 #define SSI_IC_RORIC BIT(0)
51
52 #define SSI_FC 0x20
53 #define SSI_FC_TXFFL BIT(12)
54 #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
55 #define SSI_FC_RXFFL BIT(4)
56 #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
57
58 #define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
59
60 #define SSI_FIFO_DEPTH 8U
61
62 #define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
63 #define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
64
65 #define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
66
67 struct uniphier_spi_platdata {
68 void __iomem *base;
69 u32 frequency; /* input frequency */
70 u32 speed_hz;
71 uint deactivate_delay_us; /* Delay to wait after deactivate */
72 uint activate_delay_us; /* Delay to wait after activate */
73 };
74
75 struct uniphier_spi_priv {
76 void __iomem *base;
77 u8 mode;
78 u8 fifo_depth;
79 u8 bits_per_word;
80 ulong last_transaction_us; /* Time of last transaction end */
81 };
82
uniphier_spi_enable(struct uniphier_spi_priv * priv,int enable)83 static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
84 {
85 u32 val;
86
87 val = readl(priv->base + SSI_CTL);
88 if (enable)
89 val |= SSI_CTL_EN;
90 else
91 val &= ~SSI_CTL_EN;
92 writel(val, priv->base + SSI_CTL);
93 }
94
uniphier_spi_regdump(struct uniphier_spi_priv * priv)95 static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
96 {
97 pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
98 pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
99 pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
100 pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
101 pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
102 pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
103 pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
104 pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
105 pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
106 pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
107 }
108
spi_cs_activate(struct udevice * dev)109 static void spi_cs_activate(struct udevice *dev)
110 {
111 struct udevice *bus = dev->parent;
112 struct uniphier_spi_platdata *plat = bus->platdata;
113 struct uniphier_spi_priv *priv = dev_get_priv(bus);
114 ulong delay_us; /* The delay completed so far */
115 u32 val;
116
117 /* If it's too soon to do another transaction, wait */
118 if (plat->deactivate_delay_us && priv->last_transaction_us) {
119 delay_us = timer_get_us() - priv->last_transaction_us;
120 if (delay_us < plat->deactivate_delay_us)
121 udelay(plat->deactivate_delay_us - delay_us);
122 }
123
124 val = readl(priv->base + SSI_FPS);
125 if (priv->mode & SPI_CS_HIGH)
126 val |= SSI_FPS_FSPOL;
127 else
128 val &= ~SSI_FPS_FSPOL;
129 writel(val, priv->base + SSI_FPS);
130
131 if (plat->activate_delay_us)
132 udelay(plat->activate_delay_us);
133 }
134
spi_cs_deactivate(struct udevice * dev)135 static void spi_cs_deactivate(struct udevice *dev)
136 {
137 struct udevice *bus = dev->parent;
138 struct uniphier_spi_platdata *plat = bus->platdata;
139 struct uniphier_spi_priv *priv = dev_get_priv(bus);
140 u32 val;
141
142 val = readl(priv->base + SSI_FPS);
143 if (priv->mode & SPI_CS_HIGH)
144 val &= ~SSI_FPS_FSPOL;
145 else
146 val |= SSI_FPS_FSPOL;
147 writel(val, priv->base + SSI_FPS);
148
149 /* Remember time of this transaction so we can honour the bus delay */
150 if (plat->deactivate_delay_us)
151 priv->last_transaction_us = timer_get_us();
152 }
153
uniphier_spi_claim_bus(struct udevice * dev)154 static int uniphier_spi_claim_bus(struct udevice *dev)
155 {
156 struct udevice *bus = dev->parent;
157 struct uniphier_spi_priv *priv = dev_get_priv(bus);
158 u32 val, size;
159
160 uniphier_spi_enable(priv, false);
161
162 /* disable interrupts */
163 writel(0, priv->base + SSI_IE);
164
165 /* bits_per_word */
166 size = priv->bits_per_word;
167 val = readl(priv->base + SSI_TXWDS);
168 val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
169 val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
170 val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
171 writel(val, priv->base + SSI_TXWDS);
172
173 val = readl(priv->base + SSI_RXWDS);
174 val &= ~SSI_RXWDS_DTLEN_MASK;
175 val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
176 writel(val, priv->base + SSI_RXWDS);
177
178 /* reset FIFOs */
179 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
180 writel(val, priv->base + SSI_FC);
181
182 /* FIFO threthold */
183 val = readl(priv->base + SSI_FC);
184 val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
185 val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
186 val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
187 writel(val, priv->base + SSI_FC);
188
189 /* clear interrupts */
190 writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
191 priv->base + SSI_IC);
192
193 uniphier_spi_enable(priv, true);
194
195 return 0;
196 }
197
uniphier_spi_release_bus(struct udevice * dev)198 static int uniphier_spi_release_bus(struct udevice *dev)
199 {
200 struct udevice *bus = dev->parent;
201 struct uniphier_spi_priv *priv = dev_get_priv(bus);
202
203 uniphier_spi_enable(priv, false);
204
205 return 0;
206 }
207
uniphier_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)208 static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
209 const void *dout, void *din, unsigned long flags)
210 {
211 struct udevice *bus = dev->parent;
212 struct uniphier_spi_priv *priv = dev_get_priv(bus);
213 const u8 *tx_buf = dout;
214 u8 *rx_buf = din, buf;
215 u32 len = bitlen / 8;
216 u32 tx_len, rx_len;
217 u32 ts, status;
218 int ret = 0;
219
220 if (bitlen % 8) {
221 dev_err(dev, "Non byte aligned SPI transfer\n");
222 return -EINVAL;
223 }
224
225 if (flags & SPI_XFER_BEGIN)
226 spi_cs_activate(dev);
227
228 uniphier_spi_enable(priv, true);
229
230 ts = get_timer(0);
231 tx_len = len;
232 rx_len = len;
233
234 uniphier_spi_regdump(priv);
235
236 while (tx_len || rx_len) {
237 ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
238 SSI_REG_TIMEOUT * 1000, false);
239 if (ret) {
240 if (ret == -ETIMEDOUT)
241 dev_err(dev, "access timeout\n");
242 break;
243 }
244
245 status = readl(priv->base + SSI_SR);
246 /* write the data into TX */
247 if (tx_len && (status & SSI_SR_TNF)) {
248 buf = tx_buf ? *tx_buf++ : 0;
249 writel(buf, priv->base + SSI_XDR);
250 tx_len--;
251 }
252
253 /* read the data from RX */
254 if (rx_len && (status & SSI_SR_RNE)) {
255 buf = readl(priv->base + SSI_XDR);
256 if (rx_buf)
257 *rx_buf++ = buf;
258 rx_len--;
259 }
260
261 if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
262 dev_err(dev, "transfer timeout\n");
263 ret = -ETIMEDOUT;
264 break;
265 }
266 }
267
268 if (flags & SPI_XFER_END)
269 spi_cs_deactivate(dev);
270
271 uniphier_spi_enable(priv, false);
272
273 return ret;
274 }
275
uniphier_spi_set_speed(struct udevice * bus,uint speed)276 static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
277 {
278 struct uniphier_spi_platdata *plat = bus->platdata;
279 struct uniphier_spi_priv *priv = dev_get_priv(bus);
280 u32 val, ckdiv;
281
282 if (speed > plat->frequency)
283 speed = plat->frequency;
284
285 /* baudrate */
286 ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
287 ckdiv = round_up(ckdiv, 2);
288
289 val = readl(priv->base + SSI_CKS);
290 val &= ~SSI_CKS_CKRAT_MASK;
291 val |= ckdiv & SSI_CKS_CKRAT_MASK;
292 writel(val, priv->base + SSI_CKS);
293
294 return 0;
295 }
296
uniphier_spi_set_mode(struct udevice * bus,uint mode)297 static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
298 {
299 struct uniphier_spi_priv *priv = dev_get_priv(bus);
300 u32 val1, val2;
301
302 /*
303 * clock setting
304 * CKPHS capture timing. 0:rising edge, 1:falling edge
305 * CKINIT clock initial level. 0:low, 1:high
306 * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
307 * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
308 *
309 * frame setting
310 * FSPOL frame signal porarity. 0: low, 1: high
311 * FSTRT start frame timing
312 * 0: rising edge of clock, 1: falling edge of clock
313 */
314 val1 = readl(priv->base + SSI_CKS);
315 val2 = readl(priv->base + SSI_FPS);
316
317 switch (mode & (SPI_CPOL | SPI_CPHA)) {
318 case SPI_MODE_0:
319 /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
320 val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
321 val1 &= ~SSI_CKS_CKINIT;
322 val2 &= ~SSI_FPS_FSTRT;
323 break;
324 case SPI_MODE_1:
325 /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
326 val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
327 val2 |= SSI_FPS_FSTRT;
328 break;
329 case SPI_MODE_2:
330 /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
331 val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
332 val1 &= ~SSI_CKS_CKPHS;
333 val2 |= SSI_FPS_FSTRT;
334 break;
335 case SPI_MODE_3:
336 /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
337 val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
338 val1 &= ~SSI_CKS_CKDLY;
339 val2 &= ~SSI_FPS_FSTRT;
340 break;
341 }
342
343 writel(val1, priv->base + SSI_CKS);
344 writel(val2, priv->base + SSI_FPS);
345
346 /* format */
347 val1 = readl(priv->base + SSI_TXWDS);
348 val2 = readl(priv->base + SSI_RXWDS);
349 if (mode & SPI_LSB_FIRST) {
350 val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
351 val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
352 }
353 writel(val1, priv->base + SSI_TXWDS);
354 writel(val2, priv->base + SSI_RXWDS);
355
356 priv->mode = mode;
357
358 return 0;
359 }
360
uniphier_spi_ofdata_to_platdata(struct udevice * bus)361 static int uniphier_spi_ofdata_to_platdata(struct udevice *bus)
362 {
363 struct uniphier_spi_platdata *plat = bus->platdata;
364 const void *blob = gd->fdt_blob;
365 int node = dev_of_offset(bus);
366
367 plat->base = devfdt_get_addr_ptr(bus);
368
369 plat->frequency =
370 fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
371 plat->deactivate_delay_us =
372 fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
373 plat->activate_delay_us =
374 fdtdec_get_int(blob, node, "spi-activate-delay", 0);
375 plat->speed_hz = plat->frequency / 2;
376
377 return 0;
378 }
379
uniphier_spi_probe(struct udevice * bus)380 static int uniphier_spi_probe(struct udevice *bus)
381 {
382 struct uniphier_spi_platdata *plat = dev_get_platdata(bus);
383 struct uniphier_spi_priv *priv = dev_get_priv(bus);
384
385 priv->base = plat->base;
386 priv->fifo_depth = SSI_FIFO_DEPTH;
387 priv->bits_per_word = 8;
388
389 return 0;
390 }
391
392 static const struct dm_spi_ops uniphier_spi_ops = {
393 .claim_bus = uniphier_spi_claim_bus,
394 .release_bus = uniphier_spi_release_bus,
395 .xfer = uniphier_spi_xfer,
396 .set_speed = uniphier_spi_set_speed,
397 .set_mode = uniphier_spi_set_mode,
398 };
399
400 static const struct udevice_id uniphier_spi_ids[] = {
401 { .compatible = "socionext,uniphier-scssi" },
402 { /* Sentinel */ }
403 };
404
405 U_BOOT_DRIVER(uniphier_spi) = {
406 .name = "uniphier_spi",
407 .id = UCLASS_SPI,
408 .of_match = uniphier_spi_ids,
409 .ops = &uniphier_spi_ops,
410 .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata,
411 .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata),
412 .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv),
413 .probe = uniphier_spi_probe,
414 };
415