1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Motorola MC5272C3 board. 4 * 5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6 */ 7 8 /* 9 * board/config.h - configuration options, board specific 10 */ 11 12 #ifndef _M5272C3_H 13 #define _M5272C3_H 14 15 /* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 #define CONFIG_MCFTMR 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 26 27 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 28 29 /* Configuration for environment 30 * Environment is embedded in u-boot in the second sector of the flash 31 */ 32 33 #define LDS_BOARD_TEXT \ 34 . = DEFINED(env_offset) ? env_offset : .; \ 35 env/embedded.o(.text); 36 37 /* 38 * BOOTP options 39 */ 40 #define CONFIG_BOOTP_BOOTFILESIZE 41 42 /* 43 * Command line configuration. 44 */ 45 46 #define CONFIG_MCFFEC 47 #ifdef CONFIG_MCFFEC 48 # define CONFIG_MII_INIT 1 49 # define CONFIG_SYS_DISCOVER_PHY 50 # define CONFIG_SYS_RX_ETH_BUFFER 8 51 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 52 53 # define CONFIG_SYS_FEC0_PINMUX 0 54 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 55 # define MCFFEC_TOUT_LOOP 50000 56 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 57 # ifndef CONFIG_SYS_DISCOVER_PHY 58 # define FECDUPLEX FULL 59 # define FECSPEED _100BASET 60 # else 61 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63 # endif 64 # endif /* CONFIG_SYS_DISCOVER_PHY */ 65 #endif 66 67 #ifdef CONFIG_MCFFEC 68 # define CONFIG_IPADDR 192.162.1.2 69 # define CONFIG_NETMASK 255.255.255.0 70 # define CONFIG_SERVERIP 192.162.1.1 71 # define CONFIG_GATEWAYIP 192.162.1.1 72 #endif /* CONFIG_MCFFEC */ 73 74 #define CONFIG_HOSTNAME "M5272C3" 75 #define CONFIG_EXTRA_ENV_SETTINGS \ 76 "netdev=eth0\0" \ 77 "loadaddr=10000\0" \ 78 "u-boot=u-boot.bin\0" \ 79 "load=tftp ${loadaddr) ${u-boot}\0" \ 80 "upd=run load; run prog\0" \ 81 "prog=prot off ffe00000 ffe3ffff;" \ 82 "era ffe00000 ffe3ffff;" \ 83 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 84 "save\0" \ 85 "" 86 87 #define CONFIG_SYS_LOAD_ADDR 0x20000 88 #define CONFIG_SYS_MEMTEST_START 0x400 89 #define CONFIG_SYS_MEMTEST_END 0x380000 90 #define CONFIG_SYS_CLK 66000000 91 92 /* 93 * Low Level Configuration Settings 94 * (address mappings, register initial values, etc.) 95 * You should know what you are doing if you make changes here. 96 */ 97 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 98 #define CONFIG_SYS_SCR 0x0003 99 #define CONFIG_SYS_SPR 0xffff 100 101 /*----------------------------------------------------------------------- 102 * Definitions for initial stack pointer and data area (in DPRAM) 103 */ 104 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 105 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 106 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 107 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 108 109 /*----------------------------------------------------------------------- 110 * Start addresses for the final memory configuration 111 * (Set up by the startup code) 112 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 113 */ 114 #define CONFIG_SYS_SDRAM_BASE 0x00000000 115 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ 116 #define CONFIG_SYS_FLASH_BASE 0xffe00000 117 118 #ifdef CONFIG_MONITOR_IS_IN_RAM 119 #define CONFIG_SYS_MONITOR_BASE 0x20000 120 #else 121 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 122 #endif 123 124 #define CONFIG_SYS_MONITOR_LEN 0x20000 125 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 126 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 127 128 /* 129 * For booting Linux, the board info and command line data 130 * have to be in the first 8 MB of memory, since this is 131 * the maximum mapped by the Linux kernel during initialization ?? 132 */ 133 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 134 135 /* 136 * FLASH organization 137 */ 138 #ifdef CONFIG_SYS_FLASH_CFI 139 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 140 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 141 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 142 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 143 #endif 144 145 /*----------------------------------------------------------------------- 146 * Cache Configuration 147 */ 148 #define CONFIG_SYS_CACHELINE_SIZE 16 149 150 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 151 CONFIG_SYS_INIT_RAM_SIZE - 8) 152 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 153 CONFIG_SYS_INIT_RAM_SIZE - 4) 154 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 155 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 156 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 157 CF_ACR_EN | CF_ACR_SM_ALL) 158 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 159 CF_CACR_DISD | CF_CACR_INVI | \ 160 CF_CACR_CEIB | CF_CACR_DCM | \ 161 CF_CACR_EUSP) 162 163 /*----------------------------------------------------------------------- 164 * Memory bank definitions 165 */ 166 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 167 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 168 #define CONFIG_SYS_BR1_PRELIM 0 169 #define CONFIG_SYS_OR1_PRELIM 0 170 #define CONFIG_SYS_BR2_PRELIM 0x30000001 171 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000 172 #define CONFIG_SYS_BR3_PRELIM 0 173 #define CONFIG_SYS_OR3_PRELIM 0 174 #define CONFIG_SYS_BR4_PRELIM 0 175 #define CONFIG_SYS_OR4_PRELIM 0 176 #define CONFIG_SYS_BR5_PRELIM 0 177 #define CONFIG_SYS_OR5_PRELIM 0 178 #define CONFIG_SYS_BR6_PRELIM 0 179 #define CONFIG_SYS_OR6_PRELIM 0 180 #define CONFIG_SYS_BR7_PRELIM 0x00000701 181 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C 182 183 /*----------------------------------------------------------------------- 184 * Port configuration 185 */ 186 #define CONFIG_SYS_PACNT 0x00000000 187 #define CONFIG_SYS_PADDR 0x0000 188 #define CONFIG_SYS_PADAT 0x0000 189 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ 190 #define CONFIG_SYS_PBDDR 0x0000 191 #define CONFIG_SYS_PBDAT 0x0000 192 #define CONFIG_SYS_PDCNT 0x00000000 193 #endif /* _M5272C3_H */ 194