1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8536ds board configuration file 8 * 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_SDCARD 16 #define CONFIG_RAMBOOT_SDCARD 1 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 18 #endif 19 20 #ifdef CONFIG_SPIFLASH 21 #define CONFIG_RAMBOOT_SPIFLASH 1 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 23 #endif 24 25 #ifndef CONFIG_RESET_VECTOR_ADDRESS 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 27 #endif 28 29 #ifndef CONFIG_SYS_MONITOR_BASE 30 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 31 #endif 32 33 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 34 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 35 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 36 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 37 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 38 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 39 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 40 41 42 #define CONFIG_ENV_OVERWRITE 43 44 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 45 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 46 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 47 48 /* 49 * These can be toggled for performance analysis, otherwise use default. 50 */ 51 #define CONFIG_L2_CACHE /* toggle L2 cache */ 52 #define CONFIG_BTB /* toggle branch predition */ 53 54 #define CONFIG_ENABLE_36BIT_PHYS 1 55 56 #ifdef CONFIG_PHYS_64BIT 57 #define CONFIG_ADDR_MAP 1 58 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 59 #endif 60 61 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 62 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 63 64 /* 65 * Config the L2 Cache as L2 SRAM 66 */ 67 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 68 #ifdef CONFIG_PHYS_64BIT 69 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 70 #else 71 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 72 #endif 73 #define CONFIG_SYS_L2_SIZE (512 << 10) 74 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 75 76 #define CONFIG_SYS_CCSRBAR 0xffe00000 77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 78 79 #if defined(CONFIG_NAND_SPL) 80 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 81 #endif 82 83 /* DDR Setup */ 84 #define CONFIG_VERY_BIG_RAM 85 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 86 #define CONFIG_DDR_SPD 87 88 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 89 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 90 91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 93 94 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 95 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 96 97 /* I2C addresses of SPD EEPROMs */ 98 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 99 #define CONFIG_SYS_SPD_BUS_NUM 1 100 101 /* These are used when DDR doesn't use SPD. */ 102 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 103 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 104 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 105 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 106 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 107 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 108 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 109 #define CONFIG_SYS_DDR_MODE_1 0x00480432 110 #define CONFIG_SYS_DDR_MODE_2 0x00000000 111 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 112 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 113 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 114 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 115 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 116 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 117 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 118 119 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 120 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 121 #define CONFIG_SYS_DDR_SBE 0x00010000 122 123 /* Make sure required options are set */ 124 #ifndef CONFIG_SPD_EEPROM 125 #error ("CONFIG_SPD_EEPROM is required") 126 #endif 127 128 #undef CONFIG_CLOCKS_IN_MHZ 129 130 /* 131 * Memory map -- xxx -this is wrong, needs updating 132 * 133 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 134 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 135 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 136 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 137 * 138 * Localbus cacheable (TBD) 139 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 140 * 141 * Localbus non-cacheable 142 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 143 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 144 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 145 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 146 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 147 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 148 */ 149 150 /* 151 * Local Bus Definitions 152 */ 153 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 156 #else 157 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 158 #endif 159 160 #define CONFIG_FLASH_BR_PRELIM \ 161 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 162 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 163 164 #define CONFIG_SYS_BR1_PRELIM \ 165 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 166 | BR_PS_16 | BR_V) 167 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 168 169 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 170 CONFIG_SYS_FLASH_BASE_PHYS } 171 #define CONFIG_SYS_FLASH_QUIET_TEST 172 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 173 174 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 175 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 176 #undef CONFIG_SYS_FLASH_CHECKSUM 177 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 178 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 179 180 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 181 #define CONFIG_SYS_RAMBOOT 182 #else 183 #undef CONFIG_SYS_RAMBOOT 184 #endif 185 186 #define CONFIG_SYS_FLASH_EMPTY_INFO 187 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 188 189 #define CONFIG_HWCONFIG /* enable hwconfig */ 190 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 191 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 192 #ifdef CONFIG_PHYS_64BIT 193 #define PIXIS_BASE_PHYS 0xfffdf0000ull 194 #else 195 #define PIXIS_BASE_PHYS PIXIS_BASE 196 #endif 197 198 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 199 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 200 201 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 202 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 203 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 204 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 205 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 206 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 207 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 208 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 209 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 210 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 211 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 212 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 213 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 214 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 215 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 216 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 217 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 218 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 219 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 220 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 221 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 222 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 223 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 224 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 225 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 226 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 227 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 228 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 229 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 230 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 231 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 232 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 233 #define PIXIS_LED 0x25 /* LED Register */ 234 235 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 236 237 /* old pixis referenced names */ 238 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 239 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 240 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 241 242 #define CONFIG_SYS_INIT_RAM_LOCK 1 243 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 244 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 245 246 #define CONFIG_SYS_GBL_DATA_OFFSET \ 247 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 248 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 249 250 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 251 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 252 253 #ifndef CONFIG_NAND_SPL 254 #define CONFIG_SYS_NAND_BASE 0xffa00000 255 #ifdef CONFIG_PHYS_64BIT 256 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 257 #else 258 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 259 #endif 260 #else 261 #define CONFIG_SYS_NAND_BASE 0xfff00000 262 #ifdef CONFIG_PHYS_64BIT 263 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 264 #else 265 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 266 #endif 267 #endif 268 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 269 CONFIG_SYS_NAND_BASE + 0x40000, \ 270 CONFIG_SYS_NAND_BASE + 0x80000, \ 271 CONFIG_SYS_NAND_BASE + 0xC0000} 272 #define CONFIG_SYS_MAX_NAND_DEVICE 4 273 #define CONFIG_NAND_FSL_ELBC 1 274 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 275 276 /* NAND boot: 4K NAND loader config */ 277 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 278 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 279 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 280 #define CONFIG_SYS_NAND_U_BOOT_START \ 281 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 282 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 283 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 284 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 285 286 /* NAND flash config */ 287 #define CONFIG_SYS_NAND_BR_PRELIM \ 288 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 289 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 290 | BR_PS_8 /* Port Size = 8 bit */ \ 291 | BR_MS_FCM /* MSEL = FCM */ \ 292 | BR_V) /* valid */ 293 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 294 | OR_FCM_PGS /* Large Page*/ \ 295 | OR_FCM_CSCT \ 296 | OR_FCM_CST \ 297 | OR_FCM_CHT \ 298 | OR_FCM_SCY_1 \ 299 | OR_FCM_TRLX \ 300 | OR_FCM_EHTR) 301 302 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 303 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 304 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 305 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 306 307 #define CONFIG_SYS_BR4_PRELIM \ 308 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 309 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 310 | BR_PS_8 /* Port Size = 8 bit */ \ 311 | BR_MS_FCM /* MSEL = FCM */ \ 312 | BR_V) /* valid */ 313 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 314 #define CONFIG_SYS_BR5_PRELIM \ 315 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 316 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 317 | BR_PS_8 /* Port Size = 8 bit */ \ 318 | BR_MS_FCM /* MSEL = FCM */ \ 319 | BR_V) /* valid */ 320 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 321 322 #define CONFIG_SYS_BR6_PRELIM \ 323 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325 | BR_PS_8 /* Port Size = 8 bit */ \ 326 | BR_MS_FCM /* MSEL = FCM */ \ 327 | BR_V) /* valid */ 328 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 329 330 /* Serial Port - controlled on board with jumper J8 331 * open - index 2 332 * shorted - index 1 333 */ 334 #define CONFIG_SYS_NS16550_SERIAL 335 #define CONFIG_SYS_NS16550_REG_SIZE 1 336 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 337 #ifdef CONFIG_NAND_SPL 338 #define CONFIG_NS16550_MIN_FUNCTIONS 339 #endif 340 341 #define CONFIG_SYS_BAUDRATE_TABLE \ 342 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 343 344 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 345 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 346 347 /* 348 * I2C 349 */ 350 #define CONFIG_SYS_I2C 351 #define CONFIG_SYS_I2C_FSL 352 #define CONFIG_SYS_FSL_I2C_SPEED 400000 353 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 354 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 355 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 356 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 357 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 358 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 359 360 /* 361 * I2C2 EEPROM 362 */ 363 #define CONFIG_ID_EEPROM 364 #ifdef CONFIG_ID_EEPROM 365 #define CONFIG_SYS_I2C_EEPROM_NXID 366 #endif 367 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 368 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 369 #define CONFIG_SYS_EEPROM_BUS_NUM 1 370 371 /* 372 * General PCI 373 * Memory space is mapped 1-1, but I/O space must start from 0. 374 */ 375 376 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 377 #ifdef CONFIG_PHYS_64BIT 378 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 379 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 380 #else 381 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 382 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 383 #endif 384 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 385 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 386 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 387 #ifdef CONFIG_PHYS_64BIT 388 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 389 #else 390 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 391 #endif 392 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 393 394 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 395 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 396 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 397 #ifdef CONFIG_PHYS_64BIT 398 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 399 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 400 #else 401 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 402 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 403 #endif 404 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 405 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 406 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 407 #ifdef CONFIG_PHYS_64BIT 408 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 409 #else 410 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 411 #endif 412 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 413 414 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 415 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 416 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 420 #else 421 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 422 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 423 #endif 424 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 425 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 426 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 429 #else 430 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 431 #endif 432 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 433 434 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 435 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 436 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 439 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 440 #else 441 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 442 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 443 #endif 444 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 445 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 446 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 449 #else 450 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 451 #endif 452 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 453 454 #if defined(CONFIG_PCI) 455 /*PCIE video card used*/ 456 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 457 458 /*PCI video card used*/ 459 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 460 461 /* video */ 462 463 #if defined(CONFIG_VIDEO) 464 #define CONFIG_BIOSEMU 465 #define CONFIG_ATI_RADEON_FB 466 #define CONFIG_VIDEO_LOGO 467 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 468 #endif 469 470 #undef CONFIG_EEPRO100 471 #undef CONFIG_TULIP 472 473 #ifndef CONFIG_PCI_PNP 474 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 475 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 476 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 477 #endif 478 479 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 480 481 #endif /* CONFIG_PCI */ 482 483 /* SATA */ 484 #define CONFIG_SYS_SATA_MAX_DEVICE 2 485 #define CONFIG_SATA1 486 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 487 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 488 #define CONFIG_SATA2 489 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 490 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 491 492 #ifdef CONFIG_FSL_SATA 493 #define CONFIG_LBA48 494 #endif 495 496 #if defined(CONFIG_TSEC_ENET) 497 498 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 499 #define CONFIG_TSEC1 1 500 #define CONFIG_TSEC1_NAME "eTSEC1" 501 #define CONFIG_TSEC3 1 502 #define CONFIG_TSEC3_NAME "eTSEC3" 503 504 #define CONFIG_FSL_SGMII_RISER 1 505 #define SGMII_RISER_PHY_OFFSET 0x1c 506 507 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 508 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 509 510 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 511 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 512 513 #define TSEC1_PHYIDX 0 514 #define TSEC3_PHYIDX 0 515 516 #define CONFIG_ETHPRIME "eTSEC1" 517 518 #endif /* CONFIG_TSEC_ENET */ 519 520 /* 521 * Environment 522 */ 523 524 #if defined(CONFIG_SYS_RAMBOOT) 525 #if defined(CONFIG_RAMBOOT_SPIFLASH) 526 #elif defined(CONFIG_RAMBOOT_SDCARD) 527 #define CONFIG_FSL_FIXED_MMC_LOCATION 528 #define CONFIG_SYS_MMC_ENV_DEV 0 529 #endif 530 #endif 531 532 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 533 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 534 535 #undef CONFIG_WATCHDOG /* watchdog disabled */ 536 537 #ifdef CONFIG_MMC 538 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 539 #endif 540 541 /* 542 * USB 543 */ 544 #define CONFIG_HAS_FSL_MPH_USB 545 #ifdef CONFIG_HAS_FSL_MPH_USB 546 #ifdef CONFIG_USB_EHCI_HCD 547 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 548 #define CONFIG_USB_EHCI_FSL 549 #endif 550 #endif 551 552 /* 553 * Miscellaneous configurable options 554 */ 555 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 556 557 /* 558 * For booting Linux, the board info and command line data 559 * have to be in the first 64 MB of memory, since this is 560 * the maximum mapped by the Linux kernel during initialization. 561 */ 562 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 563 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 564 565 #if defined(CONFIG_CMD_KGDB) 566 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 567 #endif 568 569 /* 570 * Environment Configuration 571 */ 572 573 /* The mac addresses for all ethernet interface */ 574 #if defined(CONFIG_TSEC_ENET) 575 #define CONFIG_HAS_ETH0 576 #define CONFIG_HAS_ETH1 577 #define CONFIG_HAS_ETH2 578 #define CONFIG_HAS_ETH3 579 #endif 580 581 #define CONFIG_IPADDR 192.168.1.254 582 583 #define CONFIG_HOSTNAME "unknown" 584 #define CONFIG_ROOTPATH "/opt/nfsroot" 585 #define CONFIG_BOOTFILE "uImage" 586 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 587 588 #define CONFIG_SERVERIP 192.168.1.1 589 #define CONFIG_GATEWAYIP 192.168.1.1 590 #define CONFIG_NETMASK 255.255.255.0 591 592 /* default location for tftp and bootm */ 593 #define CONFIG_LOADADDR 1000000 594 595 #define CONFIG_EXTRA_ENV_SETTINGS \ 596 "netdev=eth0\0" \ 597 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 598 "tftpflash=tftpboot $loadaddr $uboot; " \ 599 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 600 " +$filesize; " \ 601 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 602 " +$filesize; " \ 603 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 604 " $filesize; " \ 605 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 606 " +$filesize; " \ 607 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 608 " $filesize\0" \ 609 "consoledev=ttyS0\0" \ 610 "ramdiskaddr=2000000\0" \ 611 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 612 "fdtaddr=1e00000\0" \ 613 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 614 "bdev=sda3\0" \ 615 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 616 617 #define CONFIG_HDBOOT \ 618 "setenv bootargs root=/dev/$bdev rw " \ 619 "console=$consoledev,$baudrate $othbootargs;" \ 620 "tftp $loadaddr $bootfile;" \ 621 "tftp $fdtaddr $fdtfile;" \ 622 "bootm $loadaddr - $fdtaddr" 623 624 #define CONFIG_NFSBOOTCOMMAND \ 625 "setenv bootargs root=/dev/nfs rw " \ 626 "nfsroot=$serverip:$rootpath " \ 627 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 628 "console=$consoledev,$baudrate $othbootargs;" \ 629 "tftp $loadaddr $bootfile;" \ 630 "tftp $fdtaddr $fdtfile;" \ 631 "bootm $loadaddr - $fdtaddr" 632 633 #define CONFIG_RAMBOOTCOMMAND \ 634 "setenv bootargs root=/dev/ram rw " \ 635 "console=$consoledev,$baudrate $othbootargs;" \ 636 "tftp $ramdiskaddr $ramdiskfile;" \ 637 "tftp $loadaddr $bootfile;" \ 638 "tftp $fdtaddr $fdtfile;" \ 639 "bootm $loadaddr $ramdiskaddr $fdtaddr" 640 641 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 642 643 #endif /* __CONFIG_H */ 644