1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * T104x RDB board configuration file 11 */ 12 #include <asm/config_mpc85xx.h> 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 16 #ifndef CONFIG_NXP_ESBC 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 18 #else 19 #define CONFIG_SYS_FSL_PBL_PBI \ 20 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 21 #endif 22 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_PAD_TO 0x40000 25 #define CONFIG_SPL_MAX_SIZE 0x28000 26 #ifdef CONFIG_SPL_BUILD 27 #define CONFIG_SPL_SKIP_RELOCATE 28 #define CONFIG_SPL_COMMON_INIT_DDR 29 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 30 #endif 31 #define RESET_VECTOR_OFFSET 0x27FFC 32 #define BOOT_PAGE_OFFSET 0x27000 33 34 #ifdef CONFIG_MTD_RAW_NAND 35 #ifdef CONFIG_NXP_ESBC 36 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 37 /* 38 * HDR would be appended at end of image and copied to DDR along 39 * with U-Boot image. 40 */ 41 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 42 CONFIG_U_BOOT_HDR_SIZE) 43 #else 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 45 #endif 46 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 47 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 49 #ifdef CONFIG_TARGET_T1040RDB 50 #define CONFIG_SYS_FSL_PBL_RCW \ 51 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 52 #endif 53 #ifdef CONFIG_TARGET_T1042RDB_PI 54 #define CONFIG_SYS_FSL_PBL_RCW \ 55 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 56 #endif 57 #ifdef CONFIG_TARGET_T1042RDB 58 #define CONFIG_SYS_FSL_PBL_RCW \ 59 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 60 #endif 61 #ifdef CONFIG_TARGET_T1040D4RDB 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 64 #endif 65 #ifdef CONFIG_TARGET_T1042D4RDB 66 #define CONFIG_SYS_FSL_PBL_RCW \ 67 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 68 #endif 69 #endif 70 71 #ifdef CONFIG_SPIFLASH 72 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 73 #define CONFIG_SPL_SPI_FLASH_MINIMAL 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 78 #ifndef CONFIG_SPL_BUILD 79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 80 #endif 81 #ifdef CONFIG_TARGET_T1040RDB 82 #define CONFIG_SYS_FSL_PBL_RCW \ 83 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 84 #endif 85 #ifdef CONFIG_TARGET_T1042RDB_PI 86 #define CONFIG_SYS_FSL_PBL_RCW \ 87 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 88 #endif 89 #ifdef CONFIG_TARGET_T1042RDB 90 #define CONFIG_SYS_FSL_PBL_RCW \ 91 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 92 #endif 93 #ifdef CONFIG_TARGET_T1040D4RDB 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_TARGET_T1042D4RDB 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 100 #endif 101 #endif 102 103 #ifdef CONFIG_SDCARD 104 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 105 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 106 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 107 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 108 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 109 #ifndef CONFIG_SPL_BUILD 110 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 111 #endif 112 #ifdef CONFIG_TARGET_T1040RDB 113 #define CONFIG_SYS_FSL_PBL_RCW \ 114 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 115 #endif 116 #ifdef CONFIG_TARGET_T1042RDB_PI 117 #define CONFIG_SYS_FSL_PBL_RCW \ 118 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 119 #endif 120 #ifdef CONFIG_TARGET_T1042RDB 121 #define CONFIG_SYS_FSL_PBL_RCW \ 122 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 123 #endif 124 #ifdef CONFIG_TARGET_T1040D4RDB 125 #define CONFIG_SYS_FSL_PBL_RCW \ 126 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 127 #endif 128 #ifdef CONFIG_TARGET_T1042D4RDB 129 #define CONFIG_SYS_FSL_PBL_RCW \ 130 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 131 #endif 132 #endif 133 134 #endif 135 136 /* High Level Configuration Options */ 137 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 138 139 /* support deep sleep */ 140 #define CONFIG_DEEP_SLEEP 141 142 #ifndef CONFIG_RESET_VECTOR_ADDRESS 143 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 144 #endif 145 146 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 147 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 148 #define CONFIG_PCIE1 /* PCIE controller 1 */ 149 #define CONFIG_PCIE2 /* PCIE controller 2 */ 150 #define CONFIG_PCIE3 /* PCIE controller 3 */ 151 #define CONFIG_PCIE4 /* PCIE controller 4 */ 152 153 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 154 155 #define CONFIG_ENV_OVERWRITE 156 157 #if defined(CONFIG_SPIFLASH) 158 #elif defined(CONFIG_SDCARD) 159 #define CONFIG_SYS_MMC_ENV_DEV 0 160 #elif defined(CONFIG_MTD_RAW_NAND) 161 #ifdef CONFIG_NXP_ESBC 162 #define CONFIG_RAMBOOT_NAND 163 #define CONFIG_BOOTSCRIPT_COPY_RAM 164 #endif 165 #endif 166 167 #define CONFIG_SYS_CLK_FREQ 100000000 168 #define CONFIG_DDR_CLK_FREQ 66666666 169 170 /* 171 * These can be toggled for performance analysis, otherwise use default. 172 */ 173 #define CONFIG_SYS_CACHE_STASHING 174 #define CONFIG_BACKSIDE_L2_CACHE 175 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 176 #define CONFIG_BTB /* toggle branch predition */ 177 #define CONFIG_DDR_ECC 178 #ifdef CONFIG_DDR_ECC 179 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 180 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 181 #endif 182 183 #define CONFIG_ENABLE_36BIT_PHYS 184 185 #define CONFIG_ADDR_MAP 186 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 187 188 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 189 #define CONFIG_SYS_MEMTEST_END 0x00400000 190 191 /* 192 * Config the L3 Cache as L3 SRAM 193 */ 194 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 195 /* 196 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 197 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 198 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 199 */ 200 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 201 #define CONFIG_SYS_L3_SIZE 256 << 10 202 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 203 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 204 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 205 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 206 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 207 208 #define CONFIG_SYS_DCSRBAR 0xf0000000 209 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 210 211 /* 212 * DDR Setup 213 */ 214 #define CONFIG_VERY_BIG_RAM 215 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 216 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 217 218 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 219 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 220 221 #define CONFIG_DDR_SPD 222 223 #define CONFIG_SYS_SPD_BUS_NUM 0 224 #define SPD_EEPROM_ADDRESS 0x51 225 226 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 227 228 /* 229 * IFC Definitions 230 */ 231 #define CONFIG_SYS_FLASH_BASE 0xe8000000 232 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 233 234 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 235 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 236 CSPR_PORT_SIZE_16 | \ 237 CSPR_MSEL_NOR | \ 238 CSPR_V) 239 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 240 241 /* 242 * TDM Definition 243 */ 244 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 245 246 /* NOR Flash Timing Params */ 247 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 248 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 249 FTIM0_NOR_TEADC(0x5) | \ 250 FTIM0_NOR_TEAHC(0x5)) 251 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 252 FTIM1_NOR_TRAD_NOR(0x1A) |\ 253 FTIM1_NOR_TSEQRAD_NOR(0x13)) 254 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 255 FTIM2_NOR_TCH(0x4) | \ 256 FTIM2_NOR_TWPH(0x0E) | \ 257 FTIM2_NOR_TWP(0x1c)) 258 #define CONFIG_SYS_NOR_FTIM3 0x0 259 260 #define CONFIG_SYS_FLASH_QUIET_TEST 261 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 262 263 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 264 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 265 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 267 268 #define CONFIG_SYS_FLASH_EMPTY_INFO 269 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 270 271 /* CPLD on IFC */ 272 #define CPLD_LBMAP_MASK 0x3F 273 #define CPLD_BANK_SEL_MASK 0x07 274 #define CPLD_BANK_OVERRIDE 0x40 275 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 276 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 277 #define CPLD_LBMAP_RESET 0xFF 278 #define CPLD_LBMAP_SHIFT 0x03 279 280 #if defined(CONFIG_TARGET_T1042RDB_PI) 281 #define CPLD_DIU_SEL_DFP 0x80 282 #elif defined(CONFIG_TARGET_T1042D4RDB) 283 #define CPLD_DIU_SEL_DFP 0xc0 284 #endif 285 286 #if defined(CONFIG_TARGET_T1040D4RDB) 287 #define CPLD_INT_MASK_ALL 0xFF 288 #define CPLD_INT_MASK_THERM 0x80 289 #define CPLD_INT_MASK_DVI_DFP 0x40 290 #define CPLD_INT_MASK_QSGMII1 0x20 291 #define CPLD_INT_MASK_QSGMII2 0x10 292 #define CPLD_INT_MASK_SGMI1 0x08 293 #define CPLD_INT_MASK_SGMI2 0x04 294 #define CPLD_INT_MASK_TDMR1 0x02 295 #define CPLD_INT_MASK_TDMR2 0x01 296 #endif 297 298 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 299 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 300 #define CONFIG_SYS_CSPR2_EXT (0xf) 301 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 302 | CSPR_PORT_SIZE_8 \ 303 | CSPR_MSEL_GPCM \ 304 | CSPR_V) 305 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 306 #define CONFIG_SYS_CSOR2 0x0 307 /* CPLD Timing parameters for IFC CS2 */ 308 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 309 FTIM0_GPCM_TEADC(0x0e) | \ 310 FTIM0_GPCM_TEAHC(0x0e)) 311 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 312 FTIM1_GPCM_TRAD(0x1f)) 313 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 314 FTIM2_GPCM_TCH(0x8) | \ 315 FTIM2_GPCM_TWP(0x1f)) 316 #define CONFIG_SYS_CS2_FTIM3 0x0 317 318 /* NAND Flash on IFC */ 319 #define CONFIG_NAND_FSL_IFC 320 #define CONFIG_SYS_NAND_BASE 0xff800000 321 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 322 323 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 324 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 325 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 326 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 327 | CSPR_V) 328 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 329 330 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 331 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 332 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 333 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 334 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 335 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 336 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 337 338 #define CONFIG_SYS_NAND_ONFI_DETECTION 339 340 /* ONFI NAND Flash mode0 Timing Params */ 341 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 342 FTIM0_NAND_TWP(0x18) | \ 343 FTIM0_NAND_TWCHT(0x07) | \ 344 FTIM0_NAND_TWH(0x0a)) 345 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 346 FTIM1_NAND_TWBE(0x39) | \ 347 FTIM1_NAND_TRR(0x0e) | \ 348 FTIM1_NAND_TRP(0x18)) 349 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 350 FTIM2_NAND_TREH(0x0a) | \ 351 FTIM2_NAND_TWHRE(0x1e)) 352 #define CONFIG_SYS_NAND_FTIM3 0x0 353 354 #define CONFIG_SYS_NAND_DDR_LAW 11 355 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 356 #define CONFIG_SYS_MAX_NAND_DEVICE 1 357 358 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 359 360 #if defined(CONFIG_MTD_RAW_NAND) 361 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 362 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 363 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 364 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 365 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 366 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 367 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 368 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 369 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 370 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 371 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 372 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 373 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 374 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 375 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 376 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 377 #else 378 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 379 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 380 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 381 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 382 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 383 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 384 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 385 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 386 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 387 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 388 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 389 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 390 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 391 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 392 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 393 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 394 #endif 395 396 #ifdef CONFIG_SPL_BUILD 397 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 398 #else 399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 400 #endif 401 402 #if defined(CONFIG_RAMBOOT_PBL) 403 #define CONFIG_SYS_RAMBOOT 404 #endif 405 406 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 407 #if defined(CONFIG_MTD_RAW_NAND) 408 #define CONFIG_A008044_WORKAROUND 409 #endif 410 #endif 411 412 #define CONFIG_HWCONFIG 413 414 /* define to use L1 as initial stack */ 415 #define CONFIG_L1_INIT_RAM 416 #define CONFIG_SYS_INIT_RAM_LOCK 417 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 420 /* The assembler doesn't like typecast */ 421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 422 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 423 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 424 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 425 426 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 427 GENERATED_GBL_DATA_SIZE) 428 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 429 430 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 431 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 432 433 /* Serial Port - controlled on board with jumper J8 434 * open - index 2 435 * shorted - index 1 436 */ 437 #define CONFIG_SYS_NS16550_SERIAL 438 #define CONFIG_SYS_NS16550_REG_SIZE 1 439 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 440 441 #define CONFIG_SYS_BAUDRATE_TABLE \ 442 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 443 444 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 445 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 446 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 447 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 448 449 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 450 /* Video */ 451 #define CONFIG_FSL_DIU_FB 452 453 #ifdef CONFIG_FSL_DIU_FB 454 #define CONFIG_FSL_DIU_CH7301 455 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 456 #define CONFIG_VIDEO_LOGO 457 #define CONFIG_VIDEO_BMP_LOGO 458 #endif 459 #endif 460 461 /* I2C */ 462 #define CONFIG_SYS_I2C 463 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 464 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 465 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 466 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 467 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 468 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 469 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 470 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 471 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 472 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 473 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 474 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 475 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 476 477 /* I2C bus multiplexer */ 478 #define I2C_MUX_PCA_ADDR 0x70 479 #define I2C_MUX_CH_DEFAULT 0x8 480 481 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 482 defined(CONFIG_TARGET_T1040D4RDB) || \ 483 defined(CONFIG_TARGET_T1042D4RDB) 484 /* LDI/DVI Encoder for display */ 485 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 486 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 487 488 /* 489 * RTC configuration 490 */ 491 #define RTC 492 #define CONFIG_RTC_DS1337 1 493 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 494 495 /*DVI encoder*/ 496 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 497 #endif 498 499 /* 500 * eSPI - Enhanced SPI 501 */ 502 503 /* 504 * General PCI 505 * Memory space is mapped 1-1, but I/O space must start from 0. 506 */ 507 508 #ifdef CONFIG_PCI 509 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 510 #ifdef CONFIG_PCIE1 511 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 512 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 513 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 514 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 515 #endif 516 517 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 518 #ifdef CONFIG_PCIE2 519 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 520 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 521 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 522 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 523 #endif 524 525 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 526 #ifdef CONFIG_PCIE3 527 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 528 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 529 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 530 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 531 #endif 532 533 /* controller 4, Base address 203000 */ 534 #ifdef CONFIG_PCIE4 535 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 536 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 537 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 538 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 539 #endif 540 541 #if !defined(CONFIG_DM_PCI) 542 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 543 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 544 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 545 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 546 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 547 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 548 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 549 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 550 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 551 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 552 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 553 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 554 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 555 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 556 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 557 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 558 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 559 #define CONFIG_PCI_INDIRECT_BRIDGE 560 #endif 561 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 562 #endif /* CONFIG_PCI */ 563 564 /* SATA */ 565 #define CONFIG_FSL_SATA_V2 566 #ifdef CONFIG_FSL_SATA_V2 567 #define CONFIG_SYS_SATA_MAX_DEVICE 1 568 #define CONFIG_SATA1 569 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 570 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 571 572 #define CONFIG_LBA48 573 #endif 574 575 /* 576 * USB 577 */ 578 #define CONFIG_HAS_FSL_DR_USB 579 580 #ifdef CONFIG_HAS_FSL_DR_USB 581 #ifdef CONFIG_USB_EHCI_HCD 582 #define CONFIG_USB_EHCI_FSL 583 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 584 #endif 585 #endif 586 587 #ifdef CONFIG_MMC 588 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 589 #endif 590 591 /* Qman/Bman */ 592 #ifndef CONFIG_NOBQFMAN 593 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 594 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 595 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 596 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 597 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 598 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 599 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 600 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 601 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 602 CONFIG_SYS_BMAN_CENA_SIZE) 603 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 604 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 605 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 606 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 607 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 608 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 609 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 610 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 611 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 612 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 613 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 614 CONFIG_SYS_QMAN_CENA_SIZE) 615 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 616 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 617 618 #define CONFIG_SYS_DPAA_FMAN 619 #define CONFIG_SYS_DPAA_PME 620 621 #define CONFIG_U_QE 622 623 /* Default address of microcode for the Linux Fman driver */ 624 #if defined(CONFIG_SPIFLASH) 625 /* 626 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 627 * env, so we got 0x110000. 628 */ 629 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 630 #elif defined(CONFIG_SDCARD) 631 /* 632 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 633 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 634 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 635 */ 636 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 637 #elif defined(CONFIG_MTD_RAW_NAND) 638 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 639 #else 640 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 641 #endif 642 643 #if defined(CONFIG_SPIFLASH) 644 #define CONFIG_SYS_QE_FW_ADDR 0x130000 645 #elif defined(CONFIG_SDCARD) 646 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 647 #elif defined(CONFIG_MTD_RAW_NAND) 648 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 649 #else 650 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 651 #endif 652 653 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 654 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 655 #endif /* CONFIG_NOBQFMAN */ 656 657 #ifdef CONFIG_SYS_DPAA_FMAN 658 #define CONFIG_PHY_VITESSE 659 #define CONFIG_PHY_REALTEK 660 #endif 661 662 #ifdef CONFIG_FMAN_ENET 663 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 664 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 665 #elif defined(CONFIG_TARGET_T1040D4RDB) 666 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 667 #elif defined(CONFIG_TARGET_T1042D4RDB) 668 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 669 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 670 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 671 #endif 672 673 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 674 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 675 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 676 #else 677 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 678 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 679 #endif 680 681 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 682 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 683 #define CONFIG_VSC9953 684 #ifdef CONFIG_TARGET_T1040RDB 685 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 686 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 687 #else 688 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 689 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 690 #endif 691 #endif 692 693 #define CONFIG_ETHPRIME "FM1@DTSEC4" 694 #endif 695 696 /* 697 * Environment 698 */ 699 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 700 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 701 702 /* 703 * Miscellaneous configurable options 704 */ 705 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 706 707 /* 708 * For booting Linux, the board info and command line data 709 * have to be in the first 64 MB of memory, since this is 710 * the maximum mapped by the Linux kernel during initialization. 711 */ 712 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 713 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 714 715 #ifdef CONFIG_CMD_KGDB 716 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 717 #endif 718 719 /* 720 * Dynamic MTD Partition support with mtdparts 721 */ 722 723 /* 724 * Environment Configuration 725 */ 726 #define CONFIG_ROOTPATH "/opt/nfsroot" 727 #define CONFIG_BOOTFILE "uImage" 728 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 729 730 /* default location for tftp and bootm */ 731 #define CONFIG_LOADADDR 1000000 732 733 #define __USB_PHY_TYPE utmi 734 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 735 736 #ifdef CONFIG_TARGET_T1040RDB 737 #define FDTFILE "t1040rdb/t1040rdb.dtb" 738 #elif defined(CONFIG_TARGET_T1042RDB_PI) 739 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 740 #elif defined(CONFIG_TARGET_T1042RDB) 741 #define FDTFILE "t1042rdb/t1042rdb.dtb" 742 #elif defined(CONFIG_TARGET_T1040D4RDB) 743 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 744 #elif defined(CONFIG_TARGET_T1042D4RDB) 745 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 746 #endif 747 748 #ifdef CONFIG_FSL_DIU_FB 749 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 750 #else 751 #define DIU_ENVIRONMENT 752 #endif 753 754 #define CONFIG_EXTRA_ENV_SETTINGS \ 755 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 756 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 757 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 758 "netdev=eth0\0" \ 759 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 760 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 761 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 762 "tftpflash=tftpboot $loadaddr $uboot && " \ 763 "protect off $ubootaddr +$filesize && " \ 764 "erase $ubootaddr +$filesize && " \ 765 "cp.b $loadaddr $ubootaddr $filesize && " \ 766 "protect on $ubootaddr +$filesize && " \ 767 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 768 "consoledev=ttyS0\0" \ 769 "ramdiskaddr=2000000\0" \ 770 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 771 "fdtaddr=1e00000\0" \ 772 "fdtfile=" __stringify(FDTFILE) "\0" \ 773 "bdev=sda3\0" 774 775 #define CONFIG_LINUX \ 776 "setenv bootargs root=/dev/ram rw " \ 777 "console=$consoledev,$baudrate $othbootargs;" \ 778 "setenv ramdiskaddr 0x02000000;" \ 779 "setenv fdtaddr 0x00c00000;" \ 780 "setenv loadaddr 0x1000000;" \ 781 "bootm $loadaddr $ramdiskaddr $fdtaddr" 782 783 #define CONFIG_HDBOOT \ 784 "setenv bootargs root=/dev/$bdev rw " \ 785 "console=$consoledev,$baudrate $othbootargs;" \ 786 "tftp $loadaddr $bootfile;" \ 787 "tftp $fdtaddr $fdtfile;" \ 788 "bootm $loadaddr - $fdtaddr" 789 790 #define CONFIG_NFSBOOTCOMMAND \ 791 "setenv bootargs root=/dev/nfs rw " \ 792 "nfsroot=$serverip:$rootpath " \ 793 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 794 "console=$consoledev,$baudrate $othbootargs;" \ 795 "tftp $loadaddr $bootfile;" \ 796 "tftp $fdtaddr $fdtfile;" \ 797 "bootm $loadaddr - $fdtaddr" 798 799 #define CONFIG_RAMBOOTCOMMAND \ 800 "setenv bootargs root=/dev/ram rw " \ 801 "console=$consoledev,$baudrate $othbootargs;" \ 802 "tftp $ramdiskaddr $ramdiskfile;" \ 803 "tftp $loadaddr $bootfile;" \ 804 "tftp $fdtaddr $fdtfile;" \ 805 "bootm $loadaddr $ramdiskaddr $fdtaddr" 806 807 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 808 809 #include <asm/fsl_secure_boot.h> 810 811 #endif /* __CONFIG_H */ 812