1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2005 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 /* 8 * TQM8349 board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_E300 1 /* E300 Family */ 18 19 /* board pre init: do not call, nothing to do */ 20 21 /* detect the number of flash banks */ 22 23 /* 24 * DDR Setup 25 */ 26 /* DDR is system memory*/ 27 #define CONFIG_SYS_SDRAM_BASE 0x00000000 28 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ 29 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 30 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ 31 32 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 33 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 34 #define CONFIG_SYS_MEMTEST_END 0x00100000 35 36 /* 37 * FLASH on the Local Bus 38 */ 39 #undef CONFIG_SYS_FLASH_CHECKSUM 40 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ 41 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ 42 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ 43 44 /* 45 * FLASH bank number detection 46 */ 47 48 /* 49 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of 50 * Flash banks has to be determined at runtime and stored in a gloabl variable 51 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is 52 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array 53 * flash_info, and should be made sufficiently large to accomodate the number 54 * of banks that might actually be detected. Since most (all?) Flash related 55 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on 56 * the board, it is defined as tqm834x_num_flash_banks. 57 */ 58 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 59 60 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ 61 62 63 /* disable remaining mappings */ 64 #define CONFIG_SYS_BR1_PRELIM 0x00000000 65 #define CONFIG_SYS_OR1_PRELIM 0x00000000 66 67 #define CONFIG_SYS_BR2_PRELIM 0x00000000 68 #define CONFIG_SYS_OR2_PRELIM 0x00000000 69 70 #define CONFIG_SYS_BR3_PRELIM 0x00000000 71 #define CONFIG_SYS_OR3_PRELIM 0x00000000 72 73 /* 74 * Monitor config 75 */ 76 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 77 78 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 79 # define CONFIG_SYS_RAMBOOT 80 #else 81 # undef CONFIG_SYS_RAMBOOT 82 #endif 83 84 #define CONFIG_SYS_INIT_RAM_LOCK 1 85 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ 86 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 87 88 #define CONFIG_SYS_GBL_DATA_OFFSET \ 89 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 90 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 91 92 /* Reserve 384 kB = 3 sect. for Mon */ 93 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 94 /* Reserve 512 kB for malloc */ 95 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 96 97 /* 98 * Serial Port 99 */ 100 #define CONFIG_SYS_NS16550_SERIAL 101 #define CONFIG_SYS_NS16550_REG_SIZE 1 102 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 103 104 #define CONFIG_SYS_BAUDRATE_TABLE \ 105 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 106 107 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 108 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 109 110 /* 111 * I2C 112 */ 113 #define CONFIG_SYS_I2C 114 #define CONFIG_SYS_I2C_FSL 115 #define CONFIG_SYS_FSL_I2C_SPEED 400000 116 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 117 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 118 119 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ 120 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 121 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ 122 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ 123 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ 124 125 /* I2C RTC */ 126 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ 127 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 128 129 /* 130 * TSEC 131 */ 132 133 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 134 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 135 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 136 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 137 138 #if defined(CONFIG_TSEC_ENET) 139 140 #define CONFIG_TSEC1 1 141 #define CONFIG_TSEC1_NAME "TSEC0" 142 #define CONFIG_TSEC2 1 143 #define CONFIG_TSEC2_NAME "TSEC1" 144 #define TSEC1_PHY_ADDR 2 145 #define TSEC2_PHY_ADDR 1 146 #define TSEC1_PHYIDX 0 147 #define TSEC2_PHYIDX 0 148 #define TSEC1_FLAGS TSEC_GIGABIT 149 #define TSEC2_FLAGS TSEC_GIGABIT 150 151 /* Options are: TSEC[0-1] */ 152 #define CONFIG_ETHPRIME "TSEC0" 153 154 #endif /* CONFIG_TSEC_ENET */ 155 156 #if defined(CONFIG_PCI) 157 158 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 159 160 /* PCI1 host bridge */ 161 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 162 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 163 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 164 #define CONFIG_SYS_PCI1_MMIO_BASE \ 165 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 166 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 167 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 168 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 169 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 170 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ 171 172 #undef CONFIG_EEPRO100 173 #define CONFIG_EEPRO100 174 #undef CONFIG_TULIP 175 176 #if !defined(CONFIG_PCI_PNP) 177 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE 178 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE 179 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ 180 #endif 181 182 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 183 184 #endif /* CONFIG_PCI */ 185 186 /* 187 * Environment 188 */ 189 190 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 191 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 192 193 /* 194 * BOOTP options 195 */ 196 #define CONFIG_BOOTP_BOOTFILESIZE 197 198 /* 199 * Miscellaneous configurable options 200 */ 201 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 202 203 #undef CONFIG_WATCHDOG /* watchdog disabled */ 204 205 /* 206 * For booting Linux, the board info and command line data 207 * have to be in the first 256 MB of memory, since this is 208 * the maximum mapped by the Linux kernel during initialization. 209 */ 210 /* Initial Memory map for Linux */ 211 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 212 213 /* System IO Config */ 214 #define CONFIG_SYS_SICRH 0 215 #define CONFIG_SYS_SICRL SICRL_LDP_A 216 217 /* PCI */ 218 #ifdef CONFIG_PCI 219 #define CONFIG_PCI_INDIRECT_BRIDGE 220 #endif 221 222 #if defined(CONFIG_CMD_KGDB) 223 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 224 #endif 225 226 /* 227 * Environment Configuration 228 */ 229 230 /* default location for tftp and bootm */ 231 #define CONFIG_LOADADDR 400000 232 233 #define CONFIG_EXTRA_ENV_SETTINGS \ 234 "netdev=eth0\0" \ 235 "hostname=tqm834x\0" \ 236 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 237 "nfsroot=${serverip}:${rootpath}\0" \ 238 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 239 "addip=setenv bootargs ${bootargs} " \ 240 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 241 ":${hostname}:${netdev}:off panic=1\0" \ 242 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ 243 "flash_nfs_old=run nfsargs addip addcons;" \ 244 "bootm ${kernel_addr}\0" \ 245 "flash_nfs=run nfsargs addip addcons;" \ 246 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 247 "flash_self_old=run ramargs addip addcons;" \ 248 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 249 "flash_self=run ramargs addip addcons;" \ 250 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 251 "net_nfs_old=tftp 400000 ${bootfile};" \ 252 "run nfsargs addip addcons;bootm\0" \ 253 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 254 "tftp ${fdt_addr_r} ${fdt_file}; " \ 255 "run nfsargs addip addcons; " \ 256 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 257 "rootpath=/opt/eldk/ppc_6xx\0" \ 258 "bootfile=tqm834x/uImage\0" \ 259 "fdtfile=tqm834x/tqm834x.dtb\0" \ 260 "kernel_addr_r=400000\0" \ 261 "fdt_addr_r=600000\0" \ 262 "ramdisk_addr_r=800000\0" \ 263 "kernel_addr=800C0000\0" \ 264 "fdt_addr=800A0000\0" \ 265 "ramdisk_addr=80300000\0" \ 266 "u-boot=tqm834x/u-boot.bin\0" \ 267 "load=tftp 200000 ${u-boot}\0" \ 268 "update=protect off 80000000 +${filesize};" \ 269 "era 80000000 +${filesize};" \ 270 "cp.b 200000 80000000 ${filesize}\0" \ 271 "upd=run load update\0" \ 272 "" 273 274 #define CONFIG_BOOTCOMMAND "run flash_self" 275 276 /* 277 * JFFS2 partitions 278 */ 279 /* mtdparts command line support */ 280 281 /* default mtd partition table */ 282 #endif /* __CONFIG_H */ 283