1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #ifndef __HI3520DV500_H 20 #define __HI3520DV500_H 21 22 #include <linux/sizes.h> 23 #include <asm/arch/platform.h> 24 25 #define CONFIG_SUPPORT_RAW_INITRD 26 27 #define CONFIG_BOARD_EARLY_INIT_F 28 29 /* Physical Memory Map */ 30 31 /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ 32 #define CONFIG_SYS_TEXT_BASE 0x40800000 33 #define CONFIG_SYS_TEXT_BASE_ORI 0x40700000 34 35 36 #define PHYS_SDRAM_1 0x40000000 37 #define PHYS_SDRAM_1_SIZE 0x20000000 38 39 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 40 41 #define CONFIG_SYS_INIT_SP_ADDR 0x0401A000 42 43 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) 44 #define CONFIG_SYS_GBL_DATA_SIZE 128 45 46 /* Generic Timer Definitions */ 47 #define COUNTER_FREQUENCY 0x1800000 48 49 #define CONFIG_SYS_TIMER_RATE CFG_TIMER_CLK 50 #define CONFIG_SYS_TIMER_COUNTER (CFG_TIMERBASE + REG_TIMER_VALUE) 51 #define CONFIG_SYS_TIMER_COUNTS_DOWN 52 53 /* Size of malloc() pool */ 54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 55 56 /* PL011 Serial Configuration */ 57 #define CONFIG_PL011_CLOCK 24000000 58 59 #define CONFIG_PL01x_PORTS \ 60 {(void *)UART0_REG_BASE, (void *)UART1_REG_BASE, \ 61 (void *)UART2_REG_BASE} 62 63 #define CONFIG_CUR_UART_BASE UART0_REG_BASE 64 65 #define CONFIG_64BIT 66 67 /*Network configuration*/ 68 /*----------------------------------------------------------------------- 69 * HIETH driver 70 -----------------------------------------------------------------------*/ 71 /* default is hieth-switch-fabric */ 72 #ifdef CONFIG_HISFV300_ETH 73 #define INNER_PHY 74 #define HISFV_MII_MODE 0 75 #define HISFV_RMII_MODE 1 76 #define HIETH_MII_RMII_MODE_U HISFV_MII_MODE 77 #define HIETH_MII_RMII_MODE_D HISFV_MII_MODE 78 #define HISFV_PHY_U 0 79 #define HISFV_PHY_D 2 80 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 81 #endif /* CONFIG_HISFV300_ETH */ 82 83 #define CONFIG_PHY_GIGE 84 #ifdef CONFIG_HIGMACV300_ETH 85 #define CONFIG_GMAC_NUMS 1 86 #define CONFIG_HIGMAC_PHY0_ADDR 1 87 #define CONFIG_HIGMAC_PHY0_INTERFACE_MODE 0 /* rgmii 2, rmii 1, mii 0 */ 88 #define CONFIG_HIGMAC_PHY1_ADDR 3 89 #define CONFIG_HIGMAC_PHY1_INTERFACE_MODE 0 /* rgmii 2, rmii 1, mii 0 */ 90 #define CONFIG_HIGMAC_DESC_4_WORD 91 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 92 #endif 93 94 /* Flash Memory Configuration v100 */ 95 #ifdef CONFIG_HIFMC 96 #define CONFIG_HIFMC_REG_BASE FMC_REG_BASE 97 #define CONFIG_HIFMC_BUFFER_BASE FMC_MEM_BASE 98 #define CONFIG_HIFMC_MAX_CS_NUM 2 99 #endif 100 101 #ifdef CONFIG_HIFMC_SPI_NOR 102 #define CONFIG_CMD_SF 103 #define CONFIG_SPI_NOR_MAX_CHIP_NUM 1 104 #define CONFIG_SPI_NOR_QUIET_TEST 105 #endif 106 107 #ifdef CONFIG_HIFMC_SPI_NAND 108 #define CONFIG_CMD_NAND 109 #define CONFIG_SPI_NAND_MAX_CHIP_NUM 1 110 #define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_SPI_NAND_MAX_CHIP_NUM 111 #define CONFIG_SYS_NAND_MAX_CHIPS CONFIG_SPI_NAND_MAX_CHIP_NUM 112 #define CONFIG_SYS_NAND_BASE FMC_MEM_BASE 113 #endif 114 115 #ifdef CONFIG_HIFMC_NAND 116 /* base on needs #define CONFIG_NAND_EDO_MODE */ 117 #define CONFIG_CMD_NAND 118 #define CONFIG_NAND_MAX_CHIP_NUM 1 119 #define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_NAND_MAX_CHIP_NUM 120 #define CONFIG_SYS_NAND_MAX_CHIPS CONFIG_NAND_MAX_CHIP_NUM 121 #define CONFIG_SYS_NAND_BASE FMC_MEM_BASE 122 #endif 123 124 /* the flag for auto update. 1:enable; 0:disable */ 125 #define CONFIG_AUTO_UPDATE 0 126 127 #if (CONFIG_AUTO_UPDATE == 1) 128 #define CONFIG_AUTO_UPDATE_ADAPTATION 1 129 #define CONFIG_AUTO_USB_UPDATE 1 130 #define CONFIG_FS_FAT 1 131 #define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536 132 #endif 133 134 /* SD/MMC configuration */ 135 #ifdef CONFIG_MMC 136 /*#define CONFIG_MMC_SDMA*/ 137 #define CONFIG_EMMC 138 #define CONFIG_SUPPORT_EMMC_BOOT 139 #define CONFIG_GENERIC_MMC 140 #define CONFIG_CMD_MMC 141 #define CONFIG_SYS_MMC_ENV_DEV 0 142 #define CONFIG_EXT4_SPARSE 143 #define CONFIG_SDHCI 144 #define CONFIG_HISI_SDHCI 145 #define CONFIG_HISI_SDHCI_MAX_FREQ 148500000 146 #define CONFIG_FS_EXT4 147 #define CONFIG_SDHCI_ADMA 148 #define CONFIG_SUPPORT_EMMC_RPMB 149 #endif 150 151 #define CONFIG_MISC_INIT_R 152 153 /* Command line configuration */ 154 #define CONFIG_MENU 155 /*#define CONFIG_CMD_UNZIP*/ 156 #define CONFIG_CMD_ENV 157 158 #define CONFIG_MTD_PARTITIONS 159 160 /* BOOTP options */ 161 #define CONFIG_BOOTP_BOOTFILESIZE 162 163 /* Initial environment variables */ 164 165 /* 166 * Defines where the kernel and FDT will be put in RAM 167 */ 168 169 /* Assume we boot with root on the seventh partition of eMMC */ 170 #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/mtdblock2 rw" 171 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3 172 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 173 #define BOOT_TARGET_DEVICES(func) \ 174 func(USB, usb, 0) \ 175 func(MMC, mmc, 1) \ 176 func(DHCP, dhcp, na) 177 #include <config_distro_bootcmd.h> 178 179 /*allow change env*/ 180 #define CONFIG_ENV_OVERWRITE 181 182 #define CONFIG_COMMAND_HISTORY 183 184 /* env in flash instead of CFG_ENV_IS_NOWHERE */ 185 #define CONFIG_ENV_VARS_UBOOT_CONFIG 186 187 /* kernel parameter list phy addr */ 188 #define CFG_BOOT_PARAMS (CONFIG_SYS_SDRAM_BASE + 0x0100) 189 190 /* Monitor Command Prompt */ 191 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 192 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 193 sizeof(CONFIG_SYS_PROMPT) + 16) 194 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 195 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 196 197 #define CONFIG_SYS_NO_FLASH 198 199 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 200 #define CONFIG_CMDLINE_TAG 201 202 #define CONFIG_DDR_TRAINING_V2 203 #define DDR_SCRAMB_ENABLE 204 205 /*#define CONFIG_AUDIO_ENABLE*/ 206 207 /* Osd enable */ 208 #define CONFIG_OSD_ENABLE 209 /* base on needs #define CONFIG_CIPHER_ENABLE */ 210 /* base on needs #define CONFIG_OTP_ENABLE */ 211 #define CONFIG_PRODUCTNAME "hi3520dv500" 212 213 214 #endif /* __HI3520DV500_H */ 215 216