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1 /*
2  * hi3535av100.h
3  *
4  * Declaration of Header Files Related to the Chip.
5  *
6  * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
20  *
21  */
22 
23 #ifndef __HI3535AV100_H
24 #define __HI3535AV100_H
25 
26 #include <linux/sizes.h>
27 #include <asm/arch/platform.h>
28 
29 #define CONFIG_REMAKE_ELF
30 
31 #define CONFIG_SUPPORT_RAW_INITRD
32 
33 #define CONFIG_BOARD_EARLY_INIT_F
34 
35 /* Physical Memory Map */
36 
37 /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
38 #define CONFIG_SYS_TEXT_BASE		0x48800000
39 #define CONFIG_SYS_TEXT_BASE_ORI	0x48700000
40 
41 #define PHYS_SDRAM_1			0x40000000
42 #define PHYS_SDRAM_1_SIZE		0x20000000
43 
44 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
45 
46 #define CONFIG_SYS_INIT_SP_ADDR		0x0401A000
47 
48 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
49 #define CONFIG_SYS_GBL_DATA_SIZE	128
50 
51 /* Generic Timer Definitions */
52 #define COUNTER_FREQUENCY		0x1800000
53 
54 #define CONFIG_SYS_TIMER_RATE		CFG_TIMER_CLK
55 #define CONFIG_SYS_TIMER_COUNTER	(CFG_TIMERBASE + REG_TIMER_VALUE)
56 #define CONFIG_SYS_TIMER_COUNTS_DOWN
57 
58 /* Size of malloc() pool */
59 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
60 
61 /* PL011 Serial Configuration */
62 #define CONFIG_PL011_CLOCK		24000000
63 
64 #define CONFIG_PL01x_PORTS  \
65 {(void *)UART0_REG_BASE, (void *)UART1_REG_BASE, \
66 	(void *)UART2_REG_BASE, (void *)UART3_REG_BASE}
67 
68 #define CONFIG_CUR_UART_BASE	UART0_REG_BASE
69 
70 #define CONFIG_64BIT
71 
72 /* Network configuration */
73 
74 #define CONFIG_PHY_GIGE
75 #ifdef CONFIG_HIGMACV300_ETH
76 #define CONFIG_GMAC_NUMS        1
77 #define CONFIG_HIGMAC_PHY0_ADDR     1
78 #define CONFIG_HIGMAC_PHY0_INTERFACE_MODE	2 /* rgmii 2, rmii 1, mii 0 */
79 #define CONFIG_HIGMAC_PHY1_ADDR     3
80 #define CONFIG_HIGMAC_PHY1_INTERFACE_MODE	2 /* rgmii 2, rmii 1, mii 0 */
81 #define CONFIG_HIGMAC_DESC_4_WORD
82 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
83 #endif
84 
85 /* Flash Memory Configuration v100 */
86 #ifdef CONFIG_HIFMC
87 #define CONFIG_HIFMC_REG_BASE		FMC_REG_BASE
88 #define CONFIG_HIFMC_BUFFER_BASE	FMC_MEM_BASE
89 #define CONFIG_HIFMC_MAX_CS_NUM		2
90 #endif
91 
92 #ifdef CONFIG_HIFMC_SPI_NOR
93 #define CONFIG_CMD_SF
94 #define CONFIG_SPI_NOR_MAX_CHIP_NUM	1
95 #define CONFIG_SPI_NOR_QUIET_TEST
96 #endif
97 
98 #ifdef CONFIG_HIFMC_SPI_NAND
99 #define CONFIG_CMD_NAND
100 #define CONFIG_SPI_NAND_MAX_CHIP_NUM	1
101 #define CONFIG_SYS_MAX_NAND_DEVICE	CONFIG_SPI_NAND_MAX_CHIP_NUM
102 #define CONFIG_SYS_NAND_MAX_CHIPS	CONFIG_SPI_NAND_MAX_CHIP_NUM
103 #define CONFIG_SYS_NAND_BASE		FMC_MEM_BASE
104 #endif
105 
106 #ifdef CONFIG_HIFMC_NAND
107 /* base on needs #define CONFIG_NAND_EDO_MODE */
108 #define CONFIG_CMD_NAND
109 #define CONFIG_NAND_MAX_CHIP_NUM    1
110 #define CONFIG_SYS_MAX_NAND_DEVICE  CONFIG_NAND_MAX_CHIP_NUM
111 #define CONFIG_SYS_NAND_MAX_CHIPS   CONFIG_NAND_MAX_CHIP_NUM
112 #define CONFIG_SYS_NAND_BASE        FMC_MEM_BASE
113 #endif
114 
115 /* the flag for auto update. 1:enable; 0:disable */
116 #define CONFIG_AUTO_UPDATE			0
117 
118 #if (CONFIG_AUTO_UPDATE == 1)
119 #define CONFIG_AUTO_UPDATE_ADAPTATION   1
120 #define CONFIG_AUTO_USB_UPDATE	1
121 #define CONFIG_FS_FAT 1
122 #define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536
123 #endif
124 
125 /* SD/MMC configuration */
126 #ifdef CONFIG_MMC
127 /* base on needs #define CONFIG_MMC_SDMA */
128 #define CONFIG_EMMC
129 #define CONFIG_MMC_PHY
130 #define CONFIG_SUPPORT_EMMC_BOOT
131 #define CONFIG_GENERIC_MMC
132 #define CONFIG_CMD_MMC
133 #define CONFIG_SYS_MMC_ENV_DEV	0
134 #define CONFIG_EXT4_SPARSE
135 #define CONFIG_SDHCI
136 #define CONFIG_HISI_SDHCI
137 #define CONFIG_HISI_SDHCI_MAX_FREQ  148500000
138 #define CONFIG_FS_EXT4
139 #define CONFIG_SDHCI_ADMA
140 #define CONFIG_SUPPORT_EMMC_RPMB
141 #endif
142 
143 #define CONFIG_MISC_INIT_R
144 
145 /* Command line configuration */
146 #define CONFIG_MENU
147 /* base on needs #define CONFIG_CMD_UNZIP */
148 #define CONFIG_CMD_ENV
149 
150 #define CONFIG_MTD_PARTITIONS
151 
152 /* BOOTP options */
153 #define CONFIG_BOOTP_BOOTFILESIZE
154 
155 /* Initial environment variables */
156 
157 /*
158  * Defines where the kernel and FDT will be put in RAM
159  */
160 
161 /* Assume we boot with root on the seventh partition of eMMC */
162 #define CONFIG_BOOTARGS	"mem=256M console=ttyAMA0,115200n8"
163 #define CONFIG_BOOTCOMMAND "bootm 0x42000000"
164 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 3
165 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
166 #define BOOT_TARGET_DEVICES(func) \
167 	func(USB, usb, 0) \
168 func(MMC, mmc, 1) \
169 func(DHCP, dhcp, na)
170 #include <config_distro_bootcmd.h>
171 
172 /* allow change env */
173 #define  CONFIG_ENV_OVERWRITE
174 
175 #define CONFIG_COMMAND_HISTORY
176 
177 /* env in flash instead of CFG_ENV_IS_NOWHERE */
178 #define CONFIG_ENV_VARS_UBOOT_CONFIG
179 
180 /* kernel parameter list phy addr */
181 #define CFG_BOOT_PARAMS			(CONFIG_SYS_SDRAM_BASE + 0x0100)
182 
183 /* Monitor Command Prompt */
184 #define CONFIG_SYS_CBSIZE		1024 /* Console I/O Buffer Size */
185 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
186 					sizeof(CONFIG_SYS_PROMPT) + 16)
187 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
188 #define CONFIG_SYS_MAXARGS		64 /* max command args */
189 
190 #define CONFIG_SYS_NO_FLASH
191 
192 #define CONFIG_ARM64_SUPPORT_LOAD_FIP
193 
194 #define CONFIG_DDR_TRAINING_V2
195 #define DDR_SCRAMB_ENABLE
196 /* base on needs #define CONFIG_AUDIO_ENABLE */
197 
198 /* Osd enable */
199 #define CONFIG_OSD_ENABLE
200 /* base on needs #define CONFIG_CIPHER_ENABLE */
201 /* base on needs #define CONFIG_OTP_ENABLE */
202 #define CONFIG_PRODUCTNAME "hi3535av100"
203 
204 #endif /* __HI3535AV100_H */
205