1 /* 2 * hi3556av100.h 3 * 4 * Declaration of Header Files Related to the Chip. 5 * 6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 * 21 */ 22 23 #ifndef __HI3556AV100_H 24 #define __HI3556AV100_H 25 26 #include <linux/sizes.h> 27 #include <asm/arch/platform.h> 28 29 /* base on needs #define CONFIG_SYS_CACHELINE_SIZE 64 */ 30 31 /* base on needs #define CONFIG_REMAKE_ELF */ 32 33 #define CONFIG_SUPPORT_RAW_INITRD 34 35 #define CONFIG_BOARD_EARLY_INIT_F 36 37 /* Physical Memory Map */ 38 39 /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ 40 #define CONFIG_SYS_TEXT_BASE 0x20800000 41 #define CONFIG_SYS_TEXT_BASE_ORI 0x20700000 42 43 #define PHYS_SDRAM_1 0x20000000 44 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 0xE0000000 */ 45 46 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 47 48 #define CONFIG_SYS_INIT_SP_ADDR 0x04204000 49 50 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) 51 #define CONFIG_SYS_GBL_DATA_SIZE 128 52 53 /* Generic Timer Definitions */ 54 #define COUNTER_FREQUENCY 0x1800000 55 56 #define CONFIG_SYS_TIMER_RATE CFG_TIMER_CLK 57 #define CONFIG_SYS_TIMER_COUNTER (CFG_TIMERBASE + REG_TIMER_VALUE) 58 #define CONFIG_SYS_TIMER_COUNTS_DOWN 59 60 /* Size of malloc() pool */ 61 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) 62 63 /* PL011 Serial Configuration */ 64 #define CONFIG_PL011_CLOCK 24000000 65 66 #define CONFIG_PL01x_PORTS \ 67 {(void *)UART0_REG_BASE, (void *)UART1_REG_BASE, \ 68 (void *)UART2_REG_BASE, (void *)UART3_REG_BASE} 69 70 #define CONFIG_CUR_UART_BASE UART0_REG_BASE 71 72 /* Network configuration */ 73 #define CONFIG_PHY_GIGE 74 #ifdef CONFIG_HIGMACV300_ETH 75 #define CONFIG_GMAC_NUMS 1 76 #define CONFIG_HIGMAC_PHY0_ADDR 1 77 #define CONFIG_HIGMAC_PHY0_INTERFACE_MODE 2 /* rgmii 2, rmii 1 */ 78 #define CONFIG_HIGMAC_DESC_4_WORD 79 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 80 #endif 81 82 /* Flash Memory Configuration v100 */ 83 #ifdef CONFIG_HIFMC 84 #define CONFIG_HIFMC_REG_BASE FMC_REG_BASE 85 #define CONFIG_HIFMC_BUFFER_BASE FMC_MEM_BASE 86 #define CONFIG_HIFMC_MAX_CS_NUM 2 87 #endif 88 89 #ifdef CONFIG_HIFMC_SPI_NOR 90 #define CONFIG_CMD_SF 91 #define CONFIG_SPI_NOR_MAX_CHIP_NUM 1 92 #define CONFIG_SPI_NOR_QUIET_TEST 93 #endif 94 95 #ifdef CONFIG_HIFMC_SPI_NAND 96 #define CONFIG_CMD_NAND 97 #define CONFIG_SPI_NAND_MAX_CHIP_NUM 1 98 #define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_SPI_NAND_MAX_CHIP_NUM 99 #define CONFIG_SYS_NAND_MAX_CHIPS CONFIG_SPI_NAND_MAX_CHIP_NUM 100 #define CONFIG_SYS_NAND_BASE FMC_MEM_BASE 101 #endif 102 103 #ifdef CONFIG_HIFMC_NAND 104 /* base on needs #define CONFIG_NAND_EDO_MODE */ 105 #define CONFIG_CMD_NAND 106 #define CONFIG_NAND_MAX_CHIP_NUM 1 107 #define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_NAND_MAX_CHIP_NUM 108 #define CONFIG_SYS_NAND_MAX_CHIPS CONFIG_NAND_MAX_CHIP_NUM 109 #define CONFIG_SYS_NAND_BASE FMC_MEM_BASE 110 #endif 111 112 #define CONFIG_MISC_INIT_R 113 114 /* Command line configuration */ 115 #define CONFIG_MENU 116 #define CONFIG_CMD_UNZIP 117 #define CONFIG_CMD_ENV 118 119 #define CONFIG_MTD_PARTITIONS 120 121 /* BOOTP options */ 122 #define CONFIG_BOOTP_BOOTFILESIZE 123 124 /* Initial environment variables */ 125 126 /* 127 * Defines where the kernel and FDT will be put in RAM 128 */ 129 130 /* Assume we boot with root on the seventh partition of eMMC */ 131 #define CONFIG_BOOTARGS "mem=128M console=ttyAMA0,115200n8" 132 #define CONFIG_BOOTCOMMAND "bootm 0x22000000 0x23000000" 133 134 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 135 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 136 #define BOOT_TARGET_DEVICES(func) \ 137 func(USB, usb, 0) \ 138 func(MMC, mmc, 1) \ 139 func(DHCP, dhcp, na) 140 #include <config_distro_bootcmd.h> 141 142 /* allow change env */ 143 #define CONFIG_ENV_OVERWRITE 144 145 #define CONFIG_COMMAND_HISTORY 146 147 /* env in flash instead of CFG_ENV_IS_NOWHERE */ 148 #define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */ 149 150 #define CONFIG_ENV_SIZE 0x40000 151 #define CONFIG_ENV_SECT_SIZE 0x10000 152 #define CONFIG_ENV_VARS_UBOOT_CONFIG 153 154 /* kernel parameter list phy addr */ 155 #define CFG_BOOT_PARAMS (CONFIG_SYS_SDRAM_BASE + 0x0100) 156 157 /* Monitor Command Prompt */ 158 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 159 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 160 sizeof(CONFIG_SYS_PROMPT) + 16) 161 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 162 163 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 164 165 #define CONFIG_SYS_NO_FLASH 166 167 168 /* base on needs #define DDR_SCRAMB_ENABLE */ 169 170 /* base on needs #define CONFIG_AUDIO_ENABLE */ 171 /* Osd enable */ 172 /* base on needs #define CONFIG_OSD_ENABLE */ 173 #define CONFIG_PRODUCTNAME "hi3556av100" 174 175 176 /* the flag for auto update. 1:enable; 0:disable */ 177 #define CONFIG_AUTO_UPDATE 1 178 179 #if (CONFIG_AUTO_UPDATE == 1) 180 #define CONFIG_AUTO_UPDATE_ADAPTATION 1 181 #define CONFIG_AUTO_SD_UPDATE 1 182 #define CONFIG_AUTO_USB_UPDATE 1 183 184 #define CONFIG_FS_FAT 1 185 #define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536 186 #endif 187 188 /*--------------------------------------------------------------------- 189 * sdcard system updae 190 * ---------------------------------------------------------------------*/ 191 #ifdef CONFIG_AUTO_SD_UPDATE 192 193 #ifndef CONFIG_SDHCI 194 #define CONFIG_MMC_WRITE 1 195 #define CONFIG_MMC_QUIRKS 1 196 #define CONFIG_MMC_HW_PARTITIONING 1 197 #define CONFIG_MMC_HS400_ES_SUPPORT 1 198 #define CONFIG_MMC_HS400_SUPPORT 1 199 #define CONFIG_MMC_HS200_SUPPORT 1 200 #define CONFIG_MMC_VERBOSE 1 201 #define CONFIG_MMC_SDHCI 1 202 #define CONFIG_MMC_SDHCI_ADMA 1 203 #endif 204 205 #ifndef CONFIG_MMC 206 #define CONFIG_MMC 1 207 #endif 208 209 #ifndef CONFIG_HIFMC 210 #define CONFIG_EMMC 211 #endif 212 #endif 213 214 /* SD/MMC configuration */ 215 #ifdef CONFIG_MMC 216 #define CONFIG_SUPPORT_EMMC_BOOT 217 #define CONFIG_GENERIC_MMC 218 #define CONFIG_CMD_MMC 219 #define CONFIG_SYS_MMC_ENV_DEV 0 220 #define CONFIG_EXT4_SPARSE 221 #define CONFIG_SDHCI 222 #define CONFIG_HISI_SDHCI 223 #define CONFIG_HISI_SDHCI_MAX_FREQ 200000000 224 #define CONFIG_BOUNCE_BUFFER 225 #define CONFIG_FS_EXT4 226 #define CONFIG_SDHCI_ADMA 227 #endif 228 229 #define CONFIG_SKIP_LOWLEVEL_INIT 230 #define CONFIG_CMDLINE_TAG 231 232 #define CONFIG_CMD_UGZIP 233 234 #define HIGZIP_HEAD_SIZE 0X10 235 #define HEAD_MAGIC_NUM0 0X70697A67 /* 'g''z''i''p' */ 236 #define HEAD_MAGIC_NUM0_OFFSET 0X8 237 #define HEAD_MAGIC_NUM1 0X64616568 /* 'h''e''a''d' */ 238 #define HEAD_MAGIC_NUM1_OFFSET 0XC 239 #define COMPRESSED_SIZE_OFFSET 0X0 240 #define UNCOMPRESSED_SIZE_OFFSET 0X4 241 242 #define CONFIG_DDR_TRAINING_V2 243 244 /* base on needs #define CONFIG_CIPHER_ENABLE */ 245 246 /* the macro for pmu by i2c */ 247 /* base on needs #define I2C_PMU_ENABLE */ 248 249 #endif /* __HI3556AV100_H */ 250