1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 */
18
19 #include "vou_drv.h"
20 #include "hi_type.h"
21 #include "vou_reg.h"
22 #include "vou_def.h"
23 #include "vou_hal.h"
24 #include "vou_coef_org.h"
25
26 #define VO_DEV_MAX_NUM 2
27 #define VO_LAYER_MAX_NUM 2
28
29 #define VO_SD_VTTH_WATERLINE 100
30 #define VO_HD_VTTH_WATERLINE 240
31
32 #define VO_BACKGROUD_BLACK 0x8080
33 #define VO_BACKGROUD_GREEN 0x804D3A42
34 #define VO_BACKGROUD_WHITE 0x3fffffff
35 #define VO_BACKGROUD_DEFAULT VO_BACKGROUD_WHITE
36
37 /* vou interrupt mask type */
38 typedef enum {
39 VO_INTMSK_NONE = 0,
40 VO_INTMSK_DHD0_VTTHD1 = 0x1,
41 VO_INTMSK_DHD0_VTTHD2 = 0x2,
42 VO_INTMSK_DHD0_VTTHD3 = 0x4,
43 VO_INTMSK_DHD0_UFINT = 0x8,
44
45 VO_INTMSK_DHD1_VTTHD1 = 0x10,
46 VO_INTMSK_DHD1_VTTHD2 = 0x20,
47 VO_INTMSK_DHD1_VTTHD3 = 0x40,
48 VO_INTMSK_DHD1_UFINT = 0x80,
49
50 VO_INTMSK_DSD_VTTHD1 = 0x100,
51 VO_INTMSK_DSD_VTTHD2 = 0x200,
52 VO_INTMSK_DSD_VTTHD3 = 0x400,
53 VO_INTMSK_DSD_UFINT = 0x800,
54
55 VO_INTMSK_B0_ERR = 0x1000,
56 VO_INTMSK_B1_ERR = 0x2000,
57 VO_INTMSK_B2_ERR = 0x4000,
58
59 VO_INTMSK_WBC_DHDOVER = 0x8000,
60
61 VO_INTREPORT_ALL = 0xffffffff
62 } vo_int_mask;
63
64 typedef struct {
65 hi_bool enable;
66 hi_u32 bk_grd;
67 vo_intf_type intf_type;
68 vo_intf_sync out_sync;
69 hal_disp_pixel_format pixel_fmt;
70 } hal_dev_config;
71
72 typedef struct {
73 hi_u32 bk_grd;
74 } hal_layer_config;
75
76 typedef struct {
77 hi_s32 luma;
78 hi_s32 cont;
79 hi_s32 hue;
80 hi_s32 satu;
81 } hal_csc_value;
82
83 typedef struct {
84 hi_u32 base_phys;
85 hi_void *base_virt;
86 hi_u32 hor;
87 hi_u32 ver422;
88 hi_u32 ver420;
89 hi_u32 lut;
90 hi_u32 gam;
91 hi_u32 acc;
92 } hal_coef_addr;
93
94 hal_disp_syncinfo g_sync_timing[VO_OUTPUT_BUTT] = {
95 /* synm, iop, itf, vact, vbb, vfb, hact, hbb, hfb, hmid,bvact,bvbb, bvfb, hpw, vpw,idv, ihs, ivs */
96 { 0, 0, 0, 288, 22, 2, 720, 132, 12, 1, 288, 23, 2, 126, 3, 0, 0, 0 }, /* 576I(PAL) */
97 { 0, 0, 0, 240, 18, 4, 720, 119, 19, 1, 240, 19, 4, 124, 3, 0, 0, 0 }, /* 480I(NTSC) */
98 { 0, 1, 1, 1080, 41, 4, 1920, 192, 638, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@24Hz */
99 { 0, 1, 1, 1080, 41, 4, 1920, 192, 528, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@25Hz */
100 { 0, 1, 1, 1080, 41, 4, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@30Hz */
101 { 0, 1, 1, 720, 25, 5, 1280, 260, 440, 1, 1, 1, 1, 40, 5, 0, 0, 0 }, /* 720P@50Hz */
102 { 0, 1, 1, 720, 25, 5, 1280, 260, 110, 1, 1, 1, 1, 40, 5, 0, 0, 0 }, /* 720P@60Hz */
103 { 0, 0, 1, 540, 20, 2, 1920, 192, 528, 1128, 540, 21, 2, 44, 5, 0, 0, 0 }, /* 1080I@50Hz */
104 { 0, 0, 1, 540, 20, 2, 1920, 192, 88, 908, 540, 21, 2, 44, 5, 0, 0, 0 }, /* 1080I@60Hz */
105 { 0, 1, 1, 1080, 41, 4, 1920, 192, 528, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@50Hz */
106 { 0, 1, 1, 1080, 41, 4, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1080P@60Hz */
107 { 1, 1, 1, 576, 44, 5, 720, 132, 12, 1, 1, 1, 1, 64, 5, 0, 0, 0 }, /* 576P@50Hz */
108 { 1, 1, 1, 480, 36, 9, 720, 122, 16, 1, 1, 1, 1, 62, 6, 0, 0, 0 }, /* 480P@60Hz */
109 { 1, 1, 2, 600, 27, 1, 800, 216, 40, 1, 1, 1, 1, 128, 4, 0, 0, 0 }, /* 800*600@60Hz VGA@60Hz */
110 { 1, 1, 2, 768, 35, 3, 1024, 296, 24, 1, 1, 1, 1, 136, 6, 0, 1, 1 }, /* 1024x768@60Hz */
111 { 1, 1, 2, 1024, 41, 1, 1280, 360, 48, 1, 1, 1, 1, 112, 3, 0, 0, 0 }, /* 1280x1024@60Hz */
112 { 1, 1, 2, 768, 27, 3, 1366, 356, 70, 1, 1, 1, 1, 143, 3, 0, 0, 0 }, /* 1366x768@60Hz */
113 { 1, 1, 2, 900, 31, 3, 1440, 384, 80, 1, 1, 1, 1, 152, 6, 0, 1, 0 }, /* 1440x900@60Hz */
114 { 1, 1, 2, 800, 28, 3, 1280, 328, 72, 1, 1, 1, 1, 128, 6, 0, 1, 0 }, /* 1280*800@60Hz VGA@60Hz */
115 { 1, 1, 2, 1200, 49, 1, 1600, 496, 64, 1, 1, 1, 1, 192, 3, 0, 0, 0 }, /* 1600*1200@60Hz */
116 { 1, 1, 2, 1050, 36, 3, 1680, 456, 104, 1, 1, 1, 1, 176, 6, 0, 1, 0 }, /* 1680*1050@60Hz */
117 { 1, 1, 2, 1200, 32, 3, 1920, 112, 48, 1, 1, 1, 1, 32, 6, 0, 0, 1 }, /* 1920*1200@60Hz CVT (reduced blanking) */
118 { 1, 1, 2, 480, 35, 10, 640, 144, 16, 1, 1, 1, 1, 96, 2, 0, 1, 1 }, /* 640*480@60Hz CVT */
119 { 0, 0, 0, 288, 22, 2, 960, 176, 16, 1, 288, 23, 2, 168, 3, 0, 0, 0 }, /* 960H(PAL) */
120 { 0, 0, 0, 240, 18, 4, 960, 163, 21, 1, 240, 19, 4, 168, 3, 0, 0, 0 }, /* 960H(NTSC) */
121 { 0, 1, 1, 2160, 72, 8, 1920, 192, 88, 1, 1, 1, 1, 44, 5, 0, 0, 0 }, /* 1920*2160@30Hz */
122 { 1, 1, 2, 1440, 39, 2, 2560, 112, 48, 1, 1, 1, 1, 32, 5, 0, 0, 0 }, /* 2560*1440@30Hz */
123 { 1, 1, 2, 1440, 39, 2, 2560, 112, 48, 1, 1, 1, 1, 32, 5, 0, 0, 0 }, /* 2560*1440@60Hz */
124 { 0, 1, 2, 1600, 43, 3, 2560, 112, 48, 1, 1, 1, 1, 32, 6, 0, 0, 1 }, /* 2560*1600@60Hz CVT (reduced blanking) */
125 { 0, 1, 1, 2160, 82, 8, 3840, 384, 1276, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@24Hz */
126 { 0, 1, 1, 2160, 82, 8, 3840, 384, 1056, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@25Hz */
127 { 0, 1, 1, 2160, 82, 8, 3840, 384, 176, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@30Hz */
128 { 0, 1, 1, 2160, 82, 8, 3840, 384, 1056, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@50Hz */
129 { 0, 1, 1, 2160, 82, 8, 3840, 384, 176, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 3840*2160@60Hz */
130 { 0, 1, 1, 2160, 82, 8, 4096, 384, 1020, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@24 */
131 { 0, 1, 1, 2160, 82, 8, 4096, 216, 968, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@25 */
132 { 0, 1, 1, 2160, 82, 8, 4096, 216, 88, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@30 */
133 { 0, 1, 1, 2160, 82, 8, 4096, 216, 968, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@50 */
134 { 0, 1, 1, 2160, 82, 8, 4096, 216, 88, 1, 1, 1, 1, 88, 10, 0, 0, 0 }, /* 4096x2160@60 */
135 { 0, 1, 1, 240, 15, 9, 320, 65, 7, 1, 240, 14, 9, 1, 1, 0, 0, 0 }, /* 320X240@60 8bit LCD */
136 { 0, 1, 1, 240, 2, 2, 320, 5, 10, 1, 1, 1, 1, 10, 1, 0, 0, 0 }, /* 320X240@50 6bit LCD */
137 { 0, 1, 1, 320, 10, 4, 240, 30, 10, 1, 1, 1, 1, 10, 2, 0, 0, 0 }, /* 240X320@50 6bit LCD */
138 { 0, 1, 1, 320, 2, 2, 240, 20, 10, 1, 1, 1, 1, 2, 1, 0, 0, 0 }, /* 240X320@60 16bit LCD */
139 { 0, 1, 1, 600, 23, 12, 800, 210, 46, 1, 1, 1, 1, 2, 1, 0, 0, 0 }, /* 800X600@60 24bit LCD */
140 { 0, 1, 1, 1280, 24, 8, 720, 123, 99, 1, 1, 1, 1, 24, 4, 0, 0, 0 }, /* 720 x1280 at 60 hz */
141 { 0, 1, 1, 1920, 36, 16, 1080, 28, 130, 1, 1, 1, 1, 24, 4, 0, 0, 0 }, /* 1080 x1920 at 60 hz */
142 { 0, 1, 1, 4320, 64, 16, 7680, 768, 552, 1, 1, 1, 1, 176, 20, 0, 0, 0 }, /* 7680x4320@30 */
143 {} /* user */
144 };
145
146 static hal_dev_config g_hal_dev_cfg[VO_DEV_MAX_NUM] = {
147 {
148 .enable = HI_FALSE,
149 .bk_grd = VO_BACKGROUD_DEFAULT,
150 .intf_type = VO_INTF_HDMI | VO_INTF_BT1120 | VO_INTF_BT656,
151 .out_sync = VO_OUTPUT_1080P60,
152 .pixel_fmt = HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_422,
153 },
154 {
155 .enable = HI_FALSE,
156 .bk_grd = VO_BACKGROUD_DEFAULT,
157 .intf_type = VO_INTF_BT1120 | VO_INTF_BT656 | VO_INTF_LCD,
158 .out_sync = VO_OUTPUT_1080P60,
159 .pixel_fmt = HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_422,
160 }
161 };
162
163 #define max2(x, y) ((x) > (y) ? (x) : (y))
164 #define min2(x, y) ((x) < (y) ? (x) : (y))
165 #define clip_min(x, min) (((x) >= (min)) ? (x) : (min))
166
rgb_to_yuv_full(hi_u32 rgb)167 static hi_u32 rgb_to_yuv_full(hi_u32 rgb)
168 {
169 hi_u16 y, u, v;
170 hi_u16 r, g, b;
171 hi_u16 py_temp, pcb_temp, pcr_temp;
172
173 r = rgb_r(rgb);
174 g = rgb_g(rgb);
175 b = rgb_b(rgb);
176
177 /* to calculate rgb to yc, the numbers is from algorithm, not magic numbers */
178 py_temp = (hi_u16)(((r * 76 + g * 150 + b * 29) >> 8) * 4);
179 pcb_temp = (hi_u16)(clip_min(((((b * 130 - r * 44) - g * 86) >> 8) + 128), 0) * 4);
180 pcr_temp = (hi_u16)(clip_min(((((r * 130 - g * 109) - b * 21) >> 8) + 128), 0) * 4);
181
182 /* value 0 - 1023 */
183 y = max2(min2(py_temp, 1023), 0);
184 u = max2(min2(pcb_temp, 1023), 0);
185 v = max2(min2(pcr_temp, 1023), 0);
186
187 return yuv(y, u, v);
188 }
189
vo_drv_board_init(hi_void)190 hi_void vo_drv_board_init(hi_void)
191 {
192 hal_vo_init();
193 vo_drv_default_setting();
194 }
195
vo_drv_int_reg_up_mode(vo_hal_layer vo_layer,vo_int_mode int_mode)196 hi_void vo_drv_int_reg_up_mode(vo_hal_layer vo_layer, vo_int_mode int_mode)
197 {
198 hal_video_set_layer_up_mode(vo_layer, int_mode);
199 return;
200 }
201
vo_drv_set_dev_intf_type(hi_s32 vo_dev,vo_intf_type intf_type)202 hi_void vo_drv_set_dev_intf_type(hi_s32 vo_dev, vo_intf_type intf_type)
203 {
204 g_hal_dev_cfg[vo_dev].intf_type = intf_type;
205 return;
206 }
207
vo_drv_set_dev_bk_grd(hi_s32 vo_dev,hi_u32 bg_color)208 hi_void vo_drv_set_dev_bk_grd(hi_s32 vo_dev, hi_u32 bg_color)
209 {
210 g_hal_dev_cfg[vo_dev].bk_grd = bg_color;
211 return;
212 }
213
vo_drv_set_dev_out_sync(hi_s32 vo_dev,vo_intf_sync vo_out_mode)214 hi_void vo_drv_set_dev_out_sync(hi_s32 vo_dev, vo_intf_sync vo_out_mode)
215 {
216 g_hal_dev_cfg[vo_dev].out_sync = vo_out_mode;
217 return;
218 }
219
220 /* interrupt relative */
vo_drv_dev_int_enable(vo_hal_dev vo_dev,hi_bool enable)221 hi_void vo_drv_dev_int_enable(vo_hal_dev vo_dev, hi_bool enable)
222 {
223 vo_int_mask int_type;
224 vo_int_mask hifb_int_type = 0x0;
225
226 switch (vo_dev) {
227 case VO_DEV_DHD0:
228 int_type = VO_INTMSK_DHD0_VTTHD1;
229 hifb_int_type = VO_INTMSK_DHD0_VTTHD2 | VO_INTMSK_DHD0_VTTHD3;
230 break;
231
232 case VO_DEV_DHD1:
233 int_type = VO_INTMSK_DHD1_VTTHD1;
234 hifb_int_type = VO_INTMSK_DHD1_VTTHD2 | VO_INTMSK_DHD1_VTTHD3;
235 break;
236
237 default:
238 return;
239 }
240
241 if (enable == HI_TRUE) {
242 hal_disp_set_int_mask(int_type);
243 hal_disp_set_int_mask1(hifb_int_type);
244 } else {
245 hal_disp_clr_int_mask(int_type);
246 hal_disp_clr_int_mask1(hifb_int_type);
247 }
248
249 return;
250 }
251
vo_drv_int_set_mode(hi_s32 vo_dev,vo_int_mode int_mode)252 hi_void vo_drv_int_set_mode(hi_s32 vo_dev, vo_int_mode int_mode)
253 {
254 hal_disp_set_vt_thd_mode(vo_dev, int_mode);
255 return;
256 }
257
vo_drv_layer_enable(vo_hal_layer vo_layer,hi_bool enable)258 hi_void vo_drv_layer_enable(vo_hal_layer vo_layer, hi_bool enable)
259 {
260 hal_layer_enable_layer(vo_layer, enable);
261 return;
262 }
263
vo_drv_def_layer_bind_dev(hi_void)264 hi_void vo_drv_def_layer_bind_dev(hi_void)
265 {
266 hal_cbm_set_cbm_mixer_prio(HAL_DISP_LAYER_VHD0, VO_MIX_PRIO0, HAL_CBMMIX1);
267 hal_cbm_set_cbm_mixer_prio(HAL_DISP_LAYER_GFX0, VO_MIX_PRIO2, HAL_CBMMIX1);
268 hal_cbm_set_cbm_mixer_prio(HAL_DISP_LAYER_VHD1, VO_MIX_PRIO0, HAL_CBMMIX2);
269 hal_cbm_set_cbm_mixer_prio(HAL_DISP_LAYER_GFX1, VO_MIX_PRIO2, HAL_CBMMIX2);
270
271 return;
272 }
273
vo_drv_set_uhd_clk(vo_hal_dev vo_dev,vo_intf_sync intf_sync)274 hi_void vo_drv_set_uhd_clk(vo_hal_dev vo_dev, vo_intf_sync intf_sync)
275 {
276 /* the numbers below is the default value of the register. */
277 hi_u32 frac = 0;
278 hi_u32 postdiv1 = 0;
279 hi_u32 postdiv2 = 0;
280 hi_u32 fbdiv = 0;
281 hi_u32 refdiv = 0;
282 hi_u32 vdp_hd_clk_sel = 0x0;
283 hi_u32 lcd_mclk_div = 0x015E4C3;
284
285 switch (intf_sync) {
286 /* the number is pll register config, calculate from out sync */
287 case VO_OUTPUT_PAL:
288 case VO_OUTPUT_NTSC:
289 case VO_OUTPUT_576P50:
290 case VO_OUTPUT_480P60: {
291 /* 27MHz */
292 fbdiv = 81;
293 frac = 0;
294 refdiv = 2;
295 postdiv1 = 6;
296 postdiv2 = 6;
297 vdp_hd_clk_sel = 0x2;
298 break;
299 }
300
301 case VO_OUTPUT_1080P24:
302 case VO_OUTPUT_1080P25:
303 case VO_OUTPUT_1080P30:
304 case VO_OUTPUT_720P50:
305 case VO_OUTPUT_720P60:
306 case VO_OUTPUT_1080I50:
307 case VO_OUTPUT_1080I60:
308 case VO_OUTPUT_720x1280_60: {
309 /* 74.25MHz */
310 fbdiv = 99;
311 frac = 0;
312 refdiv = 2;
313 postdiv1 = 4;
314 postdiv2 = 4;
315 vdp_hd_clk_sel = 0x2;
316 break;
317 }
318
319 case VO_OUTPUT_1080P50:
320 case VO_OUTPUT_1080P60:
321 case VO_OUTPUT_1920x2160_30:
322 case VO_OUTPUT_1080x1920_60: {
323 /* 148.5MHz */
324 fbdiv = 99;
325 frac = 0;
326 refdiv = 2;
327 postdiv1 = 4;
328 postdiv2 = 2;
329 vdp_hd_clk_sel = 0x2;
330 break;
331 }
332
333 case VO_OUTPUT_800x600_60: {
334 /* 40MHz */
335 fbdiv = 80;
336 frac = 0;
337 refdiv = 2;
338 postdiv1 = 6;
339 postdiv2 = 4;
340 vdp_hd_clk_sel = 0x2;
341
342 break;
343 }
344
345 case VO_OUTPUT_1024x768_60: {
346 /* 65MHz */
347 fbdiv = 65;
348 frac = 0;
349 refdiv = 1;
350 postdiv1 = 6;
351 postdiv2 = 4;
352 vdp_hd_clk_sel = 0x2;
353 break;
354 }
355
356 case VO_OUTPUT_1280x1024_60: {
357 /* 108MHz */
358 fbdiv = 72;
359 frac = 0;
360 refdiv = 2;
361 postdiv1 = 4;
362 postdiv2 = 2;
363 vdp_hd_clk_sel = 0x2;
364
365 break;
366 }
367
368 case VO_OUTPUT_1366x768_60: {
369 /* 85.5MHz */
370 fbdiv = 171;
371 frac = 0;
372 refdiv = 4;
373 postdiv1 = 6;
374 postdiv2 = 2;
375 vdp_hd_clk_sel = 0x2;
376
377 break;
378 }
379
380 case VO_OUTPUT_1440x900_60: {
381 /* 106.5MHz */
382 fbdiv = 213;
383 frac = 0;
384 refdiv = 4;
385 postdiv1 = 6;
386 postdiv2 = 2;
387 vdp_hd_clk_sel = 0x2;
388
389 break;
390 }
391
392 case VO_OUTPUT_1280x800_60: {
393 /* 83.5MHz */
394 fbdiv = 167;
395 frac = 0;
396 refdiv = 4;
397 postdiv1 = 6;
398 postdiv2 = 2;
399 vdp_hd_clk_sel = 0x2;
400
401 break;
402 }
403
404 case VO_OUTPUT_1600x1200_60: {
405 /* 162MHz */
406 fbdiv = 81;
407 frac = 0;
408 refdiv = 2;
409 postdiv1 = 3;
410 postdiv2 = 2;
411 vdp_hd_clk_sel = 0x1;
412
413 break;
414 }
415
416 case VO_OUTPUT_1680x1050_60: {
417 /* 146.25MHz */
418 fbdiv = 585;
419 frac = 0;
420 refdiv = 8;
421 postdiv1 = 6;
422 postdiv2 = 2;
423 vdp_hd_clk_sel = 0x2;
424
425 break;
426 }
427
428 case VO_OUTPUT_1920x1200_60: {
429 /* 154MHz */
430 fbdiv = 154;
431 frac = 0;
432 refdiv = 4;
433 postdiv1 = 3;
434 postdiv2 = 2;
435 vdp_hd_clk_sel = 0x1;
436
437 break;
438 }
439
440 case VO_OUTPUT_640x480_60: {
441 /* 25.175MHz */
442 fbdiv = 113;
443 frac = 4823450;
444 refdiv = 3;
445 postdiv1 = 6;
446 postdiv2 = 6;
447 vdp_hd_clk_sel = 0x2;
448
449 break;
450 }
451
452 case VO_OUTPUT_320x240_60: {
453 /* lcd clk config */
454 vdp_hd_clk_sel = 0x3;
455 lcd_mclk_div = 0x2ad11d;
456 break;
457 }
458
459 case VO_OUTPUT_320x240_50: {
460 /* lcd clk config */
461 vdp_hd_clk_sel = 0x2;
462 lcd_mclk_div = 0x152306;
463 break;
464 }
465
466 case VO_OUTPUT_240x320_50: {
467 /* lcd clk config */
468 vdp_hd_clk_sel = 0x2;
469 lcd_mclk_div = 0x169f00;
470 break;
471 }
472
473 case VO_OUTPUT_240x320_60: {
474 /* lcd clk config */
475 vdp_hd_clk_sel = 0x0;
476 lcd_mclk_div = 0x90c54;
477 break;
478 }
479
480 case VO_OUTPUT_800x600_50: {
481 /* lcd clk config */
482 vdp_hd_clk_sel = 0x0;
483 lcd_mclk_div = 0x39cc92;
484 break;
485 }
486
487 case VO_OUTPUT_2560x1440_30: {
488 /* 241.6992MHz */
489 fbdiv = 1209;
490 frac = 0;
491 refdiv = 24;
492 postdiv1 = 5;
493 postdiv2 = 2;
494 vdp_hd_clk_sel = 0x2;
495 break;
496 }
497
498 case VO_OUTPUT_2560x1440_60: {
499 /* 241.6992MHz */
500 fbdiv = 161;
501 frac = 0;
502 refdiv = 4;
503 postdiv1 = 4;
504 postdiv2 = 1;
505 vdp_hd_clk_sel = 0x1;
506 break;
507 }
508
509 case VO_OUTPUT_2560x1600_60: {
510 /* 268.6272MHz */
511 fbdiv = 179;
512 frac = 0;
513 refdiv = 2;
514 postdiv1 = 4;
515 postdiv2 = 2;
516 vdp_hd_clk_sel = 0x1;
517 break;
518 }
519
520 case VO_OUTPUT_3840x2160_24:
521 case VO_OUTPUT_3840x2160_25:
522 case VO_OUTPUT_3840x2160_30:
523 case VO_OUTPUT_4096x2160_24:
524 case VO_OUTPUT_4096x2160_25:
525 case VO_OUTPUT_4096x2160_30: {
526 /* 297MHz */
527 fbdiv = 99;
528 frac = 0;
529 refdiv = 2;
530 postdiv1 = 4;
531 postdiv2 = 1;
532 vdp_hd_clk_sel = 0x1;
533 break;
534 }
535
536 case VO_OUTPUT_3840x2160_50:
537 case VO_OUTPUT_3840x2160_60:
538 case VO_OUTPUT_4096x2160_50:
539 case VO_OUTPUT_4096x2160_60: {
540 /* 594MHz */
541 fbdiv = 99;
542 frac = 0;
543 refdiv = 2;
544 postdiv1 = 2;
545 postdiv2 = 1;
546
547 vdp_hd_clk_sel = 0x0;
548 break;
549 }
550
551 case VO_OUTPUT_7680x4320_30: {
552 /* 594MHz */
553 fbdiv = 99;
554 frac = 0;
555 refdiv = 2;
556 postdiv1 = 2;
557 postdiv2 = 1;
558 vdp_hd_clk_sel = 0x0;
559 break;
560 }
561
562 default: {
563 return;
564 }
565 }
566
567 sys_hal_lcd_mclk_div(lcd_mclk_div);
568 sys_hal_vo_hd0_ppc_sel(vdp_hd_clk_sel);
569 sys_hal_set_vo_pll_fbdiv(vo_dev, fbdiv);
570 sys_hal_set_vo_pll_frac(vo_dev, frac);
571 sys_hal_set_vo_pll_refdiv(vo_dev, refdiv);
572 sys_hal_set_vo_pll_postdiv1(vo_dev, postdiv1);
573 sys_hal_set_vo_pll_postdiv2(vo_dev, postdiv2);
574 return;
575 }
576
vo_drv_set_hd_clk(vo_hal_dev vo_dev,vo_intf_sync intf_sync)577 hi_void vo_drv_set_hd_clk(vo_hal_dev vo_dev, vo_intf_sync intf_sync)
578 {
579 /* the numbers below is the default value of the register. */
580 hi_u32 spll_frac = 0;
581 hi_u32 spll_postdiv1 = 0;
582 hi_u32 spll_postdiv2 = 0;
583 hi_u32 spll_fbdiv = 0;
584 hi_u32 spll_refdiv = 0;
585 hi_u32 vdp_out_clk_sel = 0x0;
586 hi_u32 hd1_div_mod = 0x0;
587 hi_u32 lcd_mclk_div = 0x015E4C3;
588
589 switch (intf_sync) {
590 /* the number is pll register config, calculate from out sync */
591 case VO_OUTPUT_PAL:
592 case VO_OUTPUT_NTSC: {
593 /* 27MHz */
594 vdp_out_clk_sel = 0x5;
595 break;
596 }
597
598 case VO_OUTPUT_1080P24:
599 case VO_OUTPUT_1080P25:
600 case VO_OUTPUT_1080P30:
601 case VO_OUTPUT_720P50:
602 case VO_OUTPUT_720P60:
603 case VO_OUTPUT_1080I50:
604 case VO_OUTPUT_1080I60:
605 case VO_OUTPUT_720x1280_60: {
606 /* 74.25MHz */
607 vdp_out_clk_sel = 0x1;
608 break;
609 }
610
611 case VO_OUTPUT_1080P50:
612 case VO_OUTPUT_1080P60:
613 case VO_OUTPUT_1920x2160_30:
614 case VO_OUTPUT_1080x1920_60: {
615 /* 148.5MHz */
616 vdp_out_clk_sel = 0x0;
617 break;
618 }
619
620 case VO_OUTPUT_576P50:
621 case VO_OUTPUT_480P60: {
622 /* 27MHz */
623 vdp_out_clk_sel = 0x5;
624 break;
625 }
626
627 case VO_OUTPUT_800x600_60: {
628 /* 40MHz */
629 spll_fbdiv = 80;
630 spll_frac = 0;
631 spll_refdiv = 2;
632 spll_postdiv1 = 6;
633 spll_postdiv2 = 4;
634
635 vdp_out_clk_sel = 0x7;
636
637 break;
638 }
639
640 case VO_OUTPUT_1024x768_60: {
641 /* 65MHz */
642 spll_fbdiv = 65;
643 spll_frac = 0;
644 spll_refdiv = 1;
645 spll_postdiv1 = 6;
646 spll_postdiv2 = 4;
647 vdp_out_clk_sel = 0x7;
648 break;
649 }
650
651 case VO_OUTPUT_1280x1024_60: {
652 /* 108MHz */
653 spll_fbdiv = 72;
654 spll_frac = 0;
655 spll_refdiv = 2;
656 spll_postdiv1 = 4;
657 spll_postdiv2 = 2;
658 vdp_out_clk_sel = 0x7;
659 break;
660 }
661
662 case VO_OUTPUT_1366x768_60: {
663 /* 85.5MHz */
664 spll_fbdiv = 171;
665 spll_frac = 0;
666 spll_refdiv = 4;
667 spll_postdiv1 = 6;
668 spll_postdiv2 = 2;
669 vdp_out_clk_sel = 0x7;
670 break;
671 }
672
673 case VO_OUTPUT_1440x900_60: {
674 /* 106.5MHz */
675 spll_fbdiv = 213;
676 spll_frac = 0;
677 spll_refdiv = 4;
678 spll_postdiv1 = 6;
679 spll_postdiv2 = 2;
680 vdp_out_clk_sel = 0x7;
681 break;
682 }
683
684 case VO_OUTPUT_1280x800_60: {
685 /* 83.5MHz */
686 spll_fbdiv = 167;
687 spll_frac = 0;
688 spll_refdiv = 4;
689 spll_postdiv1 = 6;
690 spll_postdiv2 = 2;
691 vdp_out_clk_sel = 0x7;
692 break;
693 }
694
695 case VO_OUTPUT_1600x1200_60: {
696 /* 162MHz */
697 spll_fbdiv = 81;
698 spll_frac = 0;
699 spll_refdiv = 2;
700 spll_postdiv1 = 3;
701 spll_postdiv2 = 2;
702 vdp_out_clk_sel = 0x7;
703
704 break;
705 }
706
707 case VO_OUTPUT_1680x1050_60: {
708 /* 146.25MHz */
709 spll_fbdiv = 585;
710 spll_frac = 0;
711 spll_refdiv = 8;
712 spll_postdiv1 = 6;
713 spll_postdiv2 = 2;
714 vdp_out_clk_sel = 0x7;
715 break;
716 }
717
718 case VO_OUTPUT_1920x1200_60: {
719 /* 154MHz */
720 spll_fbdiv = 154;
721 spll_frac = 0;
722 spll_refdiv = 4;
723 spll_postdiv1 = 3;
724 spll_postdiv2 = 2;
725 vdp_out_clk_sel = 0x7;
726 break;
727 }
728
729 case VO_OUTPUT_640x480_60: {
730 /* 25.175MHz */
731 spll_fbdiv = 113;
732 spll_frac = 4823450;
733 spll_refdiv = 3;
734 spll_postdiv1 = 6;
735 spll_postdiv2 = 6;
736 vdp_out_clk_sel = 0x7;
737 break;
738 }
739
740 case VO_OUTPUT_960H_PAL: {
741 /* 35.942MHz */
742 vdp_out_clk_sel = 0x6;
743 hd1_div_mod = 0x1;
744 lcd_mclk_div = 0x83df618;
745 break;
746 }
747
748 case VO_OUTPUT_960H_NTSC: {
749 /* 35.967360MHz */
750 vdp_out_clk_sel = 0x6;
751 hd1_div_mod = 0x1;
752 lcd_mclk_div = 0x83e011c;
753 break;
754 }
755
756 case VO_OUTPUT_320x240_60: {
757 /* lcd clk config */
758 vdp_out_clk_sel = 0x6;
759 hd1_div_mod = 0x3;
760 lcd_mclk_div = 0x82aE4C3;
761 break;
762 }
763
764 case VO_OUTPUT_320x240_50: {
765 /* lcd clk config */
766 vdp_out_clk_sel = 0x6;
767 hd1_div_mod = 0x2;
768 lcd_mclk_div = 0x152306;
769 break;
770 }
771
772 case VO_OUTPUT_240x320_50: {
773 /* lcd clk config */
774 vdp_out_clk_sel = 0x6;
775 hd1_div_mod = 0x2;
776 lcd_mclk_div = 0x172dfd;
777 break;
778 }
779
780 case VO_OUTPUT_240x320_60: {
781 /* lcd clk config */
782 vdp_out_clk_sel = 0x6;
783 hd1_div_mod = 0x0;
784 lcd_mclk_div = 0x90c54;
785 break;
786 }
787
788 case VO_OUTPUT_800x600_50: {
789 /* lcd clk config */
790 vdp_out_clk_sel = 0x6;
791 hd1_div_mod = 0x0;
792 lcd_mclk_div = 0x39cc92;
793 break;
794 }
795
796 default: {
797 return;
798 }
799 }
800
801 sys_hal_lcd_mclk_div(lcd_mclk_div);
802
803 sys_hal_vo_out_clk_sel(vdp_out_clk_sel);
804 sys_hal_vo_hd1_div_mode(hd1_div_mod);
805
806 if ((intf_sync == VO_OUTPUT_800x600_60) ||
807 (intf_sync == VO_OUTPUT_1024x768_60) ||
808 (intf_sync == VO_OUTPUT_1280x1024_60) ||
809 (intf_sync == VO_OUTPUT_1366x768_60) ||
810 (intf_sync == VO_OUTPUT_1440x900_60) ||
811 (intf_sync == VO_OUTPUT_1280x800_60) ||
812 (intf_sync == VO_OUTPUT_1600x1200_60) ||
813 (intf_sync == VO_OUTPUT_1680x1050_60) ||
814 (intf_sync == VO_OUTPUT_1920x1200_60) ||
815 (intf_sync == VO_OUTPUT_640x480_60)) {
816 sys_hal_set_vo_s_pll_fbdiv(vo_dev, spll_fbdiv);
817 sys_hal_set_vo_s_pll_frac(vo_dev, spll_frac);
818
819 sys_hal_set_vo_s_pll_postdiv1(vo_dev, spll_postdiv1);
820 sys_hal_set_vo_s_pll_postdiv2(vo_dev, spll_postdiv2);
821 sys_hal_set_vo_s_pll_refdiv(vo_dev, spll_refdiv);
822 }
823 return;
824 }
825
vo_drv_set_dev_clk(vo_hal_dev vo_dev)826 hi_void vo_drv_set_dev_clk(vo_hal_dev vo_dev)
827 {
828 hi_u32 ppc_sel = 1; /* 1 ppc sel */
829
830 sys_hal_vo_hd1_ppc_sel(ppc_sel);
831
832 if (vo_dev == 0) {
833 vo_drv_set_uhd_clk(vo_dev, g_hal_dev_cfg[vo_dev].out_sync);
834 } else {
835 vo_drv_set_hd_clk(vo_dev, g_hal_dev_cfg[vo_dev].out_sync);
836 }
837
838 return;
839 }
840
vo_drv_get_dev_vtth(vo_hal_dev vo_dev)841 hi_u32 vo_drv_get_dev_vtth(vo_hal_dev vo_dev)
842 {
843 hi_u32 dev_vtth;
844
845 switch (g_hal_dev_cfg[vo_dev].out_sync) {
846 case VO_OUTPUT_3840x2160_60:
847 case VO_OUTPUT_3840x2160_50:
848 case VO_OUTPUT_4096x2160_60:
849 case VO_OUTPUT_4096x2160_50:
850 dev_vtth = 4 * VO_HD_VTTH_WATERLINE; /* 4 times of default */
851 break;
852 case VO_OUTPUT_2560x1600_60:
853 case VO_OUTPUT_3840x2160_24:
854 case VO_OUTPUT_3840x2160_25:
855 case VO_OUTPUT_3840x2160_30:
856 case VO_OUTPUT_4096x2160_24:
857 case VO_OUTPUT_4096x2160_25:
858 case VO_OUTPUT_4096x2160_30:
859 dev_vtth = 2 * VO_HD_VTTH_WATERLINE; /* 2 times of default */
860 break;
861 default:
862 dev_vtth = VO_HD_VTTH_WATERLINE;
863 }
864
865 return dev_vtth;
866 }
867
868 /* turn on clk */
vo_drv_set_all_crg_clk(hi_bool clk_en)869 hi_void vo_drv_set_all_crg_clk(hi_bool clk_en)
870 {
871 hi_bool vo_clk_en = clk_en;
872
873 sys_hal_vo_cfg_clk_en(vo_clk_en);
874 sys_hal_vo_apb_clk_en(vo_clk_en);
875 sys_hal_vo_bus_clk_en(vo_clk_en);
876 return;
877 }
878
vo_drv_get_dev_intf_type(vo_hal_dev vo_dev)879 hi_u32 vo_drv_get_dev_intf_type(vo_hal_dev vo_dev)
880 {
881 return g_hal_dev_cfg[vo_dev].intf_type;
882 }
883
vo_drv_set_cbm_bkg(hi_s32 vo_dev)884 void vo_drv_set_cbm_bkg(hi_s32 vo_dev)
885 {
886 hal_disp_bkcolor bkg;
887 hi_u32 yuv_bk_grd;
888 hal_dev_config *hal_dev_cfg = &g_hal_dev_cfg[vo_dev];
889 vo_intf_type intf_type;
890
891 intf_type = hal_dev_cfg->intf_type;
892
893 if ((VO_INTF_LCD & intf_type) ||
894 (VO_INTF_LCD_6BIT & intf_type) ||
895 (VO_INTF_LCD_8BIT & intf_type) ||
896 (VO_INTF_LCD_16BIT & intf_type) ||
897 (VO_INTF_LCD_18BIT & intf_type) ||
898 (VO_INTF_LCD_24BIT & intf_type) ||
899 (VO_INTF_MIPI & intf_type) ||
900 (VO_INTF_MIPI_SLAVE & intf_type)) {
901 bkg.bkg_y = rgb_r(hal_dev_cfg->bk_grd);
902 bkg.bkg_cb = rgb_g(hal_dev_cfg->bk_grd);
903 bkg.bkg_cr = rgb_b(hal_dev_cfg->bk_grd);
904 /* for 30bit register. */
905 bkg.bkg_y = bkg.bkg_y << 2; /* 2 to turn 8 to 10 value */
906 bkg.bkg_cb = bkg.bkg_cb << 2; /* 2 to turn 8 to 10 value */
907 bkg.bkg_cr = bkg.bkg_cr << 2; /* 2 to turn 8 to 10 value */
908 } else {
909 yuv_bk_grd = rgb_to_yuv_full(hal_dev_cfg->bk_grd);
910 bkg.bkg_y = yuv_y(yuv_bk_grd);
911 bkg.bkg_cb = yuv_u(yuv_bk_grd);
912 bkg.bkg_cr = yuv_v(yuv_bk_grd);
913 }
914
915 if (vo_dev == VO_DEV_DHD0) {
916 hal_cbm_set_cbm_bkg(HAL_CBMMIX1, &bkg);
917 } else if (vo_dev == VO_DEV_DHD1) {
918 hal_cbm_set_cbm_bkg(HAL_CBMMIX2, &bkg);
919 }
920 }
921
vo_drv_get_intf_property(hi_s32 vo_dev,hal_disp_syncinfo * sync_info,hal_disp_syncinv * inv)922 void vo_drv_get_intf_property(hi_s32 vo_dev, hal_disp_syncinfo *sync_info, hal_disp_syncinv *inv)
923 {
924 hal_dev_config *hal_dev_cfg = &g_hal_dev_cfg[vo_dev];
925
926 memcpy(sync_info, &g_sync_timing[hal_dev_cfg->out_sync], sizeof(hal_disp_syncinfo));
927 inv->hs_inv = sync_info->ihs ? 1 : 0;
928 inv->vs_inv = sync_info->ivs ? 1 : 0;
929 inv->dv_inv = sync_info->idv ? 1 : 0;
930 }
931
vo_drv_set_intf_hdmi_cfg(hi_s32 vo_dev,hal_disp_syncinfo * sync_info,hal_disp_syncinv * inv)932 void vo_drv_set_intf_hdmi_cfg(hi_s32 vo_dev, hal_disp_syncinfo *sync_info, hal_disp_syncinv *inv)
933 {
934 hal_dev_config *hal_dev_cfg = &g_hal_dev_cfg[vo_dev];
935 vo_intf_type intf_type;
936 hi_u32 hdmi_mode = 0;
937 const hi_bool hdmi_clk_en = 0x1;
938 const hi_u32 hd0_div_mod = 0x0;
939
940 intf_type = hal_dev_cfg->intf_type;
941
942 if ((VO_INTF_LCD & intf_type) ||
943 (VO_INTF_LCD_6BIT & intf_type) ||
944 (VO_INTF_LCD_8BIT & intf_type) ||
945 (VO_INTF_LCD_16BIT & intf_type) ||
946 (VO_INTF_LCD_18BIT & intf_type) ||
947 (VO_INTF_LCD_24BIT & intf_type) ||
948 (VO_INTF_MIPI & intf_type) ||
949 (VO_INTF_MIPI_SLAVE & intf_type)) {
950 hdmi_mode = 1;
951 } else {
952 hdmi_mode = 0;
953 }
954 sys_hal_vo_hdmi_clk_en(hdmi_clk_en);
955 sys_hal_vo_hd0_div_mode(vo_dev, hd0_div_mod);
956
957 if ((hal_dev_cfg->out_sync == VO_OUTPUT_576P50) ||
958 (hal_dev_cfg->out_sync == VO_OUTPUT_480P60)) {
959 inv->hs_inv = 1 - inv->hs_inv;
960 inv->vs_inv = 1 - inv->vs_inv;
961 }
962 hal_disp_set_hdmi_mode(vo_dev, hdmi_mode);
963 }
964
vo_drv_set_intf_bt1120_cfg(hi_s32 vo_dev,hal_disp_syncinfo * sync_info,hal_disp_syncinv * inv)965 void vo_drv_set_intf_bt1120_cfg(hi_s32 vo_dev, hal_disp_syncinfo *sync_info, hal_disp_syncinv *inv)
966 {
967 sys_hal_vo_hd_out_pctrl(HI_TRUE);
968 sys_hal_vo_bt_clk_sel(vo_dev);
969 sys_hal_vo_bt_clk_en(HI_TRUE);
970
971 hal_disp_set_intf_mux_sel(vo_dev, VO_INTF_BT1120);
972 hal_intf_bt_set_dfir_en(0x1);
973 }
974
vo_drv_set_intf_mipi_cfg(hi_s32 vo_dev,hal_disp_syncinfo * sync_info,hal_disp_syncinv * inv)975 void vo_drv_set_intf_mipi_cfg(hi_s32 vo_dev, hal_disp_syncinfo *sync_info, hal_disp_syncinv *inv)
976 {
977 hi_bool mipi_clk_en = 0x1;
978 hal_dev_config *hal_dev_cfg = &g_hal_dev_cfg[vo_dev];
979 U_INTF_LCD_CTRL LCD_CTRL;
980
981 sys_hal_vo_mipi_clk_en(mipi_clk_en);
982 sys_hal_vo_mipi_chn_sel(vo_dev);
983
984 hal_disp_set_intf_mux_sel(vo_dev, VO_INTF_MIPI);
985
986 LCD_CTRL.bits.hdmi_mode = 1;
987 hal_disp_set_intf_ctrl(hal_dev_cfg->intf_type, &(LCD_CTRL.u32));
988 hal_disp_set_intvsync_te_mode(vo_dev, HI_FALSE);
989 inv->hs_inv = 0;
990 inv->vs_inv = 0;
991 inv->dv_inv = 0;
992 }
vo_drv_set_intf_mipislave_cfg(hi_s32 vo_dev,hal_disp_syncinfo * sync_info,hal_disp_syncinv * inv)993 void vo_drv_set_intf_mipislave_cfg(hi_s32 vo_dev, hal_disp_syncinfo *sync_info, hal_disp_syncinv *inv)
994 {
995 hi_bool mipi_clk_en = 0x1;
996 hal_dev_config *hal_dev_cfg = &g_hal_dev_cfg[vo_dev];
997 U_INTF_LCD_CTRL LCD_CTRL;
998
999 sys_hal_vo_mipi_clk_en(mipi_clk_en);
1000 sys_hal_vo_mipi_chn_sel(vo_dev);
1001 hal_disp_set_intf_mux_sel(vo_dev, VO_INTF_MIPI);
1002
1003 LCD_CTRL.bits.hdmi_mode = 1;
1004 hal_disp_set_intf_ctrl(hal_dev_cfg->intf_type, &(LCD_CTRL.u32));
1005 hal_disp_set_intvsync_te_mode(vo_dev, HI_TRUE);
1006 inv->hs_inv = 0;
1007 inv->vs_inv = 0;
1008 inv->dv_inv = 0;
1009 }
1010
vo_drv_set_intf_cfg(hi_s32 vo_dev,hal_disp_syncinfo * sync_info,hal_disp_syncinv * inv)1011 void vo_drv_set_intf_cfg(hi_s32 vo_dev, hal_disp_syncinfo *sync_info, hal_disp_syncinv *inv)
1012 {
1013 hal_dev_config *hal_dev_cfg = &g_hal_dev_cfg[vo_dev];
1014
1015 if (VO_INTF_HDMI & hal_dev_cfg->intf_type) {
1016 vo_drv_set_intf_hdmi_cfg(vo_dev, sync_info, inv);
1017 }
1018
1019 if (VO_INTF_BT1120 & hal_dev_cfg->intf_type) {
1020 vo_drv_set_intf_bt1120_cfg(vo_dev, sync_info, inv);
1021 }
1022
1023 if (VO_INTF_MIPI & hal_dev_cfg->intf_type) {
1024 vo_drv_set_intf_mipi_cfg(vo_dev, sync_info, inv);
1025 }
1026
1027 if (VO_INTF_MIPI_SLAVE & hal_dev_cfg->intf_type) {
1028 vo_drv_set_intf_mipislave_cfg(vo_dev, sync_info, inv);
1029 }
1030 }
1031
vo_drv_set_dev_multichn(hi_s32 vo_dev)1032 void vo_drv_set_dev_multichn(hi_s32 vo_dev)
1033 {
1034 hal_multi_chn multi_chn_en;
1035
1036 multi_chn_en = HAL_MULTICHN_EN_1P1C;
1037 hal_disp_set_dev_multi_chn_en(vo_dev, multi_chn_en);
1038 }
vo_drv_set_dev_clip_by_intf(hi_s32 vo_dev)1039 void vo_drv_set_dev_clip_by_intf(hi_s32 vo_dev)
1040 { /* set clip */
1041 if (VO_INTF_BT1120 & g_hal_dev_cfg[vo_dev].intf_type) {
1042 const hal_disp_clip clip_data = { 0x40, 0x40, 0x40, 0x3ac, 0x3c0, 0x3c0 }; /* clip register config */
1043 hal_disp_set_intf_clip(VO_INTF_BT1120, HI_TRUE, &clip_data);
1044 }
1045
1046 if (VO_INTF_BT656 & g_hal_dev_cfg[vo_dev].intf_type) {
1047 const hal_disp_clip clip_data = { 0x40, 0x40, 0x40, 0x3ac, 0x3c0, 0x3c0 }; /* clip register config */
1048 hal_disp_set_intf_clip(VO_INTF_BT656, HI_TRUE, &clip_data);
1049 }
1050 }
1051
vo_drv_set_dev_int_mode(hi_s32 vo_dev,hal_disp_syncinfo * sync_info)1052 void vo_drv_set_dev_int_mode(hi_s32 vo_dev, hal_disp_syncinfo *sync_info)
1053 {
1054 vo_int_mode int_mode;
1055
1056 if (sync_info->iop == 0) {
1057 int_mode = VO_INT_MODE_FIELD;
1058 } else {
1059 int_mode = VO_INT_MODE_FRAME;
1060 }
1061 vo_drv_int_set_mode(vo_dev, int_mode);
1062 vo_drv_int_reg_up_mode(vo_dev, int_mode);
1063 }
1064
vo_drv_open(hi_s32 vo_dev)1065 hi_void vo_drv_open(hi_s32 vo_dev)
1066 {
1067 hal_disp_syncinfo sync_info;
1068 hi_u16 vtth_line;
1069 hal_disp_syncinv inv = {0};
1070
1071 vo_drv_set_all_crg_clk(HI_TRUE);
1072 hal_disp_set_intf_enable(vo_dev, HI_FALSE);
1073
1074 sys_hal_vo_dev_clk_en(0, HI_TRUE);
1075 sys_hal_vo_dev_clk_en(1, HI_TRUE);
1076
1077 vo_drv_set_cbm_bkg(vo_dev);
1078
1079 /* set interface property */
1080 vo_drv_get_intf_property(vo_dev, &sync_info, &inv);
1081
1082 vo_drv_set_intf_cfg(vo_dev, &sync_info, &inv);
1083
1084 hal_disp_set_intf_sync(vo_dev, &sync_info, &inv);
1085
1086 vo_drv_set_dev_multichn(vo_dev);
1087
1088 vo_drv_set_dev_clip_by_intf(vo_dev);
1089
1090 vo_drv_set_dev_int_mode(vo_dev, &sync_info);
1091
1092 vtth_line = sync_info.vact + sync_info.vfb + sync_info.vbb - vo_drv_get_dev_vtth(vo_dev);
1093 hal_disp_set_vt_thd(vo_dev, vtth_line);
1094
1095 hal_disp_set_intf_enable(vo_dev, HI_TRUE);
1096 vo_drv_dev_int_enable(vo_dev, HI_TRUE);
1097 hal_disp_set_reg_up(vo_dev);
1098 g_hal_dev_cfg[vo_dev].enable = HI_TRUE;
1099
1100 return;
1101 }
1102
vo_drv_close(hi_s32 vo_dev)1103 hi_void vo_drv_close(hi_s32 vo_dev)
1104 {
1105 hi_u32 i;
1106
1107 hal_disp_set_intf_enable(vo_dev, HI_FALSE);
1108 hal_disp_set_reg_up(vo_dev);
1109
1110 udelay(25 * 1000); /* delaye 25x1000 us */
1111
1112 g_hal_dev_cfg[vo_dev].enable = HI_FALSE;
1113
1114 for (i = 0; i < VO_DEV_MAX_NUM; i++) {
1115 if (g_hal_dev_cfg[vo_dev].enable) {
1116 break;
1117 }
1118 }
1119
1120 if (i == VO_DEV_MAX_NUM) {
1121 vo_drv_set_all_crg_clk(HI_FALSE);
1122 }
1123
1124 return;
1125 }
1126
vo_drv_default_setting(hi_void)1127 hi_void vo_drv_default_setting(hi_void)
1128 {
1129 hi_u32 i;
1130
1131 for (i = HAL_DISP_LAYER_VHD0; i <= HAL_DISP_LAYER_VHD1; i++) {
1132 hal_layer_set_layer_galpha(i, 255); /* 255 max alpha */
1133 }
1134
1135 /* outstanding */
1136 for (i = HAL_DISP_LAYER_VHD0; i <= HAL_DISP_LAYER_VHD1; i++) {
1137 vo_drv_layer_enable(i, HI_FALSE);
1138 }
1139
1140 return;
1141 }
1142
vo_drv_func_get_cvfir_pq_cfg(vo_zme_ds_info * ds_info,vo_zme_mode zme_mode,vo_zme_comm_pq_cfg * comm_pq_cfg)1143 hi_void vo_drv_func_get_cvfir_pq_cfg(vo_zme_ds_info *ds_info, vo_zme_mode zme_mode,
1144 vo_zme_comm_pq_cfg *comm_pq_cfg)
1145 {
1146 hi_u32 zme_vprec;
1147
1148 /* the zme num is from algorithm, not magic num */
1149 if (zme_mode == VO_ZME_TYP) {
1150 zme_vprec = ds_info->zme_vprec;
1151 comm_pq_cfg->vluma_offset = 0;
1152 comm_pq_cfg->vchroma_offset = 0;
1153 comm_pq_cfg->vbluma_offset = MIN_OFFSET * (hi_s32)zme_vprec / 2;
1154 comm_pq_cfg->vbchroma_offset = MIN_OFFSET * (hi_s32)zme_vprec / 2;
1155 comm_pq_cfg->vl_flatdect_mode = 1;
1156 comm_pq_cfg->vl_coringadj_en = 1;
1157 comm_pq_cfg->vl_gain = 32;
1158 comm_pq_cfg->vl_coring = 16;
1159 comm_pq_cfg->vc_flatdect_mode = 1;
1160 comm_pq_cfg->vc_coringadj_en = 1;
1161 comm_pq_cfg->vc_gain = 32;
1162 comm_pq_cfg->vc_coring = 16;
1163 comm_pq_cfg->lhfir_offset = 0;
1164 comm_pq_cfg->chfir_offset = 0;
1165 comm_pq_cfg->hl_flatdect_mode = 1;
1166 comm_pq_cfg->hl_coringadj_en = 1;
1167 comm_pq_cfg->hl_gain = 32;
1168 comm_pq_cfg->hl_coring = 16;
1169 comm_pq_cfg->hc_flatdect_mode = 1;
1170 comm_pq_cfg->hc_coringadj_en = 1;
1171 comm_pq_cfg->hc_gain = 32;
1172 comm_pq_cfg->hc_coring = 16;
1173 }
1174 }
1175
vo_drv_set_layer_cvfir_mode(hi_u32 layer,vo_zme_mode zme_mode,const vdp_v1_cvfir_cfg * cfg)1176 static hi_void vo_drv_set_layer_cvfir_mode(hi_u32 layer, vo_zme_mode zme_mode, const vdp_v1_cvfir_cfg *cfg)
1177 {
1178 hi_u32 vzme_ck_gt_en;
1179 hi_u32 out_pro;
1180 hi_u32 out_fmt;
1181 hi_u32 out_height;
1182 hi_u32 cvfir_en;
1183 hi_u32 cvmid_en;
1184 hi_u32 cvfir_mode;
1185 hi_u32 vratio;
1186 hi_u32 vchroma_offset;
1187 hi_u32 vbchroma_offset;
1188 vo_zme_ds_info ds_info = {0};
1189 vo_zme_comm_pq_cfg comm_pq_cfg = {0};
1190
1191 ds_info.zme_vprec = ZME_VPREC;
1192 ds_info.zme_hprec = ZME_HPREC;
1193
1194 vzme_ck_gt_en = cfg->ck_gt_en;
1195 cvfir_en = cfg->cvfir_en;
1196 cvfir_mode = cfg->cvfir_mode;
1197 cvmid_en = cfg->cvmid_en;
1198
1199 out_pro = cfg->out_pro;
1200 out_fmt = cfg->out_fmt;
1201 out_height = cfg->in_height;
1202 vratio = ds_info.zme_vprec;
1203
1204 vo_drv_func_get_cvfir_pq_cfg(&ds_info, zme_mode, &comm_pq_cfg);
1205
1206 vchroma_offset = comm_pq_cfg.vchroma_offset;
1207 vbchroma_offset = comm_pq_cfg.vbchroma_offset;
1208
1209 hal_video_cvfir_set_out_height(layer, out_height);
1210 hal_video_cvfir_set_out_fmt(layer, out_fmt);
1211 hal_video_cvfir_set_out_pro(layer, out_pro);
1212 hal_video_cvfir_set_vzme_ck_gt_en(layer, vzme_ck_gt_en);
1213
1214 hal_video_cvfir_set_cvfir_en(layer, cvfir_en);
1215 hal_video_cvfir_set_cvmid_en(layer, cvmid_en);
1216 hal_video_cvfir_set_cvfir_mode(layer, cvfir_mode);
1217 hal_video_cvfir_set_vratio(layer, vratio);
1218
1219 hal_video_cvfir_set_v_chroma_offset(layer, vchroma_offset);
1220 hal_video_cvfir_set_vb_chroma_offset(layer, vbchroma_offset);
1221 }
1222
vo_vid_set_zme_enable(hi_u32 layer,const vdp_vid_ip_cfg * vid_cfg)1223 hi_void vo_vid_set_zme_enable(hi_u32 layer, const vdp_vid_ip_cfg *vid_cfg)
1224 {
1225 /* the numbers is from algorithm, not magic numbers */
1226 vdp_v1_cvfir_cfg cvfir_cfg;
1227 cvfir_cfg.hfir_order = 0;
1228 cvfir_cfg.lhfir_en = 0;
1229 cvfir_cfg.chfir_en = 0;
1230 cvfir_cfg.lhmid_en = 0;
1231 cvfir_cfg.chmid_en = 0;
1232 cvfir_cfg.lhfir_mode = 0;
1233 cvfir_cfg.chfir_mode = 0;
1234 cvfir_cfg.hl_shootctrl_en = 0;
1235 cvfir_cfg.hl_shootctrl_mode = 0;
1236 cvfir_cfg.hc_shootctrl_en = 0;
1237 cvfir_cfg.hc_shootctrl_mode = 0;
1238 cvfir_cfg.lvfir_en = 0;
1239 cvfir_cfg.lvmid_en = 0;
1240 cvfir_cfg.lvfir_mode = 0;
1241 cvfir_cfg.vl_shootctrl_en = 0;
1242 cvfir_cfg.vl_shootctrl_mode = 0;
1243 cvfir_cfg.vc_shootctrl_en = 0;
1244 cvfir_cfg.vc_shootctrl_mode = 0;
1245
1246 /* CVFIR */
1247 cvfir_cfg.ck_gt_en = 0;
1248 cvfir_cfg.cvfir_en = 1;
1249 cvfir_cfg.cvmid_en = 0;
1250 cvfir_cfg.cvfir_mode = 0;
1251 cvfir_cfg.out_pro = VDP_RMODE_PROGRESSIVE;
1252 cvfir_cfg.out_fmt = VDP_PROC_FMT_SP_422;
1253 cvfir_cfg.in_width = vid_cfg->vid_iw;
1254 cvfir_cfg.in_height = vid_cfg->vid_ih;
1255 cvfir_cfg.out_width = vid_cfg->vid_ow;
1256 cvfir_cfg.out_height = vid_cfg->vid_oh;
1257 vo_drv_set_layer_cvfir_mode(layer, VO_ZME_TYP, &cvfir_cfg);
1258 }
1259
vo_drv_get_csc_matrix(hal_csc_mode csc_mode,const vo_csc_coef ** csc_tmp)1260 hi_s32 vo_drv_get_csc_matrix(hal_csc_mode csc_mode, const vo_csc_coef **csc_tmp)
1261 {
1262 switch (csc_mode) {
1263 case HAL_CSC_MODE_BT601_TO_BT601:
1264 case HAL_CSC_MODE_BT709_TO_BT709:
1265 case HAL_CSC_MODE_RGB_TO_RGB:
1266 *csc_tmp = &g_csc_init;
1267 break;
1268 case HAL_CSC_MODE_BT709_TO_BT601:
1269 *csc_tmp = &g_csc_yuv_to_yuv_709_601;
1270 break;
1271 case HAL_CSC_MODE_BT601_TO_BT709:
1272 *csc_tmp = &g_csc_yuv_to_yuv_601_709;
1273 break;
1274 case HAL_CSC_MODE_BT601_TO_RGB_PC:
1275 *csc_tmp = &g_csc_yuv601_to_rgb_pc;
1276 break;
1277 case HAL_CSC_MODE_BT709_TO_RGB_PC:
1278 *csc_tmp = &g_csc_yuv709_to_rgb_pc;
1279 break;
1280 case HAL_CSC_MODE_RGB_TO_BT601_PC:
1281 *csc_tmp = &g_csc_rgb_to_yuv601_pc;
1282 break;
1283 case HAL_CSC_MODE_RGB_TO_BT709_PC:
1284 *csc_tmp = &g_csc_rgb_to_yuv709_pc;
1285 break;
1286 case HAL_CSC_MODE_RGB_TO_BT601_TV:
1287 *csc_tmp = &g_csc_rgb_to_yuv601_tv;
1288 break;
1289 case HAL_CSC_MODE_RGB_TO_BT709_TV:
1290 *csc_tmp = &g_csc_rgb_to_yuv709_tv;
1291 break;
1292 default:
1293 return HI_FAILURE;
1294 }
1295 return HI_SUCCESS;
1296 }
1297
vo_drv_get_hal_cscvalue(const vo_csc * csc,hal_csc_value * csc_value)1298 hi_void vo_drv_get_hal_cscvalue(const vo_csc *csc, hal_csc_value *csc_value)
1299 {
1300 csc_value->luma = (hi_s32)csc->luma * 64 / 100 - 32; /* x64/100 -32 to adjust the value */
1301 csc_value->cont = ((hi_s32)csc->contrast - 50) * 2 + 100; /* -50) * 2 + 100 to adjust the value */
1302 csc_value->hue = (hi_s32)csc->hue * 60 / 100; /* x60/100 to adjust the value */
1303 csc_value->satu = ((hi_s32)csc->satuature - 50) * 2 + 100; /* -50) * 2 + 100 to adjust the value */
1304 }
1305
vo_drv_set_csc_coef_y2r(const hal_csc_value * csc_value,const vo_csc_coef * csc_tmp,vo_csc_coef * csc_coef)1306 hi_void vo_drv_set_csc_coef_y2r(const hal_csc_value *csc_value, const vo_csc_coef *csc_tmp, vo_csc_coef *csc_coef)
1307 {
1308 hi_s32 luma;
1309 hi_s32 contrast;
1310 hi_s32 hue;
1311 hi_s32 satu;
1312
1313 luma = csc_value->luma;
1314 contrast = csc_value->cont;
1315 hue = csc_value->hue;
1316 satu = csc_value->satu;
1317
1318 /* 100 and 1000 is to adjust the coef */
1319 csc_coef->csc_coef00 = (contrast * csc_tmp->csc_coef00) / 100;
1320 csc_coef->csc_coef01 = (contrast * satu * ((csc_tmp->csc_coef01 * g_cos_table[hue] -
1321 csc_tmp->csc_coef02 * g_sin_table[hue]) / 1000)) / 10000;
1322 csc_coef->csc_coef02 = (contrast * satu * ((csc_tmp->csc_coef01 * g_sin_table[hue] +
1323 csc_tmp->csc_coef02 * g_cos_table[hue]) / 1000)) / 10000;
1324 csc_coef->csc_coef10 = (contrast * csc_tmp->csc_coef10) / 100;
1325 csc_coef->csc_coef11 = (contrast * satu * ((csc_tmp->csc_coef11 * g_cos_table[hue] -
1326 csc_tmp->csc_coef12 * g_sin_table[hue]) / 1000)) / 10000;
1327 csc_coef->csc_coef12 = (contrast * satu * ((csc_tmp->csc_coef11 * g_sin_table[hue] +
1328 csc_tmp->csc_coef12 * g_cos_table[hue]) / 1000)) / 10000;
1329 csc_coef->csc_coef20 = (contrast * csc_tmp->csc_coef20) / 100;
1330 csc_coef->csc_coef21 = (contrast * satu * ((csc_tmp->csc_coef21 * g_cos_table[hue] -
1331 csc_tmp->csc_coef22 * g_sin_table[hue]) / 1000)) / 10000;
1332 csc_coef->csc_coef22 = (contrast * satu * ((csc_tmp->csc_coef21 * g_sin_table[hue] +
1333 csc_tmp->csc_coef22 * g_cos_table[hue]) / 1000)) / 10000;
1334 csc_coef->csc_in_dc0 += (contrast != 0) ? (luma * 100 / contrast) : luma * 100;
1335 }
1336
vo_drv_set_csc_coef_r2y(const hal_csc_value * csc_value,const vo_csc_coef * csc_tmp,vo_csc_coef * csc_coef)1337 hi_void vo_drv_set_csc_coef_r2y(const hal_csc_value *csc_value, const vo_csc_coef *csc_tmp, vo_csc_coef *csc_coef)
1338 {
1339 hi_s32 luma;
1340 hi_s32 contrast;
1341 hi_s32 hue;
1342 hi_s32 satu;
1343
1344 luma = csc_value->luma;
1345 contrast = csc_value->cont;
1346 hue = csc_value->hue;
1347 satu = csc_value->satu;
1348 /* 100 and 1000 is to adjust the coef */
1349 csc_coef->csc_coef00 = (contrast * csc_tmp->csc_coef00) / 100;
1350 csc_coef->csc_coef01 = (contrast * csc_tmp->csc_coef01) / 100;
1351 csc_coef->csc_coef02 = (contrast * csc_tmp->csc_coef02) / 100;
1352 csc_coef->csc_coef10 = (contrast * satu * ((csc_tmp->csc_coef10 * g_cos_table[hue] +
1353 csc_tmp->csc_coef20 * g_sin_table[hue]) / 1000)) / 10000;
1354 csc_coef->csc_coef11 = (contrast * satu * ((csc_tmp->csc_coef11 * g_cos_table[hue] +
1355 csc_tmp->csc_coef21 * g_sin_table[hue]) / 1000)) / 10000;
1356 csc_coef->csc_coef12 = (contrast * satu * ((csc_tmp->csc_coef12 * g_cos_table[hue] +
1357 csc_tmp->csc_coef22 * g_sin_table[hue]) / 1000)) / 10000;
1358 csc_coef->csc_coef20 = (contrast * satu * ((csc_tmp->csc_coef20 * g_cos_table[hue] -
1359 csc_tmp->csc_coef10 * g_sin_table[hue]) / 1000)) / 10000;
1360 csc_coef->csc_coef21 = (contrast * satu * ((csc_tmp->csc_coef21 * g_cos_table[hue] -
1361 csc_tmp->csc_coef11 * g_sin_table[hue]) / 1000)) / 10000;
1362 csc_coef->csc_coef22 = (contrast * satu * ((csc_tmp->csc_coef22 * g_cos_table[hue] -
1363 csc_tmp->csc_coef12 * g_sin_table[hue]) / 1000)) / 10000;
1364 csc_coef->csc_out_dc0 += luma;
1365 }
1366
vo_drv_calc_csc_matrix(const vo_csc * csc,hal_csc_mode csc_mode,vo_csc_coef * cst_coef)1367 hi_void vo_drv_calc_csc_matrix(const vo_csc *csc, hal_csc_mode csc_mode, vo_csc_coef *cst_coef)
1368 {
1369 const vo_csc_coef *csc_tmp = HI_NULL;
1370 hi_s32 ret;
1371 hal_csc_value csc_value = {0};
1372
1373 vo_drv_get_hal_cscvalue(csc, &csc_value);
1374
1375 ret = vo_drv_get_csc_matrix(csc_mode, &csc_tmp);
1376 if (ret != HI_SUCCESS) {
1377 return;
1378 }
1379
1380 cst_coef->csc_in_dc0 = csc_tmp->csc_in_dc0;
1381 cst_coef->csc_in_dc1 = csc_tmp->csc_in_dc1;
1382 cst_coef->csc_in_dc2 = csc_tmp->csc_in_dc2;
1383 cst_coef->csc_out_dc0 = csc_tmp->csc_out_dc0;
1384 cst_coef->csc_out_dc1 = csc_tmp->csc_out_dc1;
1385 cst_coef->csc_out_dc2 = csc_tmp->csc_out_dc2;
1386
1387 if ((csc_mode == HAL_CSC_MODE_BT601_TO_RGB_PC) || (csc_mode == HAL_CSC_MODE_BT709_TO_RGB_PC) ||
1388 (csc_mode == HAL_CSC_MODE_BT601_TO_RGB_TV) || (csc_mode == HAL_CSC_MODE_BT709_TO_RGB_TV)) {
1389 vo_drv_set_csc_coef_y2r(&csc_value, csc_tmp, cst_coef);
1390 } else {
1391 vo_drv_set_csc_coef_r2y(&csc_value, csc_tmp, cst_coef);
1392 }
1393 return;
1394 }
1395
vo_drv_get_hal_cscmode(vo_csc_matrix csc_matrix,hal_csc_mode * csc_mode)1396 hi_void vo_drv_get_hal_cscmode(vo_csc_matrix csc_matrix, hal_csc_mode *csc_mode)
1397 {
1398 switch (csc_matrix) {
1399 case VO_CSC_MATRIX_IDENTITY:
1400 *csc_mode = HAL_CSC_MODE_BT601_TO_BT601;
1401 break;
1402
1403 case VO_CSC_MATRIX_BT601_TO_BT709:
1404 *csc_mode = HAL_CSC_MODE_BT601_TO_BT709;
1405 break;
1406
1407 case VO_CSC_MATRIX_BT709_TO_BT601:
1408 *csc_mode = HAL_CSC_MODE_BT709_TO_BT601;
1409 break;
1410
1411 case VO_CSC_MATRIX_BT601_TO_RGB_PC:
1412 *csc_mode = HAL_CSC_MODE_BT601_TO_RGB_PC;
1413 break;
1414
1415 case VO_CSC_MATRIX_BT709_TO_RGB_PC:
1416 *csc_mode = HAL_CSC_MODE_BT709_TO_RGB_PC;
1417 break;
1418
1419 case VO_CSC_MATRIX_RGB_TO_BT601_PC:
1420 *csc_mode = HAL_CSC_MODE_RGB_TO_BT601_PC;
1421 break;
1422
1423 case VO_CSC_MATRIX_RGB_TO_BT709_PC:
1424 *csc_mode = HAL_CSC_MODE_RGB_TO_BT709_PC;
1425 break;
1426
1427 case VO_CSC_MATRIX_RGB_TO_BT601_TV:
1428 *csc_mode = HAL_CSC_MODE_RGB_TO_BT601_TV;
1429 break;
1430
1431 case VO_CSC_MATRIX_RGB_TO_BT709_TV:
1432 *csc_mode = HAL_CSC_MODE_RGB_TO_BT709_TV;
1433 break;
1434
1435 default:
1436 *csc_mode = HAL_CSC_MODE_BT601_TO_BT601;
1437 break;
1438 }
1439 }
1440
vo_drv_set_csc_coef(hal_disp_layer layer,const vo_csc * csc,const csc_coef_param * coef_param)1441 hi_s32 vo_drv_set_csc_coef(hal_disp_layer layer, const vo_csc *csc, const csc_coef_param *coef_param)
1442 {
1443 vo_csc_coef coef;
1444 hal_csc_mode csc_mode = HAL_CSC_MODE_RGB_TO_BT601_TV;
1445
1446 const hi_u32 pre = 8; /* 8 pre value */
1447 const hi_u32 dc_pre = 4; /* 4 dc pre value */
1448
1449 vo_drv_get_hal_cscmode(csc->csc_matrix, &csc_mode);
1450
1451 vo_drv_calc_csc_matrix(csc, csc_mode, &coef);
1452
1453 coef.new_csc_clip_max = GFX_CSC_CLIP_MAX;
1454 coef.new_csc_clip_min = GFX_CSC_CLIP_MIN;
1455 coef.new_csc_scale2p = GFX_CSC_SCALE;
1456
1457 /* x1024 / 1000 to adjust coef */
1458 coef.csc_coef00 = (hi_s32)pre * coef.csc_coef00 * 1024 / 1000;
1459 coef.csc_coef01 = (hi_s32)pre * coef.csc_coef01 * 1024 / 1000;
1460 coef.csc_coef02 = (hi_s32)pre * coef.csc_coef02 * 1024 / 1000;
1461 coef.csc_coef10 = (hi_s32)pre * coef.csc_coef10 * 1024 / 1000;
1462 coef.csc_coef11 = (hi_s32)pre * coef.csc_coef11 * 1024 / 1000;
1463 coef.csc_coef12 = (hi_s32)pre * coef.csc_coef12 * 1024 / 1000;
1464 coef.csc_coef20 = (hi_s32)pre * coef.csc_coef20 * 1024 / 1000;
1465 coef.csc_coef21 = (hi_s32)pre * coef.csc_coef21 * 1024 / 1000;
1466 coef.csc_coef22 = (hi_s32)pre * coef.csc_coef22 * 1024 / 1000;
1467
1468 coef.csc_in_dc0 = (hi_s32)dc_pre * coef.csc_in_dc0;
1469 coef.csc_in_dc1 = (hi_s32)dc_pre * coef.csc_in_dc1;
1470 coef.csc_in_dc2 = (hi_s32)dc_pre * coef.csc_in_dc2;
1471
1472 coef.csc_out_dc0 = (hi_s32)dc_pre * coef.csc_out_dc0;
1473 coef.csc_out_dc1 = (hi_s32)dc_pre * coef.csc_out_dc1;
1474 coef.csc_out_dc2 = (hi_s32)dc_pre * coef.csc_out_dc2;
1475
1476 hal_layer_set_csc_coef(layer, &coef);
1477
1478 return HI_SUCCESS;
1479 }
1480
1481