Lines Matching full:operand
89 void AssemblerAarch64::Ldp(const Register &rt, const Register &rt2, const MemoryOperand &operand) in Ldp() argument
92 if (operand.IsImmediateOffset()) { in Ldp()
93 switch (operand.GetAddrMode()) { in Ldp()
107 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp()
114 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldp()
121 void AssemblerAarch64::Stp(const Register &rt, const Register &rt2, const MemoryOperand &operand) in Stp() argument
124 if (operand.IsImmediateOffset()) { in Stp()
125 switch (operand.GetAddrMode()) { in Stp()
139 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp()
146 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Stp()
153 …blerAarch64::Ldp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand) in Ldp() argument
156 if (operand.IsImmediateOffset()) { in Ldp()
157 switch (operand.GetAddrMode()) { in Ldp()
170 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp()
189 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId()); in Ldp()
196 …blerAarch64::Stp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand) in Stp() argument
199 if (operand.IsImmediateOffset()) { in Stp()
200 switch (operand.GetAddrMode()) { in Stp()
213 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp()
232 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId()); in Stp()
265 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand, Scale scale) in Ldr() argument
268 uint32_t op = GetOpcodeOfLdr(operand, scale); in Ldr()
269 if (operand.IsImmediateOffset()) { in Ldr()
270 uint64_t imm = GetImmOfLdr(operand, scale, regX); in Ldr()
271 bool isSigned = operand.GetAddrMode() != AddrMode::OFFSET; in Ldr()
274 | Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldr()
277 ASSERT(operand.GetExtendOption() != Extend::NO_EXTEND); in Ldr()
278 uint32_t shift = GetShiftOfLdr(operand, scale, regX); in Ldr()
279 Register rm = operand.GetRegisterOffset(); in Ldr()
280 Register rn = operand.GetRegBase(); in Ldr()
282 (operand.GetExtendOption() << LDR_STR_Extend_LOWBITS) & LDR_STR_Extend_MASK; in Ldr()
291 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand) in Ldr() argument
293 Ldr(rt, operand, Scale::Q); in Ldr()
296 void AssemblerAarch64::Ldrh(const Register &rt, const MemoryOperand &operand) in Ldrh() argument
299 Ldr(rt, operand, Scale::H); in Ldrh()
302 void AssemblerAarch64::Ldrb(const Register &rt, const MemoryOperand &operand) in Ldrb() argument
305 Ldr(rt, operand, Scale::B); in Ldrb()
308 void AssemblerAarch64::Str(const Register &rt, const MemoryOperand &operand) in Str() argument
313 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Str()
314 if (operand.IsImmediateOffset()) { in Str()
315 switch (operand.GetAddrMode()) { in Str()
336 | Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Str()
343 void AssemblerAarch64::Ldur(const Register &rt, const MemoryOperand &operand) in Ldur() argument
347 ASSERT(operand.IsImmediateOffset()); in Ldur()
348 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldur()
351 | Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldur()
355 void AssemblerAarch64::Stur(const Register &rt, const MemoryOperand &operand) in Stur() argument
359 ASSERT(operand.IsImmediateOffset()); in Stur()
360 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stur()
363 | Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Stur()
448 Add(rd, rm, Operand(Immediate(0))); in Mov()
450 Orr(rd, Register(Zero), Operand(rm)); in Mov()
619 …firstshift = (tz / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate in EmitMovInstruct()
621 …lastshift = ((63 - lz) / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate in EmitMovInstruct()
634 … firstshift += 16; // 16 : 16 means the operand of MOVK is 16 bits Immediate in EmitMovInstruct()
683 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const Operand &operand) in Orr() argument
685 ASSERT(operand.IsShifted()); in Orr()
686 BitWiseOpShift(ORR_Shift, rd, rn, operand); in Orr()
689 void AssemblerAarch64::And(const Register &rd, const Register &rn, const Operand &operand) in And() argument
691 ASSERT(operand.IsShifted()); in And()
692 BitWiseOpShift(AND_Shift, rd, rn, operand); in And()
695 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const Operand &operand) in Ands() argument
697 ASSERT(operand.IsShifted()); in Ands()
698 BitWiseOpShift(ANDS_Shift, rd, rn, operand); in Ands()
707 …4::BitWiseOpShift(BitwiseOpCode op, const Register &rd, const Register &rn, const Operand &operand) in BitWiseOpShift() argument
709 …uint32_t shift_field = (operand.GetShiftOption() << BITWISE_OP_Shift_LOWBITS) & BITWISE_OP_Shift_M… in BitWiseOpShift()
710 …uint32_t shift_amount = (operand.GetShiftAmount() << BITWISE_OP_ShiftAmount_LOWBITS) & BITWISE_OP_… in BitWiseOpShift()
711 uint32_t code = Sf(!rd.IsW()) | op | shift_field | Rm(operand.Reg().GetId()) in BitWiseOpShift()
775 void AssemblerAarch64::Add(const Register &rd, const Register &rn, const Operand &operand) in Add() argument
777 if (operand.IsImmediate()) { in Add()
778 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Add()
785 if (operand.IsShifted()) { in Add()
786 AddSubReg(ADD_Shift, rd, rn, false, operand); in Add()
788 AddSubReg(ADD_Extend, rd, rn, false, operand); in Add()
793 void AssemblerAarch64::Adds(const Register &rd, const Register &rn, const Operand &operand) in Adds() argument
795 if (operand.IsImmediate()) { in Adds()
796 AddSubImm(ADD_Imm, rd, rn, true, operand.ImmediateValue()); in Adds()
798 if (operand.IsShifted()) { in Adds()
799 AddSubReg(ADD_Shift, rd, rn, true, operand); in Adds()
801 AddSubReg(ADD_Extend, rd, rn, true, operand); in Adds()
806 void AssemblerAarch64::Sub(const Register &rd, const Register &rn, const Operand &operand) in Sub() argument
808 if (operand.IsImmediate()) { in Sub()
809 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Sub()
816 if (operand.IsShifted()) { in Sub()
817 AddSubReg(SUB_Shift, rd, rn, false, operand); in Sub()
819 AddSubReg(SUB_Extend, rd, rn, false, operand); in Sub()
824 void AssemblerAarch64::Subs(const Register &rd, const Register &rn, const Operand &operand) in Subs() argument
826 if (operand.IsImmediate()) { in Subs()
827 AddSubImm(SUB_Imm, rd, rn, true, operand.ImmediateValue()); in Subs()
829 if (operand.IsShifted()) { in Subs()
830 AddSubReg(SUB_Shift, rd, rn, true, operand); in Subs()
832 AddSubReg(SUB_Extend, rd, rn, true, operand); in Subs()
869 bool setFlags, const Operand &operand) in AddSubReg() argument
873 if (operand.IsShifted()) { in AddSubReg()
874 … uint32_t shift_field = ((operand.GetShiftOption()) << ADD_SUB_Shift_LOWBITS) & ADD_SUB_Shift_MASK; in AddSubReg()
875 …uint32_t shift_amount = ((operand.GetShiftAmount()) << ADD_SUB_ShiftAmount_LOWBITS) & ADD_SUB_Shif… in AddSubReg()
877 code = Sf(!rd.IsW()) | op | flags_field |shift_field | Rm(operand.Reg().GetId()) in AddSubReg()
882 (operand.GetExtendOption() << ADD_SUB_ExtendOption_LOWBITS) & ADD_SUB_ExtendOption_MASK; in AddSubReg()
883 …uint32_t extend_shift = (operand.GetShiftAmount() << ADD_SUB_ExtendShift_LOWBITS) & ADD_SUB_Extend… in AddSubReg()
884 code = Sf(!rd.IsW()) | op | flags_field | Rm(operand.Reg().GetId()) | extend_field in AddSubReg()
890 void AssemblerAarch64::Cmp(const Register &rd, const Operand &operand) in Cmp() argument
892 Subs(Register(Zero, rd.GetType()), rd, operand); in Cmp()
895 void AssemblerAarch64::CMov(const Register &rd, const Register &rn, const Operand &operand, Conditi… in CMov() argument
897 ASSERT(!operand.IsImmediate()); in CMov()
899 …uint32_t code = Sf(!rd.IsW()) | CSEL | Rm(operand.Reg().GetId()) | cond_field | Rn(rn.GetId()) | R… in CMov()
1142 uint64_t AssemblerAarch64::GetImmOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX) in GetImmOfLdr() argument
1144 ASSERT(operand.IsImmediateOffset()); in GetImmOfLdr()
1145 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in GetImmOfLdr()
1146 if (operand.GetAddrMode() == OFFSET) { in GetImmOfLdr()
1160 uint64_t AssemblerAarch64::GetOpcodeOfLdr(const MemoryOperand &operand, Scale scale) in GetOpcodeOfLdr() argument
1163 if (operand.IsImmediateOffset()) { in GetOpcodeOfLdr()
1164 switch (operand.GetAddrMode()) { in GetOpcodeOfLdr()
1218 uint32_t AssemblerAarch64::GetShiftOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX) in GetShiftOfLdr() argument
1222 shift = operand.GetShiftOption() != Shift::NO_SHIFT; in GetShiftOfLdr()
1224 shift = operand.GetShiftAmount(); in GetShiftOfLdr()
1228 shift = operand.GetShiftAmount(); in GetShiftOfLdr()