Lines Matching full:unsigned
36 unsigned int size = static_cast<uint32_t>(width); in Create()
48 unsigned int cto = 0; in Create()
49 unsigned int i = 0; in Create()
72 unsigned immr = (size - i) & (size - 1); in Create()
84 unsigned int n = ((nImms >> 6) & 1) ^ 1; in Create()
370 const unsigned int HWORDSIZE = 16; in Mov()
372 unsigned int allOneHalfWords = 0; in Mov()
373 unsigned int allZeroHalfWords = 0; in Mov()
374 unsigned int regSize = rd.IsW() ? RegWSize : RegXSize; in Mov()
375 unsigned int halfWords = regSize / HWORDSIZE; in Mov()
377 for (unsigned int shift = 0; shift < regSize; shift += HWORDSIZE) { in Mov()
378 const unsigned int halfWord = (immValue >> shift) & HWORD_MASK; in Mov()
404 for (unsigned int shift = 0; shift < regSize; shift += HWORDSIZE) { in Mov()
477 static uint64_t UpdateImm(uint64_t imm, unsigned idx, bool clear) in UpdateImm()
607 unsigned int allOneHWords, unsigned int allZeroHWords) in EmitMovInstruct()
728 void AssemblerAarch64::Ubfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms) in Ubfm()
738 void AssemblerAarch64::Lsr(const Register &rd, const Register &rn, unsigned shift) in Lsr()
740 unsigned imms = 0; in Lsr()
755 void AssemblerAarch64::Lsl(const Register &rd, const Register &rn, unsigned shift) in Lsl()
757 unsigned immr = 0; in Lsl()
758 [[maybe_unused]] unsigned imms = 0; in Lsl()