Lines Matching +full:4 +full:- +full:ch
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
41 * Channels 2 1/4 1 6 2/8
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
147 #define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
148 #define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
149 #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
150 #define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
152 #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
238 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) in sh_cmt_read_cmstr() argument
240 if (ch->iostart) in sh_cmt_read_cmstr()
241 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
243 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
246 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmstr() argument
248 if (ch->iostart) in sh_cmt_write_cmstr()
249 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
251 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
254 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) in sh_cmt_read_cmcsr() argument
256 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); in sh_cmt_read_cmcsr()
259 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcsr() argument
261 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); in sh_cmt_write_cmcsr()
264 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) in sh_cmt_read_cmcnt() argument
266 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); in sh_cmt_read_cmcnt()
269 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcnt() argument
271 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); in sh_cmt_write_cmcnt()
274 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmcor() argument
276 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); in sh_cmt_write_cmcor()
279 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped) in sh_cmt_get_counter() argument
284 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
289 v1 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
290 v2 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
291 v3 = sh_cmt_read_cmcnt(ch); in sh_cmt_get_counter()
292 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
300 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) in sh_cmt_start_stop_ch() argument
306 raw_spin_lock_irqsave(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
307 value = sh_cmt_read_cmstr(ch); in sh_cmt_start_stop_ch()
310 value |= 1 << ch->timer_bit; in sh_cmt_start_stop_ch()
312 value &= ~(1 << ch->timer_bit); in sh_cmt_start_stop_ch()
314 sh_cmt_write_cmstr(ch, value); in sh_cmt_start_stop_ch()
315 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
318 static int sh_cmt_enable(struct sh_cmt_channel *ch) in sh_cmt_enable() argument
322 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_enable()
323 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); in sh_cmt_enable()
326 ret = clk_enable(ch->cmt->clk); in sh_cmt_enable()
328 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", in sh_cmt_enable()
329 ch->index); in sh_cmt_enable()
334 sh_cmt_start_stop_ch(ch, 0); in sh_cmt_enable()
337 if (ch->cmt->info->width == 16) { in sh_cmt_enable()
338 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | in sh_cmt_enable()
341 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | in sh_cmt_enable()
347 sh_cmt_write_cmcor(ch, 0xffffffff); in sh_cmt_enable()
348 sh_cmt_write_cmcnt(ch, 0); in sh_cmt_enable()
362 if (!sh_cmt_read_cmcnt(ch)) in sh_cmt_enable()
367 if (sh_cmt_read_cmcnt(ch)) { in sh_cmt_enable()
368 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", in sh_cmt_enable()
369 ch->index); in sh_cmt_enable()
370 ret = -ETIMEDOUT; in sh_cmt_enable()
375 sh_cmt_start_stop_ch(ch, 1); in sh_cmt_enable()
379 clk_disable(ch->cmt->clk); in sh_cmt_enable()
385 static void sh_cmt_disable(struct sh_cmt_channel *ch) in sh_cmt_disable() argument
388 sh_cmt_start_stop_ch(ch, 0); in sh_cmt_disable()
391 sh_cmt_write_cmcsr(ch, 0); in sh_cmt_disable()
394 clk_disable(ch->cmt->clk); in sh_cmt_disable()
396 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); in sh_cmt_disable()
397 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_disable()
405 #define FLAG_IRQCONTEXT (1 << 4)
407 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, in sh_cmt_clock_event_program_verify() argument
410 u32 value = ch->next_match_value; in sh_cmt_clock_event_program_verify()
416 now = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clock_event_program_verify()
417 ch->flags |= FLAG_REPROGRAM; /* force reprogram */ in sh_cmt_clock_event_program_verify()
421 * -> let the interrupt handler reprogram the timer. in sh_cmt_clock_event_program_verify()
422 * -> interrupt number two handles the event. in sh_cmt_clock_event_program_verify()
424 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
436 if (new_match > ch->max_match_value) in sh_cmt_clock_event_program_verify()
437 new_match = ch->max_match_value; in sh_cmt_clock_event_program_verify()
439 sh_cmt_write_cmcor(ch, new_match); in sh_cmt_clock_event_program_verify()
441 now = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clock_event_program_verify()
442 if (has_wrapped && (new_match > ch->match_value)) { in sh_cmt_clock_event_program_verify()
446 * -> first interrupt reprograms the timer. in sh_cmt_clock_event_program_verify()
447 * -> interrupt number two handles the event. in sh_cmt_clock_event_program_verify()
449 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
457 * -> save programmed match value. in sh_cmt_clock_event_program_verify()
458 * -> let isr handle the event. in sh_cmt_clock_event_program_verify()
460 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
468 * -> save programmed match value. in sh_cmt_clock_event_program_verify()
469 * -> let isr handle the event. in sh_cmt_clock_event_program_verify()
471 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
479 * -> increase delay and retry. in sh_cmt_clock_event_program_verify()
487 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", in sh_cmt_clock_event_program_verify()
488 ch->index); in sh_cmt_clock_event_program_verify()
493 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) in __sh_cmt_set_next() argument
495 if (delta > ch->max_match_value) in __sh_cmt_set_next()
496 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", in __sh_cmt_set_next()
497 ch->index); in __sh_cmt_set_next()
499 ch->next_match_value = delta; in __sh_cmt_set_next()
500 sh_cmt_clock_event_program_verify(ch, 0); in __sh_cmt_set_next()
503 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) in sh_cmt_set_next() argument
507 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_set_next()
508 __sh_cmt_set_next(ch, delta); in sh_cmt_set_next()
509 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_set_next()
514 struct sh_cmt_channel *ch = dev_id; in sh_cmt_interrupt() local
517 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & in sh_cmt_interrupt()
518 ch->cmt->info->clear_bits); in sh_cmt_interrupt()
524 if (ch->flags & FLAG_CLOCKSOURCE) in sh_cmt_interrupt()
525 ch->total_cycles += ch->match_value + 1; in sh_cmt_interrupt()
527 if (!(ch->flags & FLAG_REPROGRAM)) in sh_cmt_interrupt()
528 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
530 ch->flags |= FLAG_IRQCONTEXT; in sh_cmt_interrupt()
532 if (ch->flags & FLAG_CLOCKEVENT) { in sh_cmt_interrupt()
533 if (!(ch->flags & FLAG_SKIPEVENT)) { in sh_cmt_interrupt()
534 if (clockevent_state_oneshot(&ch->ced)) { in sh_cmt_interrupt()
535 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
536 ch->flags |= FLAG_REPROGRAM; in sh_cmt_interrupt()
539 ch->ced.event_handler(&ch->ced); in sh_cmt_interrupt()
543 ch->flags &= ~FLAG_SKIPEVENT; in sh_cmt_interrupt()
545 if (ch->flags & FLAG_REPROGRAM) { in sh_cmt_interrupt()
546 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
547 sh_cmt_clock_event_program_verify(ch, 1); in sh_cmt_interrupt()
549 if (ch->flags & FLAG_CLOCKEVENT) in sh_cmt_interrupt()
550 if ((clockevent_state_shutdown(&ch->ced)) in sh_cmt_interrupt()
551 || (ch->match_value == ch->next_match_value)) in sh_cmt_interrupt()
552 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
555 ch->flags &= ~FLAG_IRQCONTEXT; in sh_cmt_interrupt()
560 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) in sh_cmt_start() argument
565 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_start()
567 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) in sh_cmt_start()
568 ret = sh_cmt_enable(ch); in sh_cmt_start()
572 ch->flags |= flag; in sh_cmt_start()
575 if (ch->cmt->num_channels == 1 && in sh_cmt_start()
576 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) in sh_cmt_start()
577 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_start()
579 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_start()
584 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) in sh_cmt_stop() argument
589 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_stop()
591 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); in sh_cmt_stop()
592 ch->flags &= ~flag; in sh_cmt_stop()
594 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) in sh_cmt_stop()
595 sh_cmt_disable(ch); in sh_cmt_stop()
598 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) in sh_cmt_stop()
599 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_stop()
601 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_stop()
611 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_read() local
614 if (ch->cmt->num_channels == 1) { in sh_cmt_clocksource_read()
619 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_clocksource_read()
620 value = ch->total_cycles; in sh_cmt_clocksource_read()
621 raw = sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clocksource_read()
624 raw += ch->match_value + 1; in sh_cmt_clocksource_read()
625 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_clocksource_read()
630 return sh_cmt_get_counter(ch, &has_wrapped); in sh_cmt_clocksource_read()
636 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_enable() local
638 WARN_ON(ch->cs_enabled); in sh_cmt_clocksource_enable()
640 ch->total_cycles = 0; in sh_cmt_clocksource_enable()
642 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_enable()
644 ch->cs_enabled = true; in sh_cmt_clocksource_enable()
651 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_disable() local
653 WARN_ON(!ch->cs_enabled); in sh_cmt_clocksource_disable()
655 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_disable()
656 ch->cs_enabled = false; in sh_cmt_clocksource_disable()
661 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_suspend() local
663 if (!ch->cs_enabled) in sh_cmt_clocksource_suspend()
666 sh_cmt_stop(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_suspend()
667 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); in sh_cmt_clocksource_suspend()
672 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); in sh_cmt_clocksource_resume() local
674 if (!ch->cs_enabled) in sh_cmt_clocksource_resume()
677 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); in sh_cmt_clocksource_resume()
678 sh_cmt_start(ch, FLAG_CLOCKSOURCE); in sh_cmt_clocksource_resume()
681 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, in sh_cmt_register_clocksource() argument
684 struct clocksource *cs = &ch->cs; in sh_cmt_register_clocksource()
686 cs->name = name; in sh_cmt_register_clocksource()
687 cs->rating = 125; in sh_cmt_register_clocksource()
688 cs->read = sh_cmt_clocksource_read; in sh_cmt_register_clocksource()
689 cs->enable = sh_cmt_clocksource_enable; in sh_cmt_register_clocksource()
690 cs->disable = sh_cmt_clocksource_disable; in sh_cmt_register_clocksource()
691 cs->suspend = sh_cmt_clocksource_suspend; in sh_cmt_register_clocksource()
692 cs->resume = sh_cmt_clocksource_resume; in sh_cmt_register_clocksource()
693 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); in sh_cmt_register_clocksource()
694 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; in sh_cmt_register_clocksource()
696 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", in sh_cmt_register_clocksource()
697 ch->index); in sh_cmt_register_clocksource()
699 clocksource_register_hz(cs, ch->cmt->rate); in sh_cmt_register_clocksource()
708 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) in sh_cmt_clock_event_start() argument
710 sh_cmt_start(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_start()
713 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); in sh_cmt_clock_event_start()
715 sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_clock_event_start()
720 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_shutdown() local
722 sh_cmt_stop(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_shutdown()
729 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_set_state() local
733 sh_cmt_stop(ch, FLAG_CLOCKEVENT); in sh_cmt_clock_event_set_state()
735 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", in sh_cmt_clock_event_set_state()
736 ch->index, periodic ? "periodic" : "oneshot"); in sh_cmt_clock_event_set_state()
737 sh_cmt_clock_event_start(ch, periodic); in sh_cmt_clock_event_set_state()
754 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_next() local
757 if (likely(ch->flags & FLAG_IRQCONTEXT)) in sh_cmt_clock_event_next()
758 ch->next_match_value = delta - 1; in sh_cmt_clock_event_next()
760 sh_cmt_set_next(ch, delta - 1); in sh_cmt_clock_event_next()
767 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_suspend() local
769 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); in sh_cmt_clock_event_suspend()
770 clk_unprepare(ch->cmt->clk); in sh_cmt_clock_event_suspend()
775 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); in sh_cmt_clock_event_resume() local
777 clk_prepare(ch->cmt->clk); in sh_cmt_clock_event_resume()
778 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); in sh_cmt_clock_event_resume()
781 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, in sh_cmt_register_clockevent() argument
784 struct clock_event_device *ced = &ch->ced; in sh_cmt_register_clockevent()
788 irq = platform_get_irq(ch->cmt->pdev, ch->index); in sh_cmt_register_clockevent()
794 dev_name(&ch->cmt->pdev->dev), ch); in sh_cmt_register_clockevent()
796 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", in sh_cmt_register_clockevent()
797 ch->index, irq); in sh_cmt_register_clockevent()
801 ced->name = name; in sh_cmt_register_clockevent()
802 ced->features = CLOCK_EVT_FEAT_PERIODIC; in sh_cmt_register_clockevent()
803 ced->features |= CLOCK_EVT_FEAT_ONESHOT; in sh_cmt_register_clockevent()
804 ced->rating = 125; in sh_cmt_register_clockevent()
805 ced->cpumask = cpu_possible_mask; in sh_cmt_register_clockevent()
806 ced->set_next_event = sh_cmt_clock_event_next; in sh_cmt_register_clockevent()
807 ced->set_state_shutdown = sh_cmt_clock_event_shutdown; in sh_cmt_register_clockevent()
808 ced->set_state_periodic = sh_cmt_clock_event_set_periodic; in sh_cmt_register_clockevent()
809 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; in sh_cmt_register_clockevent()
810 ced->suspend = sh_cmt_clock_event_suspend; in sh_cmt_register_clockevent()
811 ced->resume = sh_cmt_clock_event_resume; in sh_cmt_register_clockevent()
814 ced->shift = 32; in sh_cmt_register_clockevent()
815 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); in sh_cmt_register_clockevent()
816 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); in sh_cmt_register_clockevent()
817 ced->max_delta_ticks = ch->max_match_value; in sh_cmt_register_clockevent()
818 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); in sh_cmt_register_clockevent()
819 ced->min_delta_ticks = 0x1f; in sh_cmt_register_clockevent()
821 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", in sh_cmt_register_clockevent()
822 ch->index); in sh_cmt_register_clockevent()
828 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, in sh_cmt_register() argument
834 ch->cmt->has_clockevent = true; in sh_cmt_register()
835 ret = sh_cmt_register_clockevent(ch, name); in sh_cmt_register()
841 ch->cmt->has_clocksource = true; in sh_cmt_register()
842 sh_cmt_register_clocksource(ch, name); in sh_cmt_register()
848 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, in sh_cmt_setup_channel() argument
858 ch->cmt = cmt; in sh_cmt_setup_channel()
859 ch->index = index; in sh_cmt_setup_channel()
860 ch->hwidx = hwidx; in sh_cmt_setup_channel()
861 ch->timer_bit = hwidx; in sh_cmt_setup_channel()
865 * timers with a per-channel start/stop register, compute its address in sh_cmt_setup_channel()
868 switch (cmt->info->model) { in sh_cmt_setup_channel()
870 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; in sh_cmt_setup_channel()
874 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; in sh_cmt_setup_channel()
878 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; in sh_cmt_setup_channel()
879 ch->ioctrl = ch->iostart + 0x10; in sh_cmt_setup_channel()
880 ch->timer_bit = 0; in sh_cmt_setup_channel()
884 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) in sh_cmt_setup_channel()
885 ch->max_match_value = ~0; in sh_cmt_setup_channel()
887 ch->max_match_value = (1 << cmt->info->width) - 1; in sh_cmt_setup_channel()
889 ch->match_value = ch->max_match_value; in sh_cmt_setup_channel()
890 raw_spin_lock_init(&ch->lock); in sh_cmt_setup_channel()
892 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), in sh_cmt_setup_channel()
895 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", in sh_cmt_setup_channel()
896 ch->index); in sh_cmt_setup_channel()
899 ch->cs_enabled = false; in sh_cmt_setup_channel()
908 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); in sh_cmt_map_memory()
910 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); in sh_cmt_map_memory()
911 return -ENXIO; in sh_cmt_map_memory()
914 cmt->mapbase = ioremap(mem->start, resource_size(mem)); in sh_cmt_map_memory()
915 if (cmt->mapbase == NULL) { in sh_cmt_map_memory()
916 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); in sh_cmt_map_memory()
917 return -ENXIO; in sh_cmt_map_memory()
924 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
925 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
933 .compatible = "renesas,cmt-48",
938 .compatible = "renesas,cmt-48-gen2",
942 .compatible = "renesas,r8a7740-cmt1",
946 .compatible = "renesas,sh73a0-cmt1",
950 .compatible = "renesas,rcar-gen2-cmt0",
954 .compatible = "renesas,rcar-gen2-cmt1",
958 .compatible = "renesas,rcar-gen3-cmt0",
962 .compatible = "renesas,rcar-gen3-cmt1",
975 cmt->pdev = pdev; in sh_cmt_setup()
976 raw_spin_lock_init(&cmt->lock); in sh_cmt_setup()
978 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { in sh_cmt_setup()
979 cmt->info = of_device_get_match_data(&pdev->dev); in sh_cmt_setup()
980 cmt->hw_channels = cmt->info->channels_mask; in sh_cmt_setup()
981 } else if (pdev->dev.platform_data) { in sh_cmt_setup()
982 struct sh_timer_config *cfg = pdev->dev.platform_data; in sh_cmt_setup()
983 const struct platform_device_id *id = pdev->id_entry; in sh_cmt_setup()
985 cmt->info = (const struct sh_cmt_info *)id->driver_data; in sh_cmt_setup()
986 cmt->hw_channels = cfg->channels_mask; in sh_cmt_setup()
988 dev_err(&cmt->pdev->dev, "missing platform data\n"); in sh_cmt_setup()
989 return -ENXIO; in sh_cmt_setup()
993 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); in sh_cmt_setup()
994 if (IS_ERR(cmt->clk)) { in sh_cmt_setup()
995 dev_err(&cmt->pdev->dev, "cannot get clock\n"); in sh_cmt_setup()
996 return PTR_ERR(cmt->clk); in sh_cmt_setup()
999 ret = clk_prepare(cmt->clk); in sh_cmt_setup()
1004 ret = clk_enable(cmt->clk); in sh_cmt_setup()
1008 if (cmt->info->width == 16) in sh_cmt_setup()
1009 cmt->rate = clk_get_rate(cmt->clk) / 512; in sh_cmt_setup()
1011 cmt->rate = clk_get_rate(cmt->clk) / 8; in sh_cmt_setup()
1013 clk_disable(cmt->clk); in sh_cmt_setup()
1021 cmt->num_channels = hweight8(cmt->hw_channels); in sh_cmt_setup()
1022 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), in sh_cmt_setup()
1024 if (cmt->channels == NULL) { in sh_cmt_setup()
1025 ret = -ENOMEM; in sh_cmt_setup()
1033 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { in sh_cmt_setup()
1034 unsigned int hwidx = ffs(mask) - 1; in sh_cmt_setup()
1035 bool clocksource = i == 1 || cmt->num_channels == 1; in sh_cmt_setup()
1038 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, in sh_cmt_setup()
1051 kfree(cmt->channels); in sh_cmt_setup()
1052 iounmap(cmt->mapbase); in sh_cmt_setup()
1054 clk_unprepare(cmt->clk); in sh_cmt_setup()
1056 clk_put(cmt->clk); in sh_cmt_setup()
1066 pm_runtime_set_active(&pdev->dev); in sh_cmt_probe()
1067 pm_runtime_enable(&pdev->dev); in sh_cmt_probe()
1071 dev_info(&pdev->dev, "kept as earlytimer\n"); in sh_cmt_probe()
1077 return -ENOMEM; in sh_cmt_probe()
1082 pm_runtime_idle(&pdev->dev); in sh_cmt_probe()
1089 if (cmt->has_clockevent || cmt->has_clocksource) in sh_cmt_probe()
1090 pm_runtime_irq_safe(&pdev->dev); in sh_cmt_probe()
1092 pm_runtime_idle(&pdev->dev); in sh_cmt_probe()
1099 return -EBUSY; /* cannot unregister clockevent and clocksource */ in sh_cmt_remove()