Lines Matching +full:clock +full:- +full:presc
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
91 #define STM32_AUTOSUSPEND_DELAY -1
96 u32 presc; member
131 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
135 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
137 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
138 complete(&qspi->data_completion); in stm32_qspi_irq()
158 u32 len = op->data.nbytes, sr; in stm32_qspi_tx_poll()
162 if (op->data.dir == SPI_MEM_DATA_IN) { in stm32_qspi_tx_poll()
164 buf = op->data.buf.in; in stm32_qspi_tx_poll()
168 buf = (u8 *)op->data.buf.out; in stm32_qspi_tx_poll()
171 while (len--) { in stm32_qspi_tx_poll()
172 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
176 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", in stm32_qspi_tx_poll()
180 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
189 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val, in stm32_qspi_tx_mm()
190 op->data.nbytes); in stm32_qspi_tx_mm()
212 if (op->data.dir == SPI_MEM_DATA_IN) { in stm32_qspi_tx_dma()
214 dma_ch = qspi->dma_chrx; in stm32_qspi_tx_dma()
217 dma_ch = qspi->dma_chtx; in stm32_qspi_tx_dma()
221 * spi_map_buf return -EINVAL if the buffer is not DMA-able in stm32_qspi_tx_dma()
222 * (DMA-able: in vmalloc | kmap | virt_addr_valid) in stm32_qspi_tx_dma()
224 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt); in stm32_qspi_tx_dma()
231 err = -ENOMEM; in stm32_qspi_tx_dma()
235 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
237 reinit_completion(&qspi->dma_completion); in stm32_qspi_tx_dma()
238 desc->callback = stm32_qspi_dma_callback; in stm32_qspi_tx_dma()
239 desc->callback_param = &qspi->dma_completion; in stm32_qspi_tx_dma()
247 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
250 if (!wait_for_completion_timeout(&qspi->dma_completion, in stm32_qspi_tx_dma()
252 err = -ETIMEDOUT; in stm32_qspi_tx_dma()
258 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
260 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt); in stm32_qspi_tx_dma()
267 if (!op->data.nbytes) in stm32_qspi_tx()
270 if (qspi->fmode == CCR_FMODE_MM) in stm32_qspi_tx()
272 else if ((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) || in stm32_qspi_tx()
273 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) in stm32_qspi_tx()
284 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, in stm32_qspi_wait_nobusy()
295 if (!op->data.nbytes) in stm32_qspi_wait_cmd()
298 if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) in stm32_qspi_wait_cmd()
301 reinit_completion(&qspi->data_completion); in stm32_qspi_wait_cmd()
302 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_wait_cmd()
303 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR); in stm32_qspi_wait_cmd()
305 if (!wait_for_completion_timeout(&qspi->data_completion, in stm32_qspi_wait_cmd()
307 err = -ETIMEDOUT; in stm32_qspi_wait_cmd()
309 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_wait_cmd()
311 err = -EIO; in stm32_qspi_wait_cmd()
316 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR); in stm32_qspi_wait_cmd()
334 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master); in stm32_qspi_send()
335 struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select]; in stm32_qspi_send()
339 dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", in stm32_qspi_send()
340 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, in stm32_qspi_send()
341 op->dummy.buswidth, op->data.buswidth, in stm32_qspi_send()
342 op->addr.val, op->data.nbytes); in stm32_qspi_send()
348 addr_max = op->addr.val + op->data.nbytes + 1; in stm32_qspi_send()
350 if (op->data.dir == SPI_MEM_DATA_IN) { in stm32_qspi_send()
351 if (addr_max < qspi->mm_size && in stm32_qspi_send()
352 op->addr.buswidth) in stm32_qspi_send()
353 qspi->fmode = CCR_FMODE_MM; in stm32_qspi_send()
355 qspi->fmode = CCR_FMODE_INDR; in stm32_qspi_send()
357 qspi->fmode = CCR_FMODE_INDW; in stm32_qspi_send()
360 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_send()
362 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc); in stm32_qspi_send()
363 cr |= FIELD_PREP(CR_FSEL, flash->cs); in stm32_qspi_send()
364 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_send()
366 if (op->data.nbytes) in stm32_qspi_send()
367 writel_relaxed(op->data.nbytes - 1, in stm32_qspi_send()
368 qspi->io_base + QSPI_DLR); in stm32_qspi_send()
370 qspi->fmode = CCR_FMODE_INDW; in stm32_qspi_send()
372 ccr = qspi->fmode; in stm32_qspi_send()
373 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode); in stm32_qspi_send()
375 stm32_qspi_get_mode(qspi, op->cmd.buswidth)); in stm32_qspi_send()
377 if (op->addr.nbytes) { in stm32_qspi_send()
379 stm32_qspi_get_mode(qspi, op->addr.buswidth)); in stm32_qspi_send()
380 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1); in stm32_qspi_send()
383 if (op->dummy.buswidth && op->dummy.nbytes) in stm32_qspi_send()
385 op->dummy.nbytes * 8 / op->dummy.buswidth); in stm32_qspi_send()
387 if (op->data.nbytes) { in stm32_qspi_send()
389 stm32_qspi_get_mode(qspi, op->data.buswidth)); in stm32_qspi_send()
392 writel_relaxed(ccr, qspi->io_base + QSPI_CCR); in stm32_qspi_send()
394 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM) in stm32_qspi_send()
395 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR); in stm32_qspi_send()
401 * -error case in stm32_qspi_send()
402 * -read memory map: prefetching must be stopped if we read the last in stm32_qspi_send()
403 * byte of device (device size - fifo size). like device size is not in stm32_qspi_send()
406 if (err || qspi->fmode == CCR_FMODE_MM) in stm32_qspi_send()
417 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT; in stm32_qspi_send()
418 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_send()
421 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR, in stm32_qspi_send()
425 writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR); in stm32_qspi_send()
428 dev_err(qspi->dev, "%s err:%d abort timeout:%d\n", in stm32_qspi_send()
436 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master); in stm32_qspi_exec_op()
439 ret = pm_runtime_get_sync(qspi->dev); in stm32_qspi_exec_op()
441 pm_runtime_put_noidle(qspi->dev); in stm32_qspi_exec_op()
445 mutex_lock(&qspi->lock); in stm32_qspi_exec_op()
447 mutex_unlock(&qspi->lock); in stm32_qspi_exec_op()
449 pm_runtime_mark_last_busy(qspi->dev); in stm32_qspi_exec_op()
450 pm_runtime_put_autosuspend(qspi->dev); in stm32_qspi_exec_op()
457 struct spi_controller *ctrl = spi->master; in stm32_qspi_setup()
460 u32 presc; in stm32_qspi_setup() local
463 if (ctrl->busy) in stm32_qspi_setup()
464 return -EBUSY; in stm32_qspi_setup()
466 if (!spi->max_speed_hz) in stm32_qspi_setup()
467 return -EINVAL; in stm32_qspi_setup()
469 ret = pm_runtime_get_sync(qspi->dev); in stm32_qspi_setup()
471 pm_runtime_put_noidle(qspi->dev); in stm32_qspi_setup()
475 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1; in stm32_qspi_setup()
477 flash = &qspi->flash[spi->chip_select]; in stm32_qspi_setup()
478 flash->qspi = qspi; in stm32_qspi_setup()
479 flash->cs = spi->chip_select; in stm32_qspi_setup()
480 flash->presc = presc; in stm32_qspi_setup()
482 mutex_lock(&qspi->lock); in stm32_qspi_setup()
483 qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN; in stm32_qspi_setup()
484 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); in stm32_qspi_setup()
487 qspi->dcr_reg = DCR_FSIZE_MASK; in stm32_qspi_setup()
488 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); in stm32_qspi_setup()
489 mutex_unlock(&qspi->lock); in stm32_qspi_setup()
491 pm_runtime_mark_last_busy(qspi->dev); in stm32_qspi_setup()
492 pm_runtime_put_autosuspend(qspi->dev); in stm32_qspi_setup()
500 struct device *dev = qspi->dev; in stm32_qspi_dma_setup()
507 dma_cfg.src_addr = qspi->phys_base + QSPI_DR; in stm32_qspi_dma_setup()
508 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR; in stm32_qspi_dma_setup()
512 qspi->dma_chrx = dma_request_chan(dev, "rx"); in stm32_qspi_dma_setup()
513 if (IS_ERR(qspi->dma_chrx)) { in stm32_qspi_dma_setup()
514 ret = PTR_ERR(qspi->dma_chrx); in stm32_qspi_dma_setup()
515 qspi->dma_chrx = NULL; in stm32_qspi_dma_setup()
516 if (ret == -EPROBE_DEFER) in stm32_qspi_dma_setup()
519 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) { in stm32_qspi_dma_setup()
521 dma_release_channel(qspi->dma_chrx); in stm32_qspi_dma_setup()
522 qspi->dma_chrx = NULL; in stm32_qspi_dma_setup()
526 qspi->dma_chtx = dma_request_chan(dev, "tx"); in stm32_qspi_dma_setup()
527 if (IS_ERR(qspi->dma_chtx)) { in stm32_qspi_dma_setup()
528 ret = PTR_ERR(qspi->dma_chtx); in stm32_qspi_dma_setup()
529 qspi->dma_chtx = NULL; in stm32_qspi_dma_setup()
531 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) { in stm32_qspi_dma_setup()
533 dma_release_channel(qspi->dma_chtx); in stm32_qspi_dma_setup()
534 qspi->dma_chtx = NULL; in stm32_qspi_dma_setup()
539 init_completion(&qspi->dma_completion); in stm32_qspi_dma_setup()
541 if (ret != -EPROBE_DEFER) in stm32_qspi_dma_setup()
549 if (qspi->dma_chtx) in stm32_qspi_dma_free()
550 dma_release_channel(qspi->dma_chtx); in stm32_qspi_dma_free()
551 if (qspi->dma_chrx) in stm32_qspi_dma_free()
552 dma_release_channel(qspi->dma_chrx); in stm32_qspi_dma_free()
565 struct device *dev = &pdev->dev; in stm32_qspi_probe()
574 return -ENOMEM; in stm32_qspi_probe()
577 qspi->ctrl = ctrl; in stm32_qspi_probe()
580 qspi->io_base = devm_ioremap_resource(dev, res); in stm32_qspi_probe()
581 if (IS_ERR(qspi->io_base)) { in stm32_qspi_probe()
582 ret = PTR_ERR(qspi->io_base); in stm32_qspi_probe()
586 qspi->phys_base = res->start; in stm32_qspi_probe()
589 qspi->mm_base = devm_ioremap_resource(dev, res); in stm32_qspi_probe()
590 if (IS_ERR(qspi->mm_base)) { in stm32_qspi_probe()
591 ret = PTR_ERR(qspi->mm_base); in stm32_qspi_probe()
595 qspi->mm_size = resource_size(res); in stm32_qspi_probe()
596 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) { in stm32_qspi_probe()
597 ret = -EINVAL; in stm32_qspi_probe()
614 init_completion(&qspi->data_completion); in stm32_qspi_probe()
616 qspi->clk = devm_clk_get(dev, NULL); in stm32_qspi_probe()
617 if (IS_ERR(qspi->clk)) { in stm32_qspi_probe()
618 ret = PTR_ERR(qspi->clk); in stm32_qspi_probe()
622 qspi->clk_rate = clk_get_rate(qspi->clk); in stm32_qspi_probe()
623 if (!qspi->clk_rate) { in stm32_qspi_probe()
624 ret = -EINVAL; in stm32_qspi_probe()
628 ret = clk_prepare_enable(qspi->clk); in stm32_qspi_probe()
630 dev_err(dev, "can not enable the clock\n"); in stm32_qspi_probe()
637 if (ret == -EPROBE_DEFER) in stm32_qspi_probe()
645 qspi->dev = dev; in stm32_qspi_probe()
651 mutex_init(&qspi->lock); in stm32_qspi_probe()
653 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD in stm32_qspi_probe()
655 ctrl->setup = stm32_qspi_setup; in stm32_qspi_probe()
656 ctrl->bus_num = -1; in stm32_qspi_probe()
657 ctrl->mem_ops = &stm32_qspi_mem_ops; in stm32_qspi_probe()
658 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP; in stm32_qspi_probe()
659 ctrl->dev.of_node = dev->of_node; in stm32_qspi_probe()
677 pm_runtime_get_sync(qspi->dev); in stm32_qspi_probe()
679 writel_relaxed(0, qspi->io_base + QSPI_CR); in stm32_qspi_probe()
680 mutex_destroy(&qspi->lock); in stm32_qspi_probe()
681 pm_runtime_put_noidle(qspi->dev); in stm32_qspi_probe()
682 pm_runtime_disable(qspi->dev); in stm32_qspi_probe()
683 pm_runtime_set_suspended(qspi->dev); in stm32_qspi_probe()
684 pm_runtime_dont_use_autosuspend(qspi->dev); in stm32_qspi_probe()
688 clk_disable_unprepare(qspi->clk); in stm32_qspi_probe()
690 spi_master_put(qspi->ctrl); in stm32_qspi_probe()
699 pm_runtime_get_sync(qspi->dev); in stm32_qspi_remove()
701 writel_relaxed(0, qspi->io_base + QSPI_CR); in stm32_qspi_remove()
703 mutex_destroy(&qspi->lock); in stm32_qspi_remove()
704 pm_runtime_put_noidle(qspi->dev); in stm32_qspi_remove()
705 pm_runtime_disable(qspi->dev); in stm32_qspi_remove()
706 pm_runtime_set_suspended(qspi->dev); in stm32_qspi_remove()
707 pm_runtime_dont_use_autosuspend(qspi->dev); in stm32_qspi_remove()
708 clk_disable_unprepare(qspi->clk); in stm32_qspi_remove()
717 clk_disable_unprepare(qspi->clk); in stm32_qspi_runtime_suspend()
726 return clk_prepare_enable(qspi->clk); in stm32_qspi_runtime_resume()
753 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); in stm32_qspi_resume()
754 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); in stm32_qspi_resume()
769 {.compatible = "st,stm32f469-qspi"},
778 .name = "stm32-qspi",