1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/errno.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/sizes.h>
23 #include <linux/spi/spi-mem.h>
24
25 #define QSPI_CR 0x00
26 #define CR_EN BIT(0)
27 #define CR_ABORT BIT(1)
28 #define CR_DMAEN BIT(2)
29 #define CR_TCEN BIT(3)
30 #define CR_SSHIFT BIT(4)
31 #define CR_DFM BIT(6)
32 #define CR_FSEL BIT(7)
33 #define CR_FTHRES_SHIFT 8
34 #define CR_TEIE BIT(16)
35 #define CR_TCIE BIT(17)
36 #define CR_FTIE BIT(18)
37 #define CR_SMIE BIT(19)
38 #define CR_TOIE BIT(20)
39 #define CR_PRESC_MASK GENMASK(31, 24)
40
41 #define QSPI_DCR 0x04
42 #define DCR_FSIZE_MASK GENMASK(20, 16)
43
44 #define QSPI_SR 0x08
45 #define SR_TEF BIT(0)
46 #define SR_TCF BIT(1)
47 #define SR_FTF BIT(2)
48 #define SR_SMF BIT(3)
49 #define SR_TOF BIT(4)
50 #define SR_BUSY BIT(5)
51 #define SR_FLEVEL_MASK GENMASK(13, 8)
52
53 #define QSPI_FCR 0x0c
54 #define FCR_CTEF BIT(0)
55 #define FCR_CTCF BIT(1)
56
57 #define QSPI_DLR 0x10
58
59 #define QSPI_CCR 0x14
60 #define CCR_INST_MASK GENMASK(7, 0)
61 #define CCR_IMODE_MASK GENMASK(9, 8)
62 #define CCR_ADMODE_MASK GENMASK(11, 10)
63 #define CCR_ADSIZE_MASK GENMASK(13, 12)
64 #define CCR_DCYC_MASK GENMASK(22, 18)
65 #define CCR_DMODE_MASK GENMASK(25, 24)
66 #define CCR_FMODE_MASK GENMASK(27, 26)
67 #define CCR_FMODE_INDW (0U << 26)
68 #define CCR_FMODE_INDR (1U << 26)
69 #define CCR_FMODE_APM (2U << 26)
70 #define CCR_FMODE_MM (3U << 26)
71 #define CCR_BUSWIDTH_0 0x0
72 #define CCR_BUSWIDTH_1 0x1
73 #define CCR_BUSWIDTH_2 0x2
74 #define CCR_BUSWIDTH_4 0x3
75
76 #define QSPI_AR 0x18
77 #define QSPI_ABR 0x1c
78 #define QSPI_DR 0x20
79 #define QSPI_PSMKR 0x24
80 #define QSPI_PSMAR 0x28
81 #define QSPI_PIR 0x2c
82 #define QSPI_LPTR 0x30
83
84 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
85 #define STM32_QSPI_MAX_NORCHIP 2
86
87 #define STM32_FIFO_TIMEOUT_US 30000
88 #define STM32_BUSY_TIMEOUT_US 100000
89 #define STM32_ABT_TIMEOUT_US 100000
90 #define STM32_COMP_TIMEOUT_MS 1000
91 #define STM32_AUTOSUSPEND_DELAY -1
92
93 struct stm32_qspi_flash {
94 struct stm32_qspi *qspi;
95 u32 cs;
96 u32 presc;
97 };
98
99 struct stm32_qspi {
100 struct device *dev;
101 struct spi_controller *ctrl;
102 phys_addr_t phys_base;
103 void __iomem *io_base;
104 void __iomem *mm_base;
105 resource_size_t mm_size;
106 struct clk *clk;
107 u32 clk_rate;
108 struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
109 struct completion data_completion;
110 u32 fmode;
111
112 struct dma_chan *dma_chtx;
113 struct dma_chan *dma_chrx;
114 struct completion dma_completion;
115
116 u32 cr_reg;
117 u32 dcr_reg;
118
119 /*
120 * to protect device configuration, could be different between
121 * 2 flash access (bk1, bk2)
122 */
123 struct mutex lock;
124 };
125
stm32_qspi_irq(int irq,void * dev_id)126 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
127 {
128 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
129 u32 cr, sr;
130
131 sr = readl_relaxed(qspi->io_base + QSPI_SR);
132
133 if (sr & (SR_TEF | SR_TCF)) {
134 /* disable irq */
135 cr = readl_relaxed(qspi->io_base + QSPI_CR);
136 cr &= ~CR_TCIE & ~CR_TEIE;
137 writel_relaxed(cr, qspi->io_base + QSPI_CR);
138 complete(&qspi->data_completion);
139 }
140
141 return IRQ_HANDLED;
142 }
143
stm32_qspi_read_fifo(u8 * val,void __iomem * addr)144 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
145 {
146 *val = readb_relaxed(addr);
147 }
148
stm32_qspi_write_fifo(u8 * val,void __iomem * addr)149 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
150 {
151 writeb_relaxed(*val, addr);
152 }
153
stm32_qspi_tx_poll(struct stm32_qspi * qspi,const struct spi_mem_op * op)154 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
155 const struct spi_mem_op *op)
156 {
157 void (*tx_fifo)(u8 *val, void __iomem *addr);
158 u32 len = op->data.nbytes, sr;
159 u8 *buf;
160 int ret;
161
162 if (op->data.dir == SPI_MEM_DATA_IN) {
163 tx_fifo = stm32_qspi_read_fifo;
164 buf = op->data.buf.in;
165
166 } else {
167 tx_fifo = stm32_qspi_write_fifo;
168 buf = (u8 *)op->data.buf.out;
169 }
170
171 while (len--) {
172 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
173 sr, (sr & SR_FTF), 1,
174 STM32_FIFO_TIMEOUT_US);
175 if (ret) {
176 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
177 len, sr);
178 return ret;
179 }
180 tx_fifo(buf++, qspi->io_base + QSPI_DR);
181 }
182
183 return 0;
184 }
185
stm32_qspi_tx_mm(struct stm32_qspi * qspi,const struct spi_mem_op * op)186 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
187 const struct spi_mem_op *op)
188 {
189 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
190 op->data.nbytes);
191 return 0;
192 }
193
stm32_qspi_dma_callback(void * arg)194 static void stm32_qspi_dma_callback(void *arg)
195 {
196 struct completion *dma_completion = arg;
197
198 complete(dma_completion);
199 }
200
stm32_qspi_tx_dma(struct stm32_qspi * qspi,const struct spi_mem_op * op)201 static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
202 const struct spi_mem_op *op)
203 {
204 struct dma_async_tx_descriptor *desc;
205 enum dma_transfer_direction dma_dir;
206 struct dma_chan *dma_ch;
207 struct sg_table sgt;
208 dma_cookie_t cookie;
209 u32 cr, t_out;
210 int err;
211
212 if (op->data.dir == SPI_MEM_DATA_IN) {
213 dma_dir = DMA_DEV_TO_MEM;
214 dma_ch = qspi->dma_chrx;
215 } else {
216 dma_dir = DMA_MEM_TO_DEV;
217 dma_ch = qspi->dma_chtx;
218 }
219
220 /*
221 * spi_map_buf return -EINVAL if the buffer is not DMA-able
222 * (DMA-able: in vmalloc | kmap | virt_addr_valid)
223 */
224 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
225 if (err)
226 return err;
227
228 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
229 dma_dir, DMA_PREP_INTERRUPT);
230 if (!desc) {
231 err = -ENOMEM;
232 goto out_unmap;
233 }
234
235 cr = readl_relaxed(qspi->io_base + QSPI_CR);
236
237 reinit_completion(&qspi->dma_completion);
238 desc->callback = stm32_qspi_dma_callback;
239 desc->callback_param = &qspi->dma_completion;
240 cookie = dmaengine_submit(desc);
241 err = dma_submit_error(cookie);
242 if (err)
243 goto out;
244
245 dma_async_issue_pending(dma_ch);
246
247 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
248
249 t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
250 if (!wait_for_completion_timeout(&qspi->dma_completion,
251 msecs_to_jiffies(t_out)))
252 err = -ETIMEDOUT;
253
254 if (err)
255 dmaengine_terminate_all(dma_ch);
256
257 out:
258 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
259 out_unmap:
260 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
261
262 return err;
263 }
264
stm32_qspi_tx(struct stm32_qspi * qspi,const struct spi_mem_op * op)265 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
266 {
267 if (!op->data.nbytes)
268 return 0;
269
270 if (qspi->fmode == CCR_FMODE_MM)
271 return stm32_qspi_tx_mm(qspi, op);
272 else if ((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
273 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx))
274 if (!stm32_qspi_tx_dma(qspi, op))
275 return 0;
276
277 return stm32_qspi_tx_poll(qspi, op);
278 }
279
stm32_qspi_wait_nobusy(struct stm32_qspi * qspi)280 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
281 {
282 u32 sr;
283
284 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
285 !(sr & SR_BUSY), 1,
286 STM32_BUSY_TIMEOUT_US);
287 }
288
stm32_qspi_wait_cmd(struct stm32_qspi * qspi,const struct spi_mem_op * op)289 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
290 const struct spi_mem_op *op)
291 {
292 u32 cr, sr;
293 int err = 0;
294
295 if (!op->data.nbytes)
296 goto wait_nobusy;
297
298 if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
299 goto out;
300
301 reinit_completion(&qspi->data_completion);
302 cr = readl_relaxed(qspi->io_base + QSPI_CR);
303 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
304
305 if (!wait_for_completion_timeout(&qspi->data_completion,
306 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
307 err = -ETIMEDOUT;
308 } else {
309 sr = readl_relaxed(qspi->io_base + QSPI_SR);
310 if (sr & SR_TEF)
311 err = -EIO;
312 }
313
314 out:
315 /* clear flags */
316 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
317 wait_nobusy:
318 if (!err)
319 err = stm32_qspi_wait_nobusy(qspi);
320
321 return err;
322 }
323
stm32_qspi_get_mode(struct stm32_qspi * qspi,u8 buswidth)324 static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
325 {
326 if (buswidth == 4)
327 return CCR_BUSWIDTH_4;
328
329 return buswidth;
330 }
331
stm32_qspi_send(struct spi_mem * mem,const struct spi_mem_op * op)332 static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
333 {
334 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
335 struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
336 u32 ccr, cr, addr_max;
337 int timeout, err = 0;
338
339 dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
340 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
341 op->dummy.buswidth, op->data.buswidth,
342 op->addr.val, op->data.nbytes);
343
344 err = stm32_qspi_wait_nobusy(qspi);
345 if (err)
346 goto abort;
347
348 addr_max = op->addr.val + op->data.nbytes + 1;
349
350 if (op->data.dir == SPI_MEM_DATA_IN) {
351 if (addr_max < qspi->mm_size &&
352 op->addr.buswidth)
353 qspi->fmode = CCR_FMODE_MM;
354 else
355 qspi->fmode = CCR_FMODE_INDR;
356 } else {
357 qspi->fmode = CCR_FMODE_INDW;
358 }
359
360 cr = readl_relaxed(qspi->io_base + QSPI_CR);
361 cr &= ~CR_PRESC_MASK & ~CR_FSEL;
362 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
363 cr |= FIELD_PREP(CR_FSEL, flash->cs);
364 writel_relaxed(cr, qspi->io_base + QSPI_CR);
365
366 if (op->data.nbytes)
367 writel_relaxed(op->data.nbytes - 1,
368 qspi->io_base + QSPI_DLR);
369 else
370 qspi->fmode = CCR_FMODE_INDW;
371
372 ccr = qspi->fmode;
373 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
374 ccr |= FIELD_PREP(CCR_IMODE_MASK,
375 stm32_qspi_get_mode(qspi, op->cmd.buswidth));
376
377 if (op->addr.nbytes) {
378 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
379 stm32_qspi_get_mode(qspi, op->addr.buswidth));
380 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
381 }
382
383 if (op->dummy.buswidth && op->dummy.nbytes)
384 ccr |= FIELD_PREP(CCR_DCYC_MASK,
385 op->dummy.nbytes * 8 / op->dummy.buswidth);
386
387 if (op->data.nbytes) {
388 ccr |= FIELD_PREP(CCR_DMODE_MASK,
389 stm32_qspi_get_mode(qspi, op->data.buswidth));
390 }
391
392 writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
393
394 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
395 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
396
397 err = stm32_qspi_tx(qspi, op);
398
399 /*
400 * Abort in:
401 * -error case
402 * -read memory map: prefetching must be stopped if we read the last
403 * byte of device (device size - fifo size). like device size is not
404 * knows, the prefetching is always stop.
405 */
406 if (err || qspi->fmode == CCR_FMODE_MM)
407 goto abort;
408
409 /* wait end of tx in indirect mode */
410 err = stm32_qspi_wait_cmd(qspi, op);
411 if (err)
412 goto abort;
413
414 return 0;
415
416 abort:
417 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
418 writel_relaxed(cr, qspi->io_base + QSPI_CR);
419
420 /* wait clear of abort bit by hw */
421 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
422 cr, !(cr & CR_ABORT), 1,
423 STM32_ABT_TIMEOUT_US);
424
425 writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
426
427 if (err || timeout)
428 dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
429 __func__, err, timeout);
430
431 return err;
432 }
433
stm32_qspi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)434 static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
435 {
436 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
437 int ret;
438
439 ret = pm_runtime_get_sync(qspi->dev);
440 if (ret < 0) {
441 pm_runtime_put_noidle(qspi->dev);
442 return ret;
443 }
444
445 mutex_lock(&qspi->lock);
446 ret = stm32_qspi_send(mem, op);
447 mutex_unlock(&qspi->lock);
448
449 pm_runtime_mark_last_busy(qspi->dev);
450 pm_runtime_put_autosuspend(qspi->dev);
451
452 return ret;
453 }
454
stm32_qspi_setup(struct spi_device * spi)455 static int stm32_qspi_setup(struct spi_device *spi)
456 {
457 struct spi_controller *ctrl = spi->master;
458 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
459 struct stm32_qspi_flash *flash;
460 u32 presc;
461 int ret;
462
463 if (ctrl->busy)
464 return -EBUSY;
465
466 if (!spi->max_speed_hz)
467 return -EINVAL;
468
469 ret = pm_runtime_get_sync(qspi->dev);
470 if (ret < 0) {
471 pm_runtime_put_noidle(qspi->dev);
472 return ret;
473 }
474
475 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
476
477 flash = &qspi->flash[spi->chip_select];
478 flash->qspi = qspi;
479 flash->cs = spi->chip_select;
480 flash->presc = presc;
481
482 mutex_lock(&qspi->lock);
483 qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
484 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
485
486 /* set dcr fsize to max address */
487 qspi->dcr_reg = DCR_FSIZE_MASK;
488 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
489 mutex_unlock(&qspi->lock);
490
491 pm_runtime_mark_last_busy(qspi->dev);
492 pm_runtime_put_autosuspend(qspi->dev);
493
494 return 0;
495 }
496
stm32_qspi_dma_setup(struct stm32_qspi * qspi)497 static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
498 {
499 struct dma_slave_config dma_cfg;
500 struct device *dev = qspi->dev;
501 int ret = 0;
502
503 memset(&dma_cfg, 0, sizeof(dma_cfg));
504
505 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
506 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
507 dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
508 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
509 dma_cfg.src_maxburst = 4;
510 dma_cfg.dst_maxburst = 4;
511
512 qspi->dma_chrx = dma_request_chan(dev, "rx");
513 if (IS_ERR(qspi->dma_chrx)) {
514 ret = PTR_ERR(qspi->dma_chrx);
515 qspi->dma_chrx = NULL;
516 if (ret == -EPROBE_DEFER)
517 goto out;
518 } else {
519 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
520 dev_err(dev, "dma rx config failed\n");
521 dma_release_channel(qspi->dma_chrx);
522 qspi->dma_chrx = NULL;
523 }
524 }
525
526 qspi->dma_chtx = dma_request_chan(dev, "tx");
527 if (IS_ERR(qspi->dma_chtx)) {
528 ret = PTR_ERR(qspi->dma_chtx);
529 qspi->dma_chtx = NULL;
530 } else {
531 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
532 dev_err(dev, "dma tx config failed\n");
533 dma_release_channel(qspi->dma_chtx);
534 qspi->dma_chtx = NULL;
535 }
536 }
537
538 out:
539 init_completion(&qspi->dma_completion);
540
541 if (ret != -EPROBE_DEFER)
542 ret = 0;
543
544 return ret;
545 }
546
stm32_qspi_dma_free(struct stm32_qspi * qspi)547 static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
548 {
549 if (qspi->dma_chtx)
550 dma_release_channel(qspi->dma_chtx);
551 if (qspi->dma_chrx)
552 dma_release_channel(qspi->dma_chrx);
553 }
554
555 /*
556 * no special host constraint, so use default spi_mem_default_supports_op
557 * to check supported mode.
558 */
559 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
560 .exec_op = stm32_qspi_exec_op,
561 };
562
stm32_qspi_probe(struct platform_device * pdev)563 static int stm32_qspi_probe(struct platform_device *pdev)
564 {
565 struct device *dev = &pdev->dev;
566 struct spi_controller *ctrl;
567 struct reset_control *rstc;
568 struct stm32_qspi *qspi;
569 struct resource *res;
570 int ret, irq;
571
572 ctrl = spi_alloc_master(dev, sizeof(*qspi));
573 if (!ctrl)
574 return -ENOMEM;
575
576 qspi = spi_controller_get_devdata(ctrl);
577 qspi->ctrl = ctrl;
578
579 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
580 qspi->io_base = devm_ioremap_resource(dev, res);
581 if (IS_ERR(qspi->io_base)) {
582 ret = PTR_ERR(qspi->io_base);
583 goto err_master_put;
584 }
585
586 qspi->phys_base = res->start;
587
588 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
589 qspi->mm_base = devm_ioremap_resource(dev, res);
590 if (IS_ERR(qspi->mm_base)) {
591 ret = PTR_ERR(qspi->mm_base);
592 goto err_master_put;
593 }
594
595 qspi->mm_size = resource_size(res);
596 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) {
597 ret = -EINVAL;
598 goto err_master_put;
599 }
600
601 irq = platform_get_irq(pdev, 0);
602 if (irq < 0) {
603 ret = irq;
604 goto err_master_put;
605 }
606
607 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
608 dev_name(dev), qspi);
609 if (ret) {
610 dev_err(dev, "failed to request irq\n");
611 goto err_master_put;
612 }
613
614 init_completion(&qspi->data_completion);
615
616 qspi->clk = devm_clk_get(dev, NULL);
617 if (IS_ERR(qspi->clk)) {
618 ret = PTR_ERR(qspi->clk);
619 goto err_master_put;
620 }
621
622 qspi->clk_rate = clk_get_rate(qspi->clk);
623 if (!qspi->clk_rate) {
624 ret = -EINVAL;
625 goto err_master_put;
626 }
627
628 ret = clk_prepare_enable(qspi->clk);
629 if (ret) {
630 dev_err(dev, "can not enable the clock\n");
631 goto err_master_put;
632 }
633
634 rstc = devm_reset_control_get_exclusive(dev, NULL);
635 if (IS_ERR(rstc)) {
636 ret = PTR_ERR(rstc);
637 if (ret == -EPROBE_DEFER)
638 goto err_clk_disable;
639 } else {
640 reset_control_assert(rstc);
641 udelay(2);
642 reset_control_deassert(rstc);
643 }
644
645 qspi->dev = dev;
646 platform_set_drvdata(pdev, qspi);
647 ret = stm32_qspi_dma_setup(qspi);
648 if (ret)
649 goto err_dma_free;
650
651 mutex_init(&qspi->lock);
652
653 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
654 | SPI_TX_DUAL | SPI_TX_QUAD;
655 ctrl->setup = stm32_qspi_setup;
656 ctrl->bus_num = -1;
657 ctrl->mem_ops = &stm32_qspi_mem_ops;
658 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
659 ctrl->dev.of_node = dev->of_node;
660
661 pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
662 pm_runtime_use_autosuspend(dev);
663 pm_runtime_set_active(dev);
664 pm_runtime_enable(dev);
665 pm_runtime_get_noresume(dev);
666
667 ret = devm_spi_register_master(dev, ctrl);
668 if (ret)
669 goto err_pm_runtime_free;
670
671 pm_runtime_mark_last_busy(dev);
672 pm_runtime_put_autosuspend(dev);
673
674 return 0;
675
676 err_pm_runtime_free:
677 pm_runtime_get_sync(qspi->dev);
678 /* disable qspi */
679 writel_relaxed(0, qspi->io_base + QSPI_CR);
680 mutex_destroy(&qspi->lock);
681 pm_runtime_put_noidle(qspi->dev);
682 pm_runtime_disable(qspi->dev);
683 pm_runtime_set_suspended(qspi->dev);
684 pm_runtime_dont_use_autosuspend(qspi->dev);
685 err_dma_free:
686 stm32_qspi_dma_free(qspi);
687 err_clk_disable:
688 clk_disable_unprepare(qspi->clk);
689 err_master_put:
690 spi_master_put(qspi->ctrl);
691
692 return ret;
693 }
694
stm32_qspi_remove(struct platform_device * pdev)695 static int stm32_qspi_remove(struct platform_device *pdev)
696 {
697 struct stm32_qspi *qspi = platform_get_drvdata(pdev);
698
699 pm_runtime_get_sync(qspi->dev);
700 /* disable qspi */
701 writel_relaxed(0, qspi->io_base + QSPI_CR);
702 stm32_qspi_dma_free(qspi);
703 mutex_destroy(&qspi->lock);
704 pm_runtime_put_noidle(qspi->dev);
705 pm_runtime_disable(qspi->dev);
706 pm_runtime_set_suspended(qspi->dev);
707 pm_runtime_dont_use_autosuspend(qspi->dev);
708 clk_disable_unprepare(qspi->clk);
709
710 return 0;
711 }
712
stm32_qspi_runtime_suspend(struct device * dev)713 static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
714 {
715 struct stm32_qspi *qspi = dev_get_drvdata(dev);
716
717 clk_disable_unprepare(qspi->clk);
718
719 return 0;
720 }
721
stm32_qspi_runtime_resume(struct device * dev)722 static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
723 {
724 struct stm32_qspi *qspi = dev_get_drvdata(dev);
725
726 return clk_prepare_enable(qspi->clk);
727 }
728
stm32_qspi_suspend(struct device * dev)729 static int __maybe_unused stm32_qspi_suspend(struct device *dev)
730 {
731 pinctrl_pm_select_sleep_state(dev);
732
733 return pm_runtime_force_suspend(dev);
734 }
735
stm32_qspi_resume(struct device * dev)736 static int __maybe_unused stm32_qspi_resume(struct device *dev)
737 {
738 struct stm32_qspi *qspi = dev_get_drvdata(dev);
739 int ret;
740
741 ret = pm_runtime_force_resume(dev);
742 if (ret < 0)
743 return ret;
744
745 pinctrl_pm_select_default_state(dev);
746
747 ret = pm_runtime_get_sync(dev);
748 if (ret < 0) {
749 pm_runtime_put_noidle(dev);
750 return ret;
751 }
752
753 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
754 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
755
756 pm_runtime_mark_last_busy(dev);
757 pm_runtime_put_autosuspend(dev);
758
759 return 0;
760 }
761
762 static const struct dev_pm_ops stm32_qspi_pm_ops = {
763 SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
764 stm32_qspi_runtime_resume, NULL)
765 SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
766 };
767
768 static const struct of_device_id stm32_qspi_match[] = {
769 {.compatible = "st,stm32f469-qspi"},
770 {}
771 };
772 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
773
774 static struct platform_driver stm32_qspi_driver = {
775 .probe = stm32_qspi_probe,
776 .remove = stm32_qspi_remove,
777 .driver = {
778 .name = "stm32-qspi",
779 .of_match_table = stm32_qspi_match,
780 .pm = &stm32_qspi_pm_ops,
781 },
782 };
783 module_platform_driver(stm32_qspi_driver);
784
785 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
786 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
787 MODULE_LICENSE("GPL v2");
788