Lines Matching +full:stm32 +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 * Inspired by st-asc.c from STMicroelectronics (c)
14 #include <linux/dma-direction.h>
16 #include <linux/dma-mapping.h>
35 #include "stm32-usart.h"
49 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
51 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
58 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
60 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
102 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_config_rs485()
103 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_config_rs485()
107 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
109 port->rs485 = *rs485conf; in stm32_usart_config_rs485()
111 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_usart_config_rs485()
113 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_config_rs485()
114 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
115 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
116 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_usart_config_rs485()
124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_usart_config_rs485()
126 rs485conf->delay_rts_before_send, in stm32_usart_config_rs485()
127 rs485conf->delay_rts_after_send, in stm32_usart_config_rs485()
130 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_config_rs485()
132 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_config_rs485()
135 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_config_rs485()
138 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
139 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
141 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
143 stm32_usart_clr_bits(port, ofs->cr1, in stm32_usart_config_rs485()
147 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
155 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_init_rs485()
157 rs485conf->flags = 0; in stm32_usart_init_rs485()
158 rs485conf->delay_rts_before_send = 0; in stm32_usart_init_rs485()
159 rs485conf->delay_rts_after_send = 0; in stm32_usart_init_rs485()
161 if (!pdev->dev.of_node) in stm32_usart_init_rs485()
162 return -ENODEV; in stm32_usart_init_rs485()
171 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_pending_rx()
175 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_pending_rx()
177 if (threaded && stm32_port->rx_ch) { in stm32_usart_pending_rx()
178 status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_pending_rx()
179 stm32_port->rx_ch->cookie, in stm32_usart_pending_rx()
195 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_get_char()
198 if (stm32_port->rx_ch) { in stm32_usart_get_char()
199 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; in stm32_usart_get_char()
203 c = readl_relaxed(port->membase + ofs->rdr); in stm32_usart_get_char()
205 c &= stm32_port->rdr_mask; in stm32_usart_get_char()
213 struct tty_port *tport = &port->state->port; in stm32_usart_receive_chars()
215 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars()
220 spin_lock(&port->lock); in stm32_usart_receive_chars()
222 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, in stm32_usart_receive_chars()
236 * cleared by the sequence [read SR - read DR]. in stm32_usart_receive_chars()
238 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_usart_receive_chars()
240 port->membase + ofs->icr); in stm32_usart_receive_chars()
242 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); in stm32_usart_receive_chars()
243 port->icount.rx++; in stm32_usart_receive_chars()
246 port->icount.overrun++; in stm32_usart_receive_chars()
248 port->icount.parity++; in stm32_usart_receive_chars()
252 port->icount.brk++; in stm32_usart_receive_chars()
256 port->icount.frame++; in stm32_usart_receive_chars()
260 sr &= port->read_status_mask; in stm32_usart_receive_chars()
277 spin_unlock(&port->lock); in stm32_usart_receive_chars()
286 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_tx_dma_complete()
289 dmaengine_terminate_async(stm32port->tx_ch); in stm32_usart_tx_dma_complete()
290 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_tx_dma_complete()
291 stm32port->tx_dma_busy = false; in stm32_usart_tx_dma_complete()
294 spin_lock_irqsave(&port->lock, flags); in stm32_usart_tx_dma_complete()
296 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_tx_dma_complete()
302 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_enable()
308 if (stm32_port->fifoen) in stm32_usart_tx_interrupt_enable()
309 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
311 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_enable()
317 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_disable()
319 if (stm32_port->fifoen) in stm32_usart_tx_interrupt_disable()
320 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
322 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_disable()
328 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars_pio()
329 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_pio()
331 if (stm32_port->tx_dma_busy) { in stm32_usart_transmit_chars_pio()
332 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_pio()
333 stm32_port->tx_dma_busy = false; in stm32_usart_transmit_chars_pio()
338 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_transmit_chars_pio()
340 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_usart_transmit_chars_pio()
341 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in stm32_usart_transmit_chars_pio()
342 port->icount.tx++; in stm32_usart_transmit_chars_pio()
355 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_transmit_chars_dma()
356 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_dma()
360 if (stm32port->tx_dma_busy) in stm32_usart_transmit_chars_dma()
363 stm32port->tx_dma_busy = true; in stm32_usart_transmit_chars_dma()
370 if (xmit->tail < xmit->head) { in stm32_usart_transmit_chars_dma()
371 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_usart_transmit_chars_dma()
373 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_usart_transmit_chars_dma()
378 two = count - one; in stm32_usart_transmit_chars_dma()
380 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_usart_transmit_chars_dma()
382 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_usart_transmit_chars_dma()
385 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_usart_transmit_chars_dma()
386 stm32port->tx_dma_buf, in stm32_usart_transmit_chars_dma()
394 desc->callback = stm32_usart_tx_dma_complete; in stm32_usart_transmit_chars_dma()
395 desc->callback_param = port; in stm32_usart_transmit_chars_dma()
400 dmaengine_terminate_async(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
405 dma_async_issue_pending(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
407 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_dma()
409 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in stm32_usart_transmit_chars_dma()
410 port->icount.tx += count; in stm32_usart_transmit_chars_dma()
414 for (i = count; i > 0; i--) in stm32_usart_transmit_chars_dma()
421 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars()
422 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars()
424 if (port->x_char) { in stm32_usart_transmit_chars()
425 if (stm32_port->tx_dma_busy) in stm32_usart_transmit_chars()
426 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
427 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_usart_transmit_chars()
428 port->x_char = 0; in stm32_usart_transmit_chars()
429 port->icount.tx++; in stm32_usart_transmit_chars()
430 if (stm32_port->tx_dma_busy) in stm32_usart_transmit_chars()
431 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
440 if (ofs->icr == UNDEF_REG) in stm32_usart_transmit_chars()
441 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_usart_transmit_chars()
443 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_usart_transmit_chars()
445 if (stm32_port->tx_ch) in stm32_usart_transmit_chars()
460 struct tty_port *tport = &port->state->port; in stm32_usart_interrupt()
462 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_interrupt()
465 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_interrupt()
467 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) in stm32_usart_interrupt()
469 port->membase + ofs->icr); in stm32_usart_interrupt()
471 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
474 port->membase + ofs->icr); in stm32_usart_interrupt()
475 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
476 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_usart_interrupt()
477 pm_wakeup_event(tport->tty->dev, 0); in stm32_usart_interrupt()
480 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) in stm32_usart_interrupt()
483 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { in stm32_usart_interrupt()
484 spin_lock(&port->lock); in stm32_usart_interrupt()
486 spin_unlock(&port->lock); in stm32_usart_interrupt()
489 if (stm32_port->rx_ch) in stm32_usart_interrupt()
500 if (stm32_port->rx_ch) in stm32_usart_threaded_interrupt()
509 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
511 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) in stm32_usart_tx_empty()
520 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_mctrl()
522 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_usart_set_mctrl()
523 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
525 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
527 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_usart_set_mctrl()
538 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_usart_get_mctrl()
543 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_usart_enable_ms()
548 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_usart_disable_ms()
555 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_stop_tx()
559 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_stop_tx()
560 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_stop_tx()
561 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_stop_tx()
562 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_stop_tx()
564 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_stop_tx()
565 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_stop_tx()
574 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_start_tx()
575 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_start_tx()
577 if (uart_circ_empty(xmit) && !port->x_char) in stm32_usart_start_tx()
580 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_start_tx()
581 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_start_tx()
582 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_start_tx()
583 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_start_tx()
585 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_start_tx()
586 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_start_tx()
597 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_throttle()
600 spin_lock_irqsave(&port->lock, flags); in stm32_usart_throttle()
601 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_throttle()
602 if (stm32_port->cr3_irq) in stm32_usart_throttle()
603 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
605 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_throttle()
612 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_unthrottle()
615 spin_lock_irqsave(&port->lock, flags); in stm32_usart_unthrottle()
616 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_unthrottle()
617 if (stm32_port->cr3_irq) in stm32_usart_unthrottle()
618 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
620 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_unthrottle()
627 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_rx()
629 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_stop_rx()
630 if (stm32_port->cr3_irq) in stm32_usart_stop_rx()
631 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
634 /* Handle breaks - ignored by us */
642 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_startup()
643 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_startup()
644 const char *name = to_platform_device(port->dev)->name; in stm32_usart_startup()
648 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, in stm32_usart_startup()
656 if (ofs->rqr != UNDEF_REG) in stm32_usart_startup()
657 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); in stm32_usart_startup()
660 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); in stm32_usart_startup()
661 stm32_usart_set_bits(port, ofs->cr1, val); in stm32_usart_startup()
669 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_shutdown()
670 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_shutdown()
678 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_usart_shutdown()
679 val |= BIT(cfg->uart_enable_bit); in stm32_usart_shutdown()
680 if (stm32_port->fifoen) in stm32_usart_shutdown()
683 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_usart_shutdown()
688 dev_err(port->dev, "transmission complete not set\n"); in stm32_usart_shutdown()
691 if (ofs->rqr != UNDEF_REG) in stm32_usart_shutdown()
693 port->membase + ofs->rqr); in stm32_usart_shutdown()
695 stm32_usart_clr_bits(port, ofs->cr1, val); in stm32_usart_shutdown()
697 free_irq(port->irq, port); in stm32_usart_shutdown()
704 tcflag_t cflag = termios->c_cflag; in stm32_usart_get_databits()
735 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_termios()
736 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_set_termios()
737 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_set_termios()
740 tcflag_t cflag = termios->c_cflag; in stm32_usart_set_termios()
745 if (!stm32_port->hw_flow_control) in stm32_usart_set_termios()
748 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_usart_set_termios()
750 spin_lock_irqsave(&port->lock, flags); in stm32_usart_set_termios()
752 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_set_termios()
759 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_set_termios()
762 writel_relaxed(0, port->membase + ofs->cr1); in stm32_usart_set_termios()
765 if (ofs->rqr != UNDEF_REG) in stm32_usart_set_termios()
767 port->membase + ofs->rqr); in stm32_usart_set_termios()
770 if (stm32_port->fifoen) in stm32_usart_set_termios()
775 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
777 if (stm32_port->fifoen) { in stm32_usart_set_termios()
787 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_usart_set_termios()
803 else if ((bits == 7) && cfg->has_7bits_data) in stm32_usart_set_termios()
806 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_usart_set_termios()
809 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_usart_set_termios()
810 stm32_port->fifoen)) { in stm32_usart_set_termios()
817 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_usart_set_termios()
818 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_usart_set_termios()
821 if (!stm32_port->rx_ch) in stm32_usart_set_termios()
822 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_usart_set_termios()
825 cr1 |= stm32_port->cr1_irq; in stm32_usart_set_termios()
826 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
831 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_usart_set_termios()
833 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_usart_set_termios()
837 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_usart_set_termios()
848 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
852 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
857 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_usart_set_termios()
861 port->read_status_mask = USART_SR_ORE; in stm32_usart_set_termios()
862 if (termios->c_iflag & INPCK) in stm32_usart_set_termios()
863 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
864 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_usart_set_termios()
865 port->read_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
868 port->ignore_status_mask = 0; in stm32_usart_set_termios()
869 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
870 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
871 if (termios->c_iflag & IGNBRK) { in stm32_usart_set_termios()
872 port->ignore_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
877 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
878 port->ignore_status_mask |= USART_SR_ORE; in stm32_usart_set_termios()
882 if ((termios->c_cflag & CREAD) == 0) in stm32_usart_set_termios()
883 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_usart_set_termios()
885 if (stm32_port->rx_ch) in stm32_usart_set_termios()
888 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_set_termios()
890 rs485conf->delay_rts_before_send, in stm32_usart_set_termios()
891 rs485conf->delay_rts_after_send, in stm32_usart_set_termios()
893 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_set_termios()
895 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
898 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
907 if (stm32_port->wakeirq > 0) { in stm32_usart_set_termios()
912 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
913 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_usart_set_termios()
914 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_set_termios()
916 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_set_termios()
917 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_set_termios()
920 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_usart_set_termios()
928 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_usart_type()
943 port->type = PORT_STM32; in stm32_usart_config_port()
950 return -EINVAL; in stm32_usart_verify_port()
958 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_pm()
959 const struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_usart_pm()
964 pm_runtime_get_sync(port->dev); in stm32_usart_pm()
967 spin_lock_irqsave(&port->lock, flags); in stm32_usart_pm()
968 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_pm()
969 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_pm()
970 pm_runtime_put_sync(port->dev); in stm32_usart_pm()
1000 struct uart_port *port = &stm32port->port; in stm32_usart_init_port()
1006 return ret ? : -ENODEV; in stm32_usart_init_port()
1008 port->iotype = UPIO_MEM; in stm32_usart_init_port()
1009 port->flags = UPF_BOOT_AUTOCONF; in stm32_usart_init_port()
1010 port->ops = &stm32_uart_ops; in stm32_usart_init_port()
1011 port->dev = &pdev->dev; in stm32_usart_init_port()
1012 port->fifosize = stm32port->info->cfg.fifosize; in stm32_usart_init_port()
1013 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_usart_init_port()
1014 port->irq = ret; in stm32_usart_init_port()
1015 port->rs485_config = stm32_usart_config_rs485; in stm32_usart_init_port()
1021 if (stm32port->info->cfg.has_wakeup) { in stm32_usart_init_port()
1022 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); in stm32_usart_init_port()
1023 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) in stm32_usart_init_port()
1024 return stm32port->wakeirq ? : -ENODEV; in stm32_usart_init_port()
1027 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_usart_init_port()
1030 port->membase = devm_ioremap_resource(&pdev->dev, res); in stm32_usart_init_port()
1031 if (IS_ERR(port->membase)) in stm32_usart_init_port()
1032 return PTR_ERR(port->membase); in stm32_usart_init_port()
1033 port->mapbase = res->start; in stm32_usart_init_port()
1035 spin_lock_init(&port->lock); in stm32_usart_init_port()
1037 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_usart_init_port()
1038 if (IS_ERR(stm32port->clk)) in stm32_usart_init_port()
1039 return PTR_ERR(stm32port->clk); in stm32_usart_init_port()
1042 ret = clk_prepare_enable(stm32port->clk); in stm32_usart_init_port()
1046 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_usart_init_port()
1047 if (!stm32port->port.uartclk) { in stm32_usart_init_port()
1048 ret = -EINVAL; in stm32_usart_init_port()
1052 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_usart_init_port()
1053 if (IS_ERR(stm32port->gpios)) { in stm32_usart_init_port()
1054 ret = PTR_ERR(stm32port->gpios); in stm32_usart_init_port()
1058 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ in stm32_usart_init_port()
1059 if (stm32port->hw_flow_control) { in stm32_usart_init_port()
1060 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_usart_init_port()
1061 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_usart_init_port()
1062 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_usart_init_port()
1063 ret = -EINVAL; in stm32_usart_init_port()
1071 clk_disable_unprepare(stm32port->clk); in stm32_usart_init_port()
1078 struct device_node *np = pdev->dev.of_node; in stm32_usart_of_get_port()
1086 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_usart_of_get_port()
1094 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_usart_of_get_port()
1095 of_property_read_bool (np, "uart-has-rtscts"); in stm32_usart_of_get_port()
1105 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1106 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1107 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1117 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_rx_probe()
1118 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_rx_probe()
1119 struct device *dev = &pdev->dev; in stm32_usart_of_dma_rx_probe()
1129 return -ENODEV; in stm32_usart_of_dma_rx_probe()
1132 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); in stm32_usart_of_dma_rx_probe()
1133 if (!stm32port->rx_ch) { in stm32_usart_of_dma_rx_probe()
1135 return -ENODEV; in stm32_usart_of_dma_rx_probe()
1137 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, in stm32_usart_of_dma_rx_probe()
1138 &stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1140 if (!stm32port->rx_buf) { in stm32_usart_of_dma_rx_probe()
1141 ret = -ENOMEM; in stm32_usart_of_dma_rx_probe()
1147 config.src_addr = port->mapbase + ofs->rdr; in stm32_usart_of_dma_rx_probe()
1150 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_usart_of_dma_rx_probe()
1153 ret = -ENODEV; in stm32_usart_of_dma_rx_probe()
1158 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, in stm32_usart_of_dma_rx_probe()
1159 stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1164 ret = -ENODEV; in stm32_usart_of_dma_rx_probe()
1169 desc->callback = NULL; in stm32_usart_of_dma_rx_probe()
1170 desc->callback_param = NULL; in stm32_usart_of_dma_rx_probe()
1175 dmaengine_terminate_sync(stm32port->rx_ch); in stm32_usart_of_dma_rx_probe()
1180 dma_async_issue_pending(stm32port->rx_ch); in stm32_usart_of_dma_rx_probe()
1185 dma_free_coherent(&pdev->dev, in stm32_usart_of_dma_rx_probe()
1186 RX_BUF_L, stm32port->rx_buf, in stm32_usart_of_dma_rx_probe()
1187 stm32port->rx_dma_buf); in stm32_usart_of_dma_rx_probe()
1190 dma_release_channel(stm32port->rx_ch); in stm32_usart_of_dma_rx_probe()
1191 stm32port->rx_ch = NULL; in stm32_usart_of_dma_rx_probe()
1199 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_tx_probe()
1200 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_tx_probe()
1201 struct device *dev = &pdev->dev; in stm32_usart_of_dma_tx_probe()
1205 stm32port->tx_dma_busy = false; in stm32_usart_of_dma_tx_probe()
1208 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); in stm32_usart_of_dma_tx_probe()
1209 if (!stm32port->tx_ch) { in stm32_usart_of_dma_tx_probe()
1211 return -ENODEV; in stm32_usart_of_dma_tx_probe()
1213 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, in stm32_usart_of_dma_tx_probe()
1214 &stm32port->tx_dma_buf, in stm32_usart_of_dma_tx_probe()
1216 if (!stm32port->tx_buf) { in stm32_usart_of_dma_tx_probe()
1217 ret = -ENOMEM; in stm32_usart_of_dma_tx_probe()
1223 config.dst_addr = port->mapbase + ofs->tdr; in stm32_usart_of_dma_tx_probe()
1226 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_usart_of_dma_tx_probe()
1229 ret = -ENODEV; in stm32_usart_of_dma_tx_probe()
1236 dma_free_coherent(&pdev->dev, in stm32_usart_of_dma_tx_probe()
1237 TX_BUF_L, stm32port->tx_buf, in stm32_usart_of_dma_tx_probe()
1238 stm32port->tx_dma_buf); in stm32_usart_of_dma_tx_probe()
1241 dma_release_channel(stm32port->tx_ch); in stm32_usart_of_dma_tx_probe()
1242 stm32port->tx_ch = NULL; in stm32_usart_of_dma_tx_probe()
1254 return -ENODEV; in stm32_usart_serial_probe()
1256 stm32port->info = of_device_get_match_data(&pdev->dev); in stm32_usart_serial_probe()
1257 if (!stm32port->info) in stm32_usart_serial_probe()
1258 return -EINVAL; in stm32_usart_serial_probe()
1264 if (stm32port->wakeirq > 0) { in stm32_usart_serial_probe()
1265 ret = device_init_wakeup(&pdev->dev, true); in stm32_usart_serial_probe()
1269 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, in stm32_usart_serial_probe()
1270 stm32port->wakeirq); in stm32_usart_serial_probe()
1274 device_set_wakeup_enable(&pdev->dev, false); in stm32_usart_serial_probe()
1279 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); in stm32_usart_serial_probe()
1283 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); in stm32_usart_serial_probe()
1285 platform_set_drvdata(pdev, &stm32port->port); in stm32_usart_serial_probe()
1287 pm_runtime_get_noresume(&pdev->dev); in stm32_usart_serial_probe()
1288 pm_runtime_set_active(&pdev->dev); in stm32_usart_serial_probe()
1289 pm_runtime_enable(&pdev->dev); in stm32_usart_serial_probe()
1291 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_usart_serial_probe()
1295 pm_runtime_put_sync(&pdev->dev); in stm32_usart_serial_probe()
1300 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_probe()
1301 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_probe()
1302 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_probe()
1304 if (stm32port->rx_ch) { in stm32_usart_serial_probe()
1305 dmaengine_terminate_async(stm32port->rx_ch); in stm32_usart_serial_probe()
1306 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1309 if (stm32port->rx_dma_buf) in stm32_usart_serial_probe()
1310 dma_free_coherent(&pdev->dev, in stm32_usart_serial_probe()
1311 RX_BUF_L, stm32port->rx_buf, in stm32_usart_serial_probe()
1312 stm32port->rx_dma_buf); in stm32_usart_serial_probe()
1314 if (stm32port->tx_ch) { in stm32_usart_serial_probe()
1315 dmaengine_terminate_async(stm32port->tx_ch); in stm32_usart_serial_probe()
1316 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1319 if (stm32port->tx_dma_buf) in stm32_usart_serial_probe()
1320 dma_free_coherent(&pdev->dev, in stm32_usart_serial_probe()
1321 TX_BUF_L, stm32port->tx_buf, in stm32_usart_serial_probe()
1322 stm32port->tx_dma_buf); in stm32_usart_serial_probe()
1324 if (stm32port->wakeirq > 0) in stm32_usart_serial_probe()
1325 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_probe()
1328 if (stm32port->wakeirq > 0) in stm32_usart_serial_probe()
1329 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_probe()
1332 clk_disable_unprepare(stm32port->clk); in stm32_usart_serial_probe()
1341 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_remove()
1344 pm_runtime_get_sync(&pdev->dev); in stm32_usart_serial_remove()
1349 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_remove()
1350 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_remove()
1351 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_remove()
1353 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_serial_remove()
1355 if (stm32_port->rx_ch) { in stm32_usart_serial_remove()
1356 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_serial_remove()
1357 dma_release_channel(stm32_port->rx_ch); in stm32_usart_serial_remove()
1360 if (stm32_port->rx_dma_buf) in stm32_usart_serial_remove()
1361 dma_free_coherent(&pdev->dev, in stm32_usart_serial_remove()
1362 RX_BUF_L, stm32_port->rx_buf, in stm32_usart_serial_remove()
1363 stm32_port->rx_dma_buf); in stm32_usart_serial_remove()
1365 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_serial_remove()
1367 if (stm32_port->tx_ch) { in stm32_usart_serial_remove()
1368 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_serial_remove()
1369 dma_release_channel(stm32_port->tx_ch); in stm32_usart_serial_remove()
1372 if (stm32_port->tx_dma_buf) in stm32_usart_serial_remove()
1373 dma_free_coherent(&pdev->dev, in stm32_usart_serial_remove()
1374 TX_BUF_L, stm32_port->tx_buf, in stm32_usart_serial_remove()
1375 stm32_port->tx_dma_buf); in stm32_usart_serial_remove()
1377 if (stm32_port->wakeirq > 0) { in stm32_usart_serial_remove()
1378 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_remove()
1379 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_remove()
1382 clk_disable_unprepare(stm32_port->clk); in stm32_usart_serial_remove()
1391 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_putchar()
1393 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_console_putchar()
1396 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_console_putchar()
1402 struct uart_port *port = &stm32_ports[co->index].port; in stm32_usart_console_write()
1404 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_write()
1405 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_console_write()
1411 if (port->sysrq) in stm32_usart_console_write()
1414 locked = spin_trylock(&port->lock); in stm32_usart_console_write()
1416 spin_lock(&port->lock); in stm32_usart_console_write()
1419 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_console_write()
1421 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_usart_console_write()
1422 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1427 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1430 spin_unlock(&port->lock); in stm32_usart_console_write()
1442 if (co->index >= STM32_MAX_PORTS) in stm32_usart_console_setup()
1443 return -ENODEV; in stm32_usart_console_setup()
1445 stm32port = &stm32_ports[co->index]; in stm32_usart_console_setup()
1450 * this to be called during the uart port registration when the in stm32_usart_console_setup()
1453 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) in stm32_usart_console_setup()
1454 return -ENXIO; in stm32_usart_console_setup()
1459 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_usart_console_setup()
1468 .index = -1,
1491 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_en_wakeup()
1493 if (stm32_port->wakeirq <= 0) in stm32_usart_serial_en_wakeup()
1497 * Enable low-power wake-up and wake-up irq if argument is set to in stm32_usart_serial_en_wakeup()
1498 * "enable", disable low-power wake-up and wake-up irq otherwise in stm32_usart_serial_en_wakeup()
1501 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
1502 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
1504 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
1505 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
1554 clk_disable_unprepare(stm32port->clk); in stm32_usart_runtime_suspend()
1565 return clk_prepare_enable(stm32port->clk); in stm32_usart_runtime_resume()
1587 static char banner[] __initdata = "STM32 USART driver initialized"; in stm32_usart_init()
1613 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");