1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@st.com>
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)
9 */
10
11 #include <linux/clk.h>
12 #include <linux/console.h>
13 #include <linux/delay.h>
14 #include <linux/dma-direction.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_platform.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/pm_wakeirq.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial.h>
29 #include <linux/spinlock.h>
30 #include <linux/sysrq.h>
31 #include <linux/tty_flip.h>
32 #include <linux/tty.h>
33
34 #include "serial_mctrl_gpio.h"
35 #include "stm32-usart.h"
36
37 static void stm32_usart_stop_tx(struct uart_port *port);
38 static void stm32_usart_transmit_chars(struct uart_port *port);
39
to_stm32_port(struct uart_port * port)40 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
41 {
42 return container_of(port, struct stm32_port, port);
43 }
44
stm32_usart_set_bits(struct uart_port * port,u32 reg,u32 bits)45 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
46 {
47 u32 val;
48
49 val = readl_relaxed(port->membase + reg);
50 val |= bits;
51 writel_relaxed(val, port->membase + reg);
52 }
53
stm32_usart_clr_bits(struct uart_port * port,u32 reg,u32 bits)54 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
55 {
56 u32 val;
57
58 val = readl_relaxed(port->membase + reg);
59 val &= ~bits;
60 writel_relaxed(val, port->membase + reg);
61 }
62
stm32_usart_config_reg_rs485(u32 * cr1,u32 * cr3,u32 delay_ADE,u32 delay_DDE,u32 baud)63 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
64 u32 delay_DDE, u32 baud)
65 {
66 u32 rs485_deat_dedt;
67 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
68 bool over8;
69
70 *cr3 |= USART_CR3_DEM;
71 over8 = *cr1 & USART_CR1_OVER8;
72
73 if (over8)
74 rs485_deat_dedt = delay_ADE * baud * 8;
75 else
76 rs485_deat_dedt = delay_ADE * baud * 16;
77
78 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
79 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
80 rs485_deat_dedt_max : rs485_deat_dedt;
81 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
82 USART_CR1_DEAT_MASK;
83 *cr1 |= rs485_deat_dedt;
84
85 if (over8)
86 rs485_deat_dedt = delay_DDE * baud * 8;
87 else
88 rs485_deat_dedt = delay_DDE * baud * 16;
89
90 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
91 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
92 rs485_deat_dedt_max : rs485_deat_dedt;
93 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
94 USART_CR1_DEDT_MASK;
95 *cr1 |= rs485_deat_dedt;
96 }
97
stm32_usart_config_rs485(struct uart_port * port,struct serial_rs485 * rs485conf)98 static int stm32_usart_config_rs485(struct uart_port *port,
99 struct serial_rs485 *rs485conf)
100 {
101 struct stm32_port *stm32_port = to_stm32_port(port);
102 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
103 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
104 u32 usartdiv, baud, cr1, cr3;
105 bool over8;
106
107 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
108
109 port->rs485 = *rs485conf;
110
111 rs485conf->flags |= SER_RS485_RX_DURING_TX;
112
113 if (rs485conf->flags & SER_RS485_ENABLED) {
114 cr1 = readl_relaxed(port->membase + ofs->cr1);
115 cr3 = readl_relaxed(port->membase + ofs->cr3);
116 usartdiv = readl_relaxed(port->membase + ofs->brr);
117 usartdiv = usartdiv & GENMASK(15, 0);
118 over8 = cr1 & USART_CR1_OVER8;
119
120 if (over8)
121 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
122 << USART_BRR_04_R_SHIFT;
123
124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
125 stm32_usart_config_reg_rs485(&cr1, &cr3,
126 rs485conf->delay_rts_before_send,
127 rs485conf->delay_rts_after_send,
128 baud);
129
130 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
131 cr3 &= ~USART_CR3_DEP;
132 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
133 } else {
134 cr3 |= USART_CR3_DEP;
135 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
136 }
137
138 writel_relaxed(cr3, port->membase + ofs->cr3);
139 writel_relaxed(cr1, port->membase + ofs->cr1);
140 } else {
141 stm32_usart_clr_bits(port, ofs->cr3,
142 USART_CR3_DEM | USART_CR3_DEP);
143 stm32_usart_clr_bits(port, ofs->cr1,
144 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
145 }
146
147 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
148
149 return 0;
150 }
151
stm32_usart_init_rs485(struct uart_port * port,struct platform_device * pdev)152 static int stm32_usart_init_rs485(struct uart_port *port,
153 struct platform_device *pdev)
154 {
155 struct serial_rs485 *rs485conf = &port->rs485;
156
157 rs485conf->flags = 0;
158 rs485conf->delay_rts_before_send = 0;
159 rs485conf->delay_rts_after_send = 0;
160
161 if (!pdev->dev.of_node)
162 return -ENODEV;
163
164 return uart_get_rs485_mode(port);
165 }
166
stm32_usart_pending_rx(struct uart_port * port,u32 * sr,int * last_res,bool threaded)167 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr,
168 int *last_res, bool threaded)
169 {
170 struct stm32_port *stm32_port = to_stm32_port(port);
171 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
172 enum dma_status status;
173 struct dma_tx_state state;
174
175 *sr = readl_relaxed(port->membase + ofs->isr);
176
177 if (threaded && stm32_port->rx_ch) {
178 status = dmaengine_tx_status(stm32_port->rx_ch,
179 stm32_port->rx_ch->cookie,
180 &state);
181 if (status == DMA_IN_PROGRESS && (*last_res != state.residue))
182 return 1;
183 else
184 return 0;
185 } else if (*sr & USART_SR_RXNE) {
186 return 1;
187 }
188 return 0;
189 }
190
stm32_usart_get_char(struct uart_port * port,u32 * sr,int * last_res)191 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr,
192 int *last_res)
193 {
194 struct stm32_port *stm32_port = to_stm32_port(port);
195 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
196 unsigned long c;
197
198 if (stm32_port->rx_ch) {
199 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
200 if ((*last_res) == 0)
201 *last_res = RX_BUF_L;
202 } else {
203 c = readl_relaxed(port->membase + ofs->rdr);
204 /* apply RDR data mask */
205 c &= stm32_port->rdr_mask;
206 }
207
208 return c;
209 }
210
stm32_usart_receive_chars(struct uart_port * port,bool threaded)211 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
212 {
213 struct tty_port *tport = &port->state->port;
214 struct stm32_port *stm32_port = to_stm32_port(port);
215 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
216 unsigned long c;
217 u32 sr;
218 char flag;
219
220 spin_lock(&port->lock);
221
222 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
223 threaded)) {
224 sr |= USART_SR_DUMMY_RX;
225 flag = TTY_NORMAL;
226
227 /*
228 * Status bits has to be cleared before reading the RDR:
229 * In FIFO mode, reading the RDR will pop the next data
230 * (if any) along with its status bits into the SR.
231 * Not doing so leads to misalignement between RDR and SR,
232 * and clear status bits of the next rx data.
233 *
234 * Clear errors flags for stm32f7 and stm32h7 compatible
235 * devices. On stm32f4 compatible devices, the error bit is
236 * cleared by the sequence [read SR - read DR].
237 */
238 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
239 writel_relaxed(sr & USART_SR_ERR_MASK,
240 port->membase + ofs->icr);
241
242 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res);
243 port->icount.rx++;
244 if (sr & USART_SR_ERR_MASK) {
245 if (sr & USART_SR_ORE) {
246 port->icount.overrun++;
247 } else if (sr & USART_SR_PE) {
248 port->icount.parity++;
249 } else if (sr & USART_SR_FE) {
250 /* Break detection if character is null */
251 if (!c) {
252 port->icount.brk++;
253 if (uart_handle_break(port))
254 continue;
255 } else {
256 port->icount.frame++;
257 }
258 }
259
260 sr &= port->read_status_mask;
261
262 if (sr & USART_SR_PE) {
263 flag = TTY_PARITY;
264 } else if (sr & USART_SR_FE) {
265 if (!c)
266 flag = TTY_BREAK;
267 else
268 flag = TTY_FRAME;
269 }
270 }
271
272 if (uart_handle_sysrq_char(port, c))
273 continue;
274 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
275 }
276
277 spin_unlock(&port->lock);
278
279 tty_flip_buffer_push(tport);
280 }
281
stm32_usart_tx_dma_complete(void * arg)282 static void stm32_usart_tx_dma_complete(void *arg)
283 {
284 struct uart_port *port = arg;
285 struct stm32_port *stm32port = to_stm32_port(port);
286 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
287 unsigned long flags;
288
289 dmaengine_terminate_async(stm32port->tx_ch);
290 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
291 stm32port->tx_dma_busy = false;
292
293 /* Let's see if we have pending data to send */
294 spin_lock_irqsave(&port->lock, flags);
295 stm32_usart_transmit_chars(port);
296 spin_unlock_irqrestore(&port->lock, flags);
297 }
298
stm32_usart_tx_interrupt_enable(struct uart_port * port)299 static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
300 {
301 struct stm32_port *stm32_port = to_stm32_port(port);
302 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
303
304 /*
305 * Enables TX FIFO threashold irq when FIFO is enabled,
306 * or TX empty irq when FIFO is disabled
307 */
308 if (stm32_port->fifoen)
309 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
310 else
311 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
312 }
313
stm32_usart_tx_interrupt_disable(struct uart_port * port)314 static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
315 {
316 struct stm32_port *stm32_port = to_stm32_port(port);
317 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
318
319 if (stm32_port->fifoen)
320 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
321 else
322 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
323 }
324
stm32_usart_transmit_chars_pio(struct uart_port * port)325 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
326 {
327 struct stm32_port *stm32_port = to_stm32_port(port);
328 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
329 struct circ_buf *xmit = &port->state->xmit;
330
331 if (stm32_port->tx_dma_busy) {
332 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
333 stm32_port->tx_dma_busy = false;
334 }
335
336 while (!uart_circ_empty(xmit)) {
337 /* Check that TDR is empty before filling FIFO */
338 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
339 break;
340 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
341 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
342 port->icount.tx++;
343 }
344
345 /* rely on TXE irq (mask or unmask) for sending remaining data */
346 if (uart_circ_empty(xmit))
347 stm32_usart_tx_interrupt_disable(port);
348 else
349 stm32_usart_tx_interrupt_enable(port);
350 }
351
stm32_usart_transmit_chars_dma(struct uart_port * port)352 static void stm32_usart_transmit_chars_dma(struct uart_port *port)
353 {
354 struct stm32_port *stm32port = to_stm32_port(port);
355 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
356 struct circ_buf *xmit = &port->state->xmit;
357 struct dma_async_tx_descriptor *desc = NULL;
358 unsigned int count, i;
359
360 if (stm32port->tx_dma_busy)
361 return;
362
363 stm32port->tx_dma_busy = true;
364
365 count = uart_circ_chars_pending(xmit);
366
367 if (count > TX_BUF_L)
368 count = TX_BUF_L;
369
370 if (xmit->tail < xmit->head) {
371 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
372 } else {
373 size_t one = UART_XMIT_SIZE - xmit->tail;
374 size_t two;
375
376 if (one > count)
377 one = count;
378 two = count - one;
379
380 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
381 if (two)
382 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
383 }
384
385 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
386 stm32port->tx_dma_buf,
387 count,
388 DMA_MEM_TO_DEV,
389 DMA_PREP_INTERRUPT);
390
391 if (!desc)
392 goto fallback_err;
393
394 desc->callback = stm32_usart_tx_dma_complete;
395 desc->callback_param = port;
396
397 /* Push current DMA TX transaction in the pending queue */
398 if (dma_submit_error(dmaengine_submit(desc))) {
399 /* dma no yet started, safe to free resources */
400 dmaengine_terminate_async(stm32port->tx_ch);
401 goto fallback_err;
402 }
403
404 /* Issue pending DMA TX requests */
405 dma_async_issue_pending(stm32port->tx_ch);
406
407 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
408
409 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
410 port->icount.tx += count;
411 return;
412
413 fallback_err:
414 for (i = count; i > 0; i--)
415 stm32_usart_transmit_chars_pio(port);
416 }
417
stm32_usart_transmit_chars(struct uart_port * port)418 static void stm32_usart_transmit_chars(struct uart_port *port)
419 {
420 struct stm32_port *stm32_port = to_stm32_port(port);
421 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
422 struct circ_buf *xmit = &port->state->xmit;
423
424 if (port->x_char) {
425 if (stm32_port->tx_dma_busy)
426 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
427 writel_relaxed(port->x_char, port->membase + ofs->tdr);
428 port->x_char = 0;
429 port->icount.tx++;
430 if (stm32_port->tx_dma_busy)
431 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
432 return;
433 }
434
435 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
436 stm32_usart_tx_interrupt_disable(port);
437 return;
438 }
439
440 if (ofs->icr == UNDEF_REG)
441 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
442 else
443 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
444
445 if (stm32_port->tx_ch)
446 stm32_usart_transmit_chars_dma(port);
447 else
448 stm32_usart_transmit_chars_pio(port);
449
450 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
451 uart_write_wakeup(port);
452
453 if (uart_circ_empty(xmit))
454 stm32_usart_tx_interrupt_disable(port);
455 }
456
stm32_usart_interrupt(int irq,void * ptr)457 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
458 {
459 struct uart_port *port = ptr;
460 struct tty_port *tport = &port->state->port;
461 struct stm32_port *stm32_port = to_stm32_port(port);
462 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
463 u32 sr;
464
465 sr = readl_relaxed(port->membase + ofs->isr);
466
467 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
468 writel_relaxed(USART_ICR_RTOCF,
469 port->membase + ofs->icr);
470
471 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
472 /* Clear wake up flag and disable wake up interrupt */
473 writel_relaxed(USART_ICR_WUCF,
474 port->membase + ofs->icr);
475 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
476 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
477 pm_wakeup_event(tport->tty->dev, 0);
478 }
479
480 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
481 stm32_usart_receive_chars(port, false);
482
483 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
484 spin_lock(&port->lock);
485 stm32_usart_transmit_chars(port);
486 spin_unlock(&port->lock);
487 }
488
489 if (stm32_port->rx_ch)
490 return IRQ_WAKE_THREAD;
491 else
492 return IRQ_HANDLED;
493 }
494
stm32_usart_threaded_interrupt(int irq,void * ptr)495 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
496 {
497 struct uart_port *port = ptr;
498 struct stm32_port *stm32_port = to_stm32_port(port);
499
500 if (stm32_port->rx_ch)
501 stm32_usart_receive_chars(port, true);
502
503 return IRQ_HANDLED;
504 }
505
stm32_usart_tx_empty(struct uart_port * port)506 static unsigned int stm32_usart_tx_empty(struct uart_port *port)
507 {
508 struct stm32_port *stm32_port = to_stm32_port(port);
509 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
510
511 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
512 return TIOCSER_TEMT;
513
514 return 0;
515 }
516
stm32_usart_set_mctrl(struct uart_port * port,unsigned int mctrl)517 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
518 {
519 struct stm32_port *stm32_port = to_stm32_port(port);
520 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
521
522 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
523 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
524 else
525 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
526
527 mctrl_gpio_set(stm32_port->gpios, mctrl);
528 }
529
stm32_usart_get_mctrl(struct uart_port * port)530 static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
531 {
532 struct stm32_port *stm32_port = to_stm32_port(port);
533 unsigned int ret;
534
535 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
536 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
537
538 return mctrl_gpio_get(stm32_port->gpios, &ret);
539 }
540
stm32_usart_enable_ms(struct uart_port * port)541 static void stm32_usart_enable_ms(struct uart_port *port)
542 {
543 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
544 }
545
stm32_usart_disable_ms(struct uart_port * port)546 static void stm32_usart_disable_ms(struct uart_port *port)
547 {
548 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
549 }
550
551 /* Transmit stop */
stm32_usart_stop_tx(struct uart_port * port)552 static void stm32_usart_stop_tx(struct uart_port *port)
553 {
554 struct stm32_port *stm32_port = to_stm32_port(port);
555 struct serial_rs485 *rs485conf = &port->rs485;
556
557 stm32_usart_tx_interrupt_disable(port);
558
559 if (rs485conf->flags & SER_RS485_ENABLED) {
560 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
561 mctrl_gpio_set(stm32_port->gpios,
562 stm32_port->port.mctrl & ~TIOCM_RTS);
563 } else {
564 mctrl_gpio_set(stm32_port->gpios,
565 stm32_port->port.mctrl | TIOCM_RTS);
566 }
567 }
568 }
569
570 /* There are probably characters waiting to be transmitted. */
stm32_usart_start_tx(struct uart_port * port)571 static void stm32_usart_start_tx(struct uart_port *port)
572 {
573 struct stm32_port *stm32_port = to_stm32_port(port);
574 struct serial_rs485 *rs485conf = &port->rs485;
575 struct circ_buf *xmit = &port->state->xmit;
576
577 if (uart_circ_empty(xmit) && !port->x_char)
578 return;
579
580 if (rs485conf->flags & SER_RS485_ENABLED) {
581 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
582 mctrl_gpio_set(stm32_port->gpios,
583 stm32_port->port.mctrl | TIOCM_RTS);
584 } else {
585 mctrl_gpio_set(stm32_port->gpios,
586 stm32_port->port.mctrl & ~TIOCM_RTS);
587 }
588 }
589
590 stm32_usart_transmit_chars(port);
591 }
592
593 /* Throttle the remote when input buffer is about to overflow. */
stm32_usart_throttle(struct uart_port * port)594 static void stm32_usart_throttle(struct uart_port *port)
595 {
596 struct stm32_port *stm32_port = to_stm32_port(port);
597 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
598 unsigned long flags;
599
600 spin_lock_irqsave(&port->lock, flags);
601 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
602 if (stm32_port->cr3_irq)
603 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
604
605 spin_unlock_irqrestore(&port->lock, flags);
606 }
607
608 /* Unthrottle the remote, the input buffer can now accept data. */
stm32_usart_unthrottle(struct uart_port * port)609 static void stm32_usart_unthrottle(struct uart_port *port)
610 {
611 struct stm32_port *stm32_port = to_stm32_port(port);
612 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
613 unsigned long flags;
614
615 spin_lock_irqsave(&port->lock, flags);
616 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
617 if (stm32_port->cr3_irq)
618 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
619
620 spin_unlock_irqrestore(&port->lock, flags);
621 }
622
623 /* Receive stop */
stm32_usart_stop_rx(struct uart_port * port)624 static void stm32_usart_stop_rx(struct uart_port *port)
625 {
626 struct stm32_port *stm32_port = to_stm32_port(port);
627 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
628
629 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
630 if (stm32_port->cr3_irq)
631 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
632 }
633
634 /* Handle breaks - ignored by us */
stm32_usart_break_ctl(struct uart_port * port,int break_state)635 static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
636 {
637 }
638
stm32_usart_startup(struct uart_port * port)639 static int stm32_usart_startup(struct uart_port *port)
640 {
641 struct stm32_port *stm32_port = to_stm32_port(port);
642 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
643 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
644 const char *name = to_platform_device(port->dev)->name;
645 u32 val;
646 int ret;
647
648 ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
649 stm32_usart_threaded_interrupt,
650 IRQF_ONESHOT | IRQF_NO_SUSPEND,
651 name, port);
652 if (ret)
653 return ret;
654
655 /* RX FIFO Flush */
656 if (ofs->rqr != UNDEF_REG)
657 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
658
659 /* RX enabling */
660 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
661 stm32_usart_set_bits(port, ofs->cr1, val);
662
663 return 0;
664 }
665
stm32_usart_shutdown(struct uart_port * port)666 static void stm32_usart_shutdown(struct uart_port *port)
667 {
668 struct stm32_port *stm32_port = to_stm32_port(port);
669 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
670 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
671 u32 val, isr;
672 int ret;
673
674 /* Disable modem control interrupts */
675 stm32_usart_disable_ms(port);
676
677 val = USART_CR1_TXEIE | USART_CR1_TE;
678 val |= stm32_port->cr1_irq | USART_CR1_RE;
679 val |= BIT(cfg->uart_enable_bit);
680 if (stm32_port->fifoen)
681 val |= USART_CR1_FIFOEN;
682
683 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
684 isr, (isr & USART_SR_TC),
685 10, 100000);
686
687 if (ret)
688 dev_err(port->dev, "transmission complete not set\n");
689
690 /* flush RX & TX FIFO */
691 if (ofs->rqr != UNDEF_REG)
692 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
693 port->membase + ofs->rqr);
694
695 stm32_usart_clr_bits(port, ofs->cr1, val);
696
697 free_irq(port->irq, port);
698 }
699
stm32_usart_get_databits(struct ktermios * termios)700 static unsigned int stm32_usart_get_databits(struct ktermios *termios)
701 {
702 unsigned int bits;
703
704 tcflag_t cflag = termios->c_cflag;
705
706 switch (cflag & CSIZE) {
707 /*
708 * CSIZE settings are not necessarily supported in hardware.
709 * CSIZE unsupported configurations are handled here to set word length
710 * to 8 bits word as default configuration and to print debug message.
711 */
712 case CS5:
713 bits = 5;
714 break;
715 case CS6:
716 bits = 6;
717 break;
718 case CS7:
719 bits = 7;
720 break;
721 /* default including CS8 */
722 default:
723 bits = 8;
724 break;
725 }
726
727 return bits;
728 }
729
stm32_usart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)730 static void stm32_usart_set_termios(struct uart_port *port,
731 struct ktermios *termios,
732 struct ktermios *old)
733 {
734 struct stm32_port *stm32_port = to_stm32_port(port);
735 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
736 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
737 struct serial_rs485 *rs485conf = &port->rs485;
738 unsigned int baud, bits;
739 u32 usartdiv, mantissa, fraction, oversampling;
740 tcflag_t cflag = termios->c_cflag;
741 u32 cr1, cr2, cr3, isr;
742 unsigned long flags;
743 int ret;
744
745 if (!stm32_port->hw_flow_control)
746 cflag &= ~CRTSCTS;
747
748 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
749
750 spin_lock_irqsave(&port->lock, flags);
751
752 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
753 isr,
754 (isr & USART_SR_TC),
755 10, 100000);
756
757 /* Send the TC error message only when ISR_TC is not set. */
758 if (ret)
759 dev_err(port->dev, "Transmission is not complete\n");
760
761 /* Stop serial port and reset value */
762 writel_relaxed(0, port->membase + ofs->cr1);
763
764 /* flush RX & TX FIFO */
765 if (ofs->rqr != UNDEF_REG)
766 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
767 port->membase + ofs->rqr);
768
769 cr1 = USART_CR1_TE | USART_CR1_RE;
770 if (stm32_port->fifoen)
771 cr1 |= USART_CR1_FIFOEN;
772 cr2 = 0;
773
774 /* Tx and RX FIFO configuration */
775 cr3 = readl_relaxed(port->membase + ofs->cr3);
776 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
777 if (stm32_port->fifoen) {
778 cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
779 cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
780 cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
781 }
782
783 if (cflag & CSTOPB)
784 cr2 |= USART_CR2_STOP_2B;
785
786 bits = stm32_usart_get_databits(termios);
787 stm32_port->rdr_mask = (BIT(bits) - 1);
788
789 if (cflag & PARENB) {
790 bits++;
791 cr1 |= USART_CR1_PCE;
792 }
793
794 /*
795 * Word length configuration:
796 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
797 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
798 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
799 * M0 and M1 already cleared by cr1 initialization.
800 */
801 if (bits == 9)
802 cr1 |= USART_CR1_M0;
803 else if ((bits == 7) && cfg->has_7bits_data)
804 cr1 |= USART_CR1_M1;
805 else if (bits != 8)
806 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
807 , bits);
808
809 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
810 stm32_port->fifoen)) {
811 if (cflag & CSTOPB)
812 bits = bits + 3; /* 1 start bit + 2 stop bits */
813 else
814 bits = bits + 2; /* 1 start bit + 1 stop bit */
815
816 /* RX timeout irq to occur after last stop bit + bits */
817 stm32_port->cr1_irq = USART_CR1_RTOIE;
818 writel_relaxed(bits, port->membase + ofs->rtor);
819 cr2 |= USART_CR2_RTOEN;
820 /* Not using dma, enable fifo threshold irq */
821 if (!stm32_port->rx_ch)
822 stm32_port->cr3_irq = USART_CR3_RXFTIE;
823 }
824
825 cr1 |= stm32_port->cr1_irq;
826 cr3 |= stm32_port->cr3_irq;
827
828 if (cflag & PARODD)
829 cr1 |= USART_CR1_PS;
830
831 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
832 if (cflag & CRTSCTS) {
833 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
834 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
835 }
836
837 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
838
839 /*
840 * The USART supports 16 or 8 times oversampling.
841 * By default we prefer 16 times oversampling, so that the receiver
842 * has a better tolerance to clock deviations.
843 * 8 times oversampling is only used to achieve higher speeds.
844 */
845 if (usartdiv < 16) {
846 oversampling = 8;
847 cr1 |= USART_CR1_OVER8;
848 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
849 } else {
850 oversampling = 16;
851 cr1 &= ~USART_CR1_OVER8;
852 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
853 }
854
855 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
856 fraction = usartdiv % oversampling;
857 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
858
859 uart_update_timeout(port, cflag, baud);
860
861 port->read_status_mask = USART_SR_ORE;
862 if (termios->c_iflag & INPCK)
863 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
864 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
865 port->read_status_mask |= USART_SR_FE;
866
867 /* Characters to ignore */
868 port->ignore_status_mask = 0;
869 if (termios->c_iflag & IGNPAR)
870 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
871 if (termios->c_iflag & IGNBRK) {
872 port->ignore_status_mask |= USART_SR_FE;
873 /*
874 * If we're ignoring parity and break indicators,
875 * ignore overruns too (for real raw support).
876 */
877 if (termios->c_iflag & IGNPAR)
878 port->ignore_status_mask |= USART_SR_ORE;
879 }
880
881 /* Ignore all characters if CREAD is not set */
882 if ((termios->c_cflag & CREAD) == 0)
883 port->ignore_status_mask |= USART_SR_DUMMY_RX;
884
885 if (stm32_port->rx_ch)
886 cr3 |= USART_CR3_DMAR;
887
888 if (rs485conf->flags & SER_RS485_ENABLED) {
889 stm32_usart_config_reg_rs485(&cr1, &cr3,
890 rs485conf->delay_rts_before_send,
891 rs485conf->delay_rts_after_send,
892 baud);
893 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
894 cr3 &= ~USART_CR3_DEP;
895 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
896 } else {
897 cr3 |= USART_CR3_DEP;
898 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
899 }
900
901 } else {
902 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
903 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
904 }
905
906 /* Configure wake up from low power on start bit detection */
907 if (stm32_port->wakeirq > 0) {
908 cr3 &= ~USART_CR3_WUS_MASK;
909 cr3 |= USART_CR3_WUS_START_BIT;
910 }
911
912 writel_relaxed(cr3, port->membase + ofs->cr3);
913 writel_relaxed(cr2, port->membase + ofs->cr2);
914 writel_relaxed(cr1, port->membase + ofs->cr1);
915
916 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
917 spin_unlock_irqrestore(&port->lock, flags);
918
919 /* Handle modem control interrupts */
920 if (UART_ENABLE_MS(port, termios->c_cflag))
921 stm32_usart_enable_ms(port);
922 else
923 stm32_usart_disable_ms(port);
924 }
925
stm32_usart_type(struct uart_port * port)926 static const char *stm32_usart_type(struct uart_port *port)
927 {
928 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
929 }
930
stm32_usart_release_port(struct uart_port * port)931 static void stm32_usart_release_port(struct uart_port *port)
932 {
933 }
934
stm32_usart_request_port(struct uart_port * port)935 static int stm32_usart_request_port(struct uart_port *port)
936 {
937 return 0;
938 }
939
stm32_usart_config_port(struct uart_port * port,int flags)940 static void stm32_usart_config_port(struct uart_port *port, int flags)
941 {
942 if (flags & UART_CONFIG_TYPE)
943 port->type = PORT_STM32;
944 }
945
946 static int
stm32_usart_verify_port(struct uart_port * port,struct serial_struct * ser)947 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
948 {
949 /* No user changeable parameters */
950 return -EINVAL;
951 }
952
stm32_usart_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)953 static void stm32_usart_pm(struct uart_port *port, unsigned int state,
954 unsigned int oldstate)
955 {
956 struct stm32_port *stm32port = container_of(port,
957 struct stm32_port, port);
958 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
959 const struct stm32_usart_config *cfg = &stm32port->info->cfg;
960 unsigned long flags = 0;
961
962 switch (state) {
963 case UART_PM_STATE_ON:
964 pm_runtime_get_sync(port->dev);
965 break;
966 case UART_PM_STATE_OFF:
967 spin_lock_irqsave(&port->lock, flags);
968 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
969 spin_unlock_irqrestore(&port->lock, flags);
970 pm_runtime_put_sync(port->dev);
971 break;
972 }
973 }
974
975 static const struct uart_ops stm32_uart_ops = {
976 .tx_empty = stm32_usart_tx_empty,
977 .set_mctrl = stm32_usart_set_mctrl,
978 .get_mctrl = stm32_usart_get_mctrl,
979 .stop_tx = stm32_usart_stop_tx,
980 .start_tx = stm32_usart_start_tx,
981 .throttle = stm32_usart_throttle,
982 .unthrottle = stm32_usart_unthrottle,
983 .stop_rx = stm32_usart_stop_rx,
984 .enable_ms = stm32_usart_enable_ms,
985 .break_ctl = stm32_usart_break_ctl,
986 .startup = stm32_usart_startup,
987 .shutdown = stm32_usart_shutdown,
988 .set_termios = stm32_usart_set_termios,
989 .pm = stm32_usart_pm,
990 .type = stm32_usart_type,
991 .release_port = stm32_usart_release_port,
992 .request_port = stm32_usart_request_port,
993 .config_port = stm32_usart_config_port,
994 .verify_port = stm32_usart_verify_port,
995 };
996
stm32_usart_init_port(struct stm32_port * stm32port,struct platform_device * pdev)997 static int stm32_usart_init_port(struct stm32_port *stm32port,
998 struct platform_device *pdev)
999 {
1000 struct uart_port *port = &stm32port->port;
1001 struct resource *res;
1002 int ret;
1003
1004 ret = platform_get_irq(pdev, 0);
1005 if (ret <= 0)
1006 return ret ? : -ENODEV;
1007
1008 port->iotype = UPIO_MEM;
1009 port->flags = UPF_BOOT_AUTOCONF;
1010 port->ops = &stm32_uart_ops;
1011 port->dev = &pdev->dev;
1012 port->fifosize = stm32port->info->cfg.fifosize;
1013 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1014 port->irq = ret;
1015 port->rs485_config = stm32_usart_config_rs485;
1016
1017 ret = stm32_usart_init_rs485(port, pdev);
1018 if (ret)
1019 return ret;
1020
1021 if (stm32port->info->cfg.has_wakeup) {
1022 stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
1023 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
1024 return stm32port->wakeirq ? : -ENODEV;
1025 }
1026
1027 stm32port->fifoen = stm32port->info->cfg.has_fifo;
1028
1029 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030 port->membase = devm_ioremap_resource(&pdev->dev, res);
1031 if (IS_ERR(port->membase))
1032 return PTR_ERR(port->membase);
1033 port->mapbase = res->start;
1034
1035 spin_lock_init(&port->lock);
1036
1037 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1038 if (IS_ERR(stm32port->clk))
1039 return PTR_ERR(stm32port->clk);
1040
1041 /* Ensure that clk rate is correct by enabling the clk */
1042 ret = clk_prepare_enable(stm32port->clk);
1043 if (ret)
1044 return ret;
1045
1046 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1047 if (!stm32port->port.uartclk) {
1048 ret = -EINVAL;
1049 goto err_clk;
1050 }
1051
1052 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1053 if (IS_ERR(stm32port->gpios)) {
1054 ret = PTR_ERR(stm32port->gpios);
1055 goto err_clk;
1056 }
1057
1058 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */
1059 if (stm32port->hw_flow_control) {
1060 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1061 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1062 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1063 ret = -EINVAL;
1064 goto err_clk;
1065 }
1066 }
1067
1068 return ret;
1069
1070 err_clk:
1071 clk_disable_unprepare(stm32port->clk);
1072
1073 return ret;
1074 }
1075
stm32_usart_of_get_port(struct platform_device * pdev)1076 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1077 {
1078 struct device_node *np = pdev->dev.of_node;
1079 int id;
1080
1081 if (!np)
1082 return NULL;
1083
1084 id = of_alias_get_id(np, "serial");
1085 if (id < 0) {
1086 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1087 return NULL;
1088 }
1089
1090 if (WARN_ON(id >= STM32_MAX_PORTS))
1091 return NULL;
1092
1093 stm32_ports[id].hw_flow_control =
1094 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1095 of_property_read_bool (np, "uart-has-rtscts");
1096 stm32_ports[id].port.line = id;
1097 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1098 stm32_ports[id].cr3_irq = 0;
1099 stm32_ports[id].last_res = RX_BUF_L;
1100 return &stm32_ports[id];
1101 }
1102
1103 #ifdef CONFIG_OF
1104 static const struct of_device_id stm32_match[] = {
1105 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1106 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1107 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1108 {},
1109 };
1110
1111 MODULE_DEVICE_TABLE(of, stm32_match);
1112 #endif
1113
stm32_usart_of_dma_rx_probe(struct stm32_port * stm32port,struct platform_device * pdev)1114 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1115 struct platform_device *pdev)
1116 {
1117 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1118 struct uart_port *port = &stm32port->port;
1119 struct device *dev = &pdev->dev;
1120 struct dma_slave_config config;
1121 struct dma_async_tx_descriptor *desc = NULL;
1122 int ret;
1123
1124 /*
1125 * Using DMA and threaded handler for the console could lead to
1126 * deadlocks.
1127 */
1128 if (uart_console(port))
1129 return -ENODEV;
1130
1131 /* Request DMA RX channel */
1132 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1133 if (!stm32port->rx_ch) {
1134 dev_info(dev, "rx dma alloc failed\n");
1135 return -ENODEV;
1136 }
1137 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1138 &stm32port->rx_dma_buf,
1139 GFP_KERNEL);
1140 if (!stm32port->rx_buf) {
1141 ret = -ENOMEM;
1142 goto alloc_err;
1143 }
1144
1145 /* Configure DMA channel */
1146 memset(&config, 0, sizeof(config));
1147 config.src_addr = port->mapbase + ofs->rdr;
1148 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1149
1150 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1151 if (ret < 0) {
1152 dev_err(dev, "rx dma channel config failed\n");
1153 ret = -ENODEV;
1154 goto config_err;
1155 }
1156
1157 /* Prepare a DMA cyclic transaction */
1158 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1159 stm32port->rx_dma_buf,
1160 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1161 DMA_PREP_INTERRUPT);
1162 if (!desc) {
1163 dev_err(dev, "rx dma prep cyclic failed\n");
1164 ret = -ENODEV;
1165 goto config_err;
1166 }
1167
1168 /* No callback as dma buffer is drained on usart interrupt */
1169 desc->callback = NULL;
1170 desc->callback_param = NULL;
1171
1172 /* Push current DMA transaction in the pending queue */
1173 ret = dma_submit_error(dmaengine_submit(desc));
1174 if (ret) {
1175 dmaengine_terminate_sync(stm32port->rx_ch);
1176 goto config_err;
1177 }
1178
1179 /* Issue pending DMA requests */
1180 dma_async_issue_pending(stm32port->rx_ch);
1181
1182 return 0;
1183
1184 config_err:
1185 dma_free_coherent(&pdev->dev,
1186 RX_BUF_L, stm32port->rx_buf,
1187 stm32port->rx_dma_buf);
1188
1189 alloc_err:
1190 dma_release_channel(stm32port->rx_ch);
1191 stm32port->rx_ch = NULL;
1192
1193 return ret;
1194 }
1195
stm32_usart_of_dma_tx_probe(struct stm32_port * stm32port,struct platform_device * pdev)1196 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1197 struct platform_device *pdev)
1198 {
1199 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1200 struct uart_port *port = &stm32port->port;
1201 struct device *dev = &pdev->dev;
1202 struct dma_slave_config config;
1203 int ret;
1204
1205 stm32port->tx_dma_busy = false;
1206
1207 /* Request DMA TX channel */
1208 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1209 if (!stm32port->tx_ch) {
1210 dev_info(dev, "tx dma alloc failed\n");
1211 return -ENODEV;
1212 }
1213 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1214 &stm32port->tx_dma_buf,
1215 GFP_KERNEL);
1216 if (!stm32port->tx_buf) {
1217 ret = -ENOMEM;
1218 goto alloc_err;
1219 }
1220
1221 /* Configure DMA channel */
1222 memset(&config, 0, sizeof(config));
1223 config.dst_addr = port->mapbase + ofs->tdr;
1224 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1225
1226 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1227 if (ret < 0) {
1228 dev_err(dev, "tx dma channel config failed\n");
1229 ret = -ENODEV;
1230 goto config_err;
1231 }
1232
1233 return 0;
1234
1235 config_err:
1236 dma_free_coherent(&pdev->dev,
1237 TX_BUF_L, stm32port->tx_buf,
1238 stm32port->tx_dma_buf);
1239
1240 alloc_err:
1241 dma_release_channel(stm32port->tx_ch);
1242 stm32port->tx_ch = NULL;
1243
1244 return ret;
1245 }
1246
stm32_usart_serial_probe(struct platform_device * pdev)1247 static int stm32_usart_serial_probe(struct platform_device *pdev)
1248 {
1249 struct stm32_port *stm32port;
1250 int ret;
1251
1252 stm32port = stm32_usart_of_get_port(pdev);
1253 if (!stm32port)
1254 return -ENODEV;
1255
1256 stm32port->info = of_device_get_match_data(&pdev->dev);
1257 if (!stm32port->info)
1258 return -EINVAL;
1259
1260 ret = stm32_usart_init_port(stm32port, pdev);
1261 if (ret)
1262 return ret;
1263
1264 if (stm32port->wakeirq > 0) {
1265 ret = device_init_wakeup(&pdev->dev, true);
1266 if (ret)
1267 goto err_uninit;
1268
1269 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1270 stm32port->wakeirq);
1271 if (ret)
1272 goto err_nowup;
1273
1274 device_set_wakeup_enable(&pdev->dev, false);
1275 }
1276
1277 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
1278 if (ret)
1279 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1280
1281 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
1282 if (ret)
1283 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1284
1285 platform_set_drvdata(pdev, &stm32port->port);
1286
1287 pm_runtime_get_noresume(&pdev->dev);
1288 pm_runtime_set_active(&pdev->dev);
1289 pm_runtime_enable(&pdev->dev);
1290
1291 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1292 if (ret)
1293 goto err_port;
1294
1295 pm_runtime_put_sync(&pdev->dev);
1296
1297 return 0;
1298
1299 err_port:
1300 pm_runtime_disable(&pdev->dev);
1301 pm_runtime_set_suspended(&pdev->dev);
1302 pm_runtime_put_noidle(&pdev->dev);
1303
1304 if (stm32port->rx_ch) {
1305 dmaengine_terminate_async(stm32port->rx_ch);
1306 dma_release_channel(stm32port->rx_ch);
1307 }
1308
1309 if (stm32port->rx_dma_buf)
1310 dma_free_coherent(&pdev->dev,
1311 RX_BUF_L, stm32port->rx_buf,
1312 stm32port->rx_dma_buf);
1313
1314 if (stm32port->tx_ch) {
1315 dmaengine_terminate_async(stm32port->tx_ch);
1316 dma_release_channel(stm32port->tx_ch);
1317 }
1318
1319 if (stm32port->tx_dma_buf)
1320 dma_free_coherent(&pdev->dev,
1321 TX_BUF_L, stm32port->tx_buf,
1322 stm32port->tx_dma_buf);
1323
1324 if (stm32port->wakeirq > 0)
1325 dev_pm_clear_wake_irq(&pdev->dev);
1326
1327 err_nowup:
1328 if (stm32port->wakeirq > 0)
1329 device_init_wakeup(&pdev->dev, false);
1330
1331 err_uninit:
1332 clk_disable_unprepare(stm32port->clk);
1333
1334 return ret;
1335 }
1336
stm32_usart_serial_remove(struct platform_device * pdev)1337 static int stm32_usart_serial_remove(struct platform_device *pdev)
1338 {
1339 struct uart_port *port = platform_get_drvdata(pdev);
1340 struct stm32_port *stm32_port = to_stm32_port(port);
1341 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1342 int err;
1343
1344 pm_runtime_get_sync(&pdev->dev);
1345 err = uart_remove_one_port(&stm32_usart_driver, port);
1346 if (err)
1347 return(err);
1348
1349 pm_runtime_disable(&pdev->dev);
1350 pm_runtime_set_suspended(&pdev->dev);
1351 pm_runtime_put_noidle(&pdev->dev);
1352
1353 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1354
1355 if (stm32_port->rx_ch) {
1356 dmaengine_terminate_async(stm32_port->rx_ch);
1357 dma_release_channel(stm32_port->rx_ch);
1358 }
1359
1360 if (stm32_port->rx_dma_buf)
1361 dma_free_coherent(&pdev->dev,
1362 RX_BUF_L, stm32_port->rx_buf,
1363 stm32_port->rx_dma_buf);
1364
1365 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1366
1367 if (stm32_port->tx_ch) {
1368 dmaengine_terminate_async(stm32_port->tx_ch);
1369 dma_release_channel(stm32_port->tx_ch);
1370 }
1371
1372 if (stm32_port->tx_dma_buf)
1373 dma_free_coherent(&pdev->dev,
1374 TX_BUF_L, stm32_port->tx_buf,
1375 stm32_port->tx_dma_buf);
1376
1377 if (stm32_port->wakeirq > 0) {
1378 dev_pm_clear_wake_irq(&pdev->dev);
1379 device_init_wakeup(&pdev->dev, false);
1380 }
1381
1382 clk_disable_unprepare(stm32_port->clk);
1383
1384 return 0;
1385 }
1386
1387 #ifdef CONFIG_SERIAL_STM32_CONSOLE
stm32_usart_console_putchar(struct uart_port * port,int ch)1388 static void stm32_usart_console_putchar(struct uart_port *port, int ch)
1389 {
1390 struct stm32_port *stm32_port = to_stm32_port(port);
1391 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1392
1393 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1394 cpu_relax();
1395
1396 writel_relaxed(ch, port->membase + ofs->tdr);
1397 }
1398
stm32_usart_console_write(struct console * co,const char * s,unsigned int cnt)1399 static void stm32_usart_console_write(struct console *co, const char *s,
1400 unsigned int cnt)
1401 {
1402 struct uart_port *port = &stm32_ports[co->index].port;
1403 struct stm32_port *stm32_port = to_stm32_port(port);
1404 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1405 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1406 unsigned long flags;
1407 u32 old_cr1, new_cr1;
1408 int locked = 1;
1409
1410 local_irq_save(flags);
1411 if (port->sysrq)
1412 locked = 0;
1413 else if (oops_in_progress)
1414 locked = spin_trylock(&port->lock);
1415 else
1416 spin_lock(&port->lock);
1417
1418 /* Save and disable interrupts, enable the transmitter */
1419 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1420 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1421 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1422 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1423
1424 uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1425
1426 /* Restore interrupt state */
1427 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1428
1429 if (locked)
1430 spin_unlock(&port->lock);
1431 local_irq_restore(flags);
1432 }
1433
stm32_usart_console_setup(struct console * co,char * options)1434 static int stm32_usart_console_setup(struct console *co, char *options)
1435 {
1436 struct stm32_port *stm32port;
1437 int baud = 9600;
1438 int bits = 8;
1439 int parity = 'n';
1440 int flow = 'n';
1441
1442 if (co->index >= STM32_MAX_PORTS)
1443 return -ENODEV;
1444
1445 stm32port = &stm32_ports[co->index];
1446
1447 /*
1448 * This driver does not support early console initialization
1449 * (use ARM early printk support instead), so we only expect
1450 * this to be called during the uart port registration when the
1451 * driver gets probed and the port should be mapped at that point.
1452 */
1453 if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1454 return -ENXIO;
1455
1456 if (options)
1457 uart_parse_options(options, &baud, &parity, &bits, &flow);
1458
1459 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1460 }
1461
1462 static struct console stm32_console = {
1463 .name = STM32_SERIAL_NAME,
1464 .device = uart_console_device,
1465 .write = stm32_usart_console_write,
1466 .setup = stm32_usart_console_setup,
1467 .flags = CON_PRINTBUFFER,
1468 .index = -1,
1469 .data = &stm32_usart_driver,
1470 };
1471
1472 #define STM32_SERIAL_CONSOLE (&stm32_console)
1473
1474 #else
1475 #define STM32_SERIAL_CONSOLE NULL
1476 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1477
1478 static struct uart_driver stm32_usart_driver = {
1479 .driver_name = DRIVER_NAME,
1480 .dev_name = STM32_SERIAL_NAME,
1481 .major = 0,
1482 .minor = 0,
1483 .nr = STM32_MAX_PORTS,
1484 .cons = STM32_SERIAL_CONSOLE,
1485 };
1486
stm32_usart_serial_en_wakeup(struct uart_port * port,bool enable)1487 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1488 bool enable)
1489 {
1490 struct stm32_port *stm32_port = to_stm32_port(port);
1491 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1492
1493 if (stm32_port->wakeirq <= 0)
1494 return;
1495
1496 /*
1497 * Enable low-power wake-up and wake-up irq if argument is set to
1498 * "enable", disable low-power wake-up and wake-up irq otherwise
1499 */
1500 if (enable) {
1501 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1502 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
1503 } else {
1504 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1505 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
1506 }
1507 }
1508
stm32_usart_serial_suspend(struct device * dev)1509 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
1510 {
1511 struct uart_port *port = dev_get_drvdata(dev);
1512
1513 uart_suspend_port(&stm32_usart_driver, port);
1514
1515 if (device_may_wakeup(dev))
1516 stm32_usart_serial_en_wakeup(port, true);
1517 else
1518 stm32_usart_serial_en_wakeup(port, false);
1519
1520 /*
1521 * When "no_console_suspend" is enabled, keep the pinctrl default state
1522 * and rely on bootloader stage to restore this state upon resume.
1523 * Otherwise, apply the idle or sleep states depending on wakeup
1524 * capabilities.
1525 */
1526 if (console_suspend_enabled || !uart_console(port)) {
1527 if (device_may_wakeup(dev))
1528 pinctrl_pm_select_idle_state(dev);
1529 else
1530 pinctrl_pm_select_sleep_state(dev);
1531 }
1532
1533 return 0;
1534 }
1535
stm32_usart_serial_resume(struct device * dev)1536 static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
1537 {
1538 struct uart_port *port = dev_get_drvdata(dev);
1539
1540 pinctrl_pm_select_default_state(dev);
1541
1542 if (device_may_wakeup(dev))
1543 stm32_usart_serial_en_wakeup(port, false);
1544
1545 return uart_resume_port(&stm32_usart_driver, port);
1546 }
1547
stm32_usart_runtime_suspend(struct device * dev)1548 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1549 {
1550 struct uart_port *port = dev_get_drvdata(dev);
1551 struct stm32_port *stm32port = container_of(port,
1552 struct stm32_port, port);
1553
1554 clk_disable_unprepare(stm32port->clk);
1555
1556 return 0;
1557 }
1558
stm32_usart_runtime_resume(struct device * dev)1559 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
1560 {
1561 struct uart_port *port = dev_get_drvdata(dev);
1562 struct stm32_port *stm32port = container_of(port,
1563 struct stm32_port, port);
1564
1565 return clk_prepare_enable(stm32port->clk);
1566 }
1567
1568 static const struct dev_pm_ops stm32_serial_pm_ops = {
1569 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
1570 stm32_usart_runtime_resume, NULL)
1571 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
1572 stm32_usart_serial_resume)
1573 };
1574
1575 static struct platform_driver stm32_serial_driver = {
1576 .probe = stm32_usart_serial_probe,
1577 .remove = stm32_usart_serial_remove,
1578 .driver = {
1579 .name = DRIVER_NAME,
1580 .pm = &stm32_serial_pm_ops,
1581 .of_match_table = of_match_ptr(stm32_match),
1582 },
1583 };
1584
stm32_usart_init(void)1585 static int __init stm32_usart_init(void)
1586 {
1587 static char banner[] __initdata = "STM32 USART driver initialized";
1588 int ret;
1589
1590 pr_info("%s\n", banner);
1591
1592 ret = uart_register_driver(&stm32_usart_driver);
1593 if (ret)
1594 return ret;
1595
1596 ret = platform_driver_register(&stm32_serial_driver);
1597 if (ret)
1598 uart_unregister_driver(&stm32_usart_driver);
1599
1600 return ret;
1601 }
1602
stm32_usart_exit(void)1603 static void __exit stm32_usart_exit(void)
1604 {
1605 platform_driver_unregister(&stm32_serial_driver);
1606 uart_unregister_driver(&stm32_usart_driver);
1607 }
1608
1609 module_init(stm32_usart_init);
1610 module_exit(stm32_usart_exit);
1611
1612 MODULE_ALIAS("platform:" DRIVER_NAME);
1613 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1614 MODULE_LICENSE("GPL v2");
1615